driver-core: remove sysdev.h usage.
[linux-2.6-block.git] / arch / arm / mach-s5pv210 / clock.c
CommitLineData
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1/* linux/arch/arm/mach-s5pv210/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
edbaa603 20#include <linux/device.h>
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21#include <linux/io.h>
22
23#include <mach/map.h>
24
25#include <plat/cpu-freq.h>
26#include <mach/regs-clock.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/pll.h>
30#include <plat/s5p-clock.h>
31#include <plat/clock-clksrc.h>
32#include <plat/s5pv210.h>
33
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34static unsigned long xtal;
35
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36static struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
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39 },
40 .sources = &clk_src_apll,
41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
42};
43
44static struct clksrc_clk clk_mout_epll = {
45 .clk = {
46 .name = "mout_epll",
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47 },
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
50};
51
52static struct clksrc_clk clk_mout_mpll = {
53 .clk = {
54 .name = "mout_mpll",
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55 },
56 .sources = &clk_src_mpll,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
58};
59
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60static struct clk *clkset_armclk_list[] = {
61 [0] = &clk_mout_apll.clk,
62 [1] = &clk_mout_mpll.clk,
63};
64
65static struct clksrc_sources clkset_armclk = {
66 .sources = clkset_armclk_list,
67 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
68};
69
70static struct clksrc_clk clk_armclk = {
71 .clk = {
72 .name = "armclk",
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73 },
74 .sources = &clkset_armclk,
75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
76 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
77};
78
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79static struct clksrc_clk clk_hclk_msys = {
80 .clk = {
81 .name = "hclk_msys",
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82 .parent = &clk_armclk.clk,
83 },
84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
85};
86
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87static struct clksrc_clk clk_pclk_msys = {
88 .clk = {
89 .name = "pclk_msys",
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90 .parent = &clk_hclk_msys.clk,
91 },
92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
93};
94
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95static struct clksrc_clk clk_sclk_a2m = {
96 .clk = {
97 .name = "sclk_a2m",
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98 .parent = &clk_mout_apll.clk,
99 },
100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
101};
102
103static struct clk *clkset_hclk_sys_list[] = {
104 [0] = &clk_mout_mpll.clk,
105 [1] = &clk_sclk_a2m.clk,
106};
107
108static struct clksrc_sources clkset_hclk_sys = {
109 .sources = clkset_hclk_sys_list,
110 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
111};
112
113static struct clksrc_clk clk_hclk_dsys = {
114 .clk = {
115 .name = "hclk_dsys",
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116 },
117 .sources = &clkset_hclk_sys,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
120};
121
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122static struct clksrc_clk clk_pclk_dsys = {
123 .clk = {
124 .name = "pclk_dsys",
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125 .parent = &clk_hclk_dsys.clk,
126 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
128};
129
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130static struct clksrc_clk clk_hclk_psys = {
131 .clk = {
132 .name = "hclk_psys",
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133 },
134 .sources = &clkset_hclk_sys,
135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
137};
138
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139static struct clksrc_clk clk_pclk_psys = {
140 .clk = {
141 .name = "pclk_psys",
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142 .parent = &clk_hclk_psys.clk,
143 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
145};
146
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147static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
148{
149 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
150}
151
152static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
153{
154 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
155}
156
157static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
158{
159 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
160}
161
162static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
163{
164 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
165}
166
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167static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
168{
169 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
170}
171
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172static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
173{
174 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
175}
176
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177static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
178{
179 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
180}
181
182static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
183{
184 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
185}
186
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187static struct clk clk_sclk_hdmi27m = {
188 .name = "sclk_hdmi27m",
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189 .rate = 27000000,
190};
191
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192static struct clk clk_sclk_hdmiphy = {
193 .name = "sclk_hdmiphy",
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194};
195
196static struct clk clk_sclk_usbphy0 = {
197 .name = "sclk_usbphy0",
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198};
199
200static struct clk clk_sclk_usbphy1 = {
201 .name = "sclk_usbphy1",
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202};
203
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204static struct clk clk_pcmcdclk0 = {
205 .name = "pcmcdclk",
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206};
207
208static struct clk clk_pcmcdclk1 = {
209 .name = "pcmcdclk",
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210};
211
212static struct clk clk_pcmcdclk2 = {
213 .name = "pcmcdclk",
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214};
215
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216static struct clk dummy_apb_pclk = {
217 .name = "apb_pclk",
218 .id = -1,
219};
220
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221static struct clk *clkset_vpllsrc_list[] = {
222 [0] = &clk_fin_vpll,
223 [1] = &clk_sclk_hdmi27m,
224};
225
226static struct clksrc_sources clkset_vpllsrc = {
227 .sources = clkset_vpllsrc_list,
228 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
229};
230
231static struct clksrc_clk clk_vpllsrc = {
232 .clk = {
233 .name = "vpll_src",
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234 .enable = s5pv210_clk_mask0_ctrl,
235 .ctrlbit = (1 << 7),
236 },
237 .sources = &clkset_vpllsrc,
238 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
239};
240
241static struct clk *clkset_sclk_vpll_list[] = {
242 [0] = &clk_vpllsrc.clk,
243 [1] = &clk_fout_vpll,
244};
245
246static struct clksrc_sources clkset_sclk_vpll = {
247 .sources = clkset_sclk_vpll_list,
248 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
249};
250
251static struct clksrc_clk clk_sclk_vpll = {
252 .clk = {
253 .name = "sclk_vpll",
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254 },
255 .sources = &clkset_sclk_vpll,
256 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
257};
258
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259static struct clk *clkset_moutdmc0src_list[] = {
260 [0] = &clk_sclk_a2m.clk,
261 [1] = &clk_mout_mpll.clk,
262 [2] = NULL,
263 [3] = NULL,
264};
265
266static struct clksrc_sources clkset_moutdmc0src = {
267 .sources = clkset_moutdmc0src_list,
268 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
269};
270
271static struct clksrc_clk clk_mout_dmc0 = {
272 .clk = {
273 .name = "mout_dmc0",
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274 },
275 .sources = &clkset_moutdmc0src,
276 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
277};
278
279static struct clksrc_clk clk_sclk_dmc0 = {
280 .clk = {
281 .name = "sclk_dmc0",
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282 .parent = &clk_mout_dmc0.clk,
283 },
284 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
285};
286
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287static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
288{
289 return clk_get_rate(clk->parent) / 2;
290}
291
292static struct clk_ops clk_hclk_imem_ops = {
293 .get_rate = s5pv210_clk_imem_get_rate,
294};
295
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296static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
297{
298 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
299}
300
301static struct clk_ops clk_fout_apll_ops = {
302 .get_rate = s5pv210_clk_fout_apll_get_rate,
303};
304
3c0fa647 305static struct clk init_clocks_off[] = {
0c1945d3 306 {
dafc9543 307 .name = "dma",
1ce3ea61 308 .devname = "dma-pl330.0",
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309 .parent = &clk_hclk_psys.clk,
310 .enable = s5pv210_clk_ip0_ctrl,
311 .ctrlbit = (1 << 3),
312 }, {
dafc9543 313 .name = "dma",
1ce3ea61 314 .devname = "dma-pl330.1",
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315 .parent = &clk_hclk_psys.clk,
316 .enable = s5pv210_clk_ip0_ctrl,
317 .ctrlbit = (1 << 4),
318 }, {
0c1945d3 319 .name = "rot",
0fe967a1 320 .parent = &clk_hclk_dsys.clk,
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321 .enable = s5pv210_clk_ip0_ctrl,
322 .ctrlbit = (1<<29),
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323 }, {
324 .name = "fimc",
b2a9dd46 325 .devname = "s5pv210-fimc.0",
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326 .parent = &clk_hclk_dsys.clk,
327 .enable = s5pv210_clk_ip0_ctrl,
328 .ctrlbit = (1 << 24),
329 }, {
330 .name = "fimc",
b2a9dd46 331 .devname = "s5pv210-fimc.1",
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332 .parent = &clk_hclk_dsys.clk,
333 .enable = s5pv210_clk_ip0_ctrl,
334 .ctrlbit = (1 << 25),
335 }, {
336 .name = "fimc",
b2a9dd46 337 .devname = "s5pv210-fimc.2",
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338 .parent = &clk_hclk_dsys.clk,
339 .enable = s5pv210_clk_ip0_ctrl,
340 .ctrlbit = (1 << 26),
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341 }, {
342 .name = "mfc",
343 .devname = "s5p-mfc",
344 .parent = &clk_pclk_psys.clk,
345 .enable = s5pv210_clk_ip0_ctrl,
346 .ctrlbit = (1 << 16),
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347 }, {
348 .name = "dac",
349 .devname = "s5p-sdo",
350 .parent = &clk_hclk_dsys.clk,
351 .enable = s5pv210_clk_ip1_ctrl,
352 .ctrlbit = (1 << 10),
353 }, {
354 .name = "mixer",
355 .devname = "s5p-mixer",
356 .parent = &clk_hclk_dsys.clk,
357 .enable = s5pv210_clk_ip1_ctrl,
358 .ctrlbit = (1 << 9),
359 }, {
360 .name = "vp",
361 .devname = "s5p-mixer",
362 .parent = &clk_hclk_dsys.clk,
363 .enable = s5pv210_clk_ip1_ctrl,
364 .ctrlbit = (1 << 8),
365 }, {
366 .name = "hdmi",
367 .devname = "s5pv210-hdmi",
368 .parent = &clk_hclk_dsys.clk,
369 .enable = s5pv210_clk_ip1_ctrl,
370 .ctrlbit = (1 << 11),
371 }, {
372 .name = "hdmiphy",
373 .devname = "s5pv210-hdmi",
374 .enable = exynos4_clk_hdmiphy_ctrl,
375 .ctrlbit = (1 << 0),
376 }, {
377 .name = "dacphy",
378 .devname = "s5p-sdo",
379 .enable = exynos4_clk_dac_ctrl,
380 .ctrlbit = (1 << 0),
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381 }, {
382 .name = "otg",
acfa245f 383 .parent = &clk_hclk_psys.clk,
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384 .enable = s5pv210_clk_ip1_ctrl,
385 .ctrlbit = (1<<16),
386 }, {
387 .name = "usb-host",
acfa245f 388 .parent = &clk_hclk_psys.clk,
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389 .enable = s5pv210_clk_ip1_ctrl,
390 .ctrlbit = (1<<17),
391 }, {
392 .name = "lcd",
0fe967a1 393 .parent = &clk_hclk_dsys.clk,
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394 .enable = s5pv210_clk_ip1_ctrl,
395 .ctrlbit = (1<<0),
396 }, {
397 .name = "cfcon",
acfa245f 398 .parent = &clk_hclk_psys.clk,
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399 .enable = s5pv210_clk_ip1_ctrl,
400 .ctrlbit = (1<<25),
401 }, {
402 .name = "hsmmc",
b2a9dd46 403 .devname = "s3c-sdhci.0",
acfa245f 404 .parent = &clk_hclk_psys.clk,
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405 .enable = s5pv210_clk_ip2_ctrl,
406 .ctrlbit = (1<<16),
407 }, {
408 .name = "hsmmc",
b2a9dd46 409 .devname = "s3c-sdhci.1",
acfa245f 410 .parent = &clk_hclk_psys.clk,
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411 .enable = s5pv210_clk_ip2_ctrl,
412 .ctrlbit = (1<<17),
413 }, {
414 .name = "hsmmc",
b2a9dd46 415 .devname = "s3c-sdhci.2",
acfa245f 416 .parent = &clk_hclk_psys.clk,
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417 .enable = s5pv210_clk_ip2_ctrl,
418 .ctrlbit = (1<<18),
419 }, {
420 .name = "hsmmc",
b2a9dd46 421 .devname = "s3c-sdhci.3",
acfa245f 422 .parent = &clk_hclk_psys.clk,
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423 .enable = s5pv210_clk_ip2_ctrl,
424 .ctrlbit = (1<<19),
425 }, {
426 .name = "systimer",
f44cf78b 427 .parent = &clk_pclk_psys.clk,
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428 .enable = s5pv210_clk_ip3_ctrl,
429 .ctrlbit = (1<<16),
430 }, {
431 .name = "watchdog",
f44cf78b 432 .parent = &clk_pclk_psys.clk,
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433 .enable = s5pv210_clk_ip3_ctrl,
434 .ctrlbit = (1<<22),
435 }, {
436 .name = "rtc",
f44cf78b 437 .parent = &clk_pclk_psys.clk,
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438 .enable = s5pv210_clk_ip3_ctrl,
439 .ctrlbit = (1<<15),
440 }, {
441 .name = "i2c",
b2a9dd46 442 .devname = "s3c2440-i2c.0",
f44cf78b 443 .parent = &clk_pclk_psys.clk,
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444 .enable = s5pv210_clk_ip3_ctrl,
445 .ctrlbit = (1<<7),
446 }, {
447 .name = "i2c",
b2a9dd46 448 .devname = "s3c2440-i2c.1",
f44cf78b 449 .parent = &clk_pclk_psys.clk,
0c1945d3 450 .enable = s5pv210_clk_ip3_ctrl,
f1c894de 451 .ctrlbit = (1 << 10),
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452 }, {
453 .name = "i2c",
b2a9dd46 454 .devname = "s3c2440-i2c.2",
f44cf78b 455 .parent = &clk_pclk_psys.clk,
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456 .enable = s5pv210_clk_ip3_ctrl,
457 .ctrlbit = (1<<9),
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458 }, {
459 .name = "i2c",
460 .devname = "s3c2440-hdmiphy-i2c",
461 .parent = &clk_pclk_psys.clk,
462 .enable = s5pv210_clk_ip3_ctrl,
463 .ctrlbit = (1 << 11),
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464 }, {
465 .name = "spi",
b2a9dd46 466 .devname = "s3c64xx-spi.0",
f44cf78b 467 .parent = &clk_pclk_psys.clk,
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468 .enable = s5pv210_clk_ip3_ctrl,
469 .ctrlbit = (1<<12),
470 }, {
471 .name = "spi",
b2a9dd46 472 .devname = "s3c64xx-spi.1",
f44cf78b 473 .parent = &clk_pclk_psys.clk,
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474 .enable = s5pv210_clk_ip3_ctrl,
475 .ctrlbit = (1<<13),
476 }, {
477 .name = "spi",
b2a9dd46 478 .devname = "s3c64xx-spi.2",
f44cf78b 479 .parent = &clk_pclk_psys.clk,
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480 .enable = s5pv210_clk_ip3_ctrl,
481 .ctrlbit = (1<<14),
482 }, {
483 .name = "timers",
f44cf78b 484 .parent = &clk_pclk_psys.clk,
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485 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1<<23),
487 }, {
488 .name = "adc",
f44cf78b 489 .parent = &clk_pclk_psys.clk,
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490 .enable = s5pv210_clk_ip3_ctrl,
491 .ctrlbit = (1<<24),
492 }, {
493 .name = "keypad",
f44cf78b 494 .parent = &clk_pclk_psys.clk,
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495 .enable = s5pv210_clk_ip3_ctrl,
496 .ctrlbit = (1<<21),
497 }, {
9aa2570e 498 .name = "iis",
b2a9dd46 499 .devname = "samsung-i2s.0",
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500 .parent = &clk_p,
501 .enable = s5pv210_clk_ip3_ctrl,
502 .ctrlbit = (1<<4),
503 }, {
9aa2570e 504 .name = "iis",
b2a9dd46 505 .devname = "samsung-i2s.1",
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506 .parent = &clk_p,
507 .enable = s5pv210_clk_ip3_ctrl,
154d62e4 508 .ctrlbit = (1 << 5),
0c1945d3 509 }, {
9aa2570e 510 .name = "iis",
b2a9dd46 511 .devname = "samsung-i2s.2",
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512 .parent = &clk_p,
513 .enable = s5pv210_clk_ip3_ctrl,
154d62e4 514 .ctrlbit = (1 << 6),
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515 }, {
516 .name = "spdif",
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517 .parent = &clk_p,
518 .enable = s5pv210_clk_ip3_ctrl,
519 .ctrlbit = (1 << 0),
154d62e4 520 },
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521};
522
523static struct clk init_clocks[] = {
524 {
664f5b20 525 .name = "hclk_imem",
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526 .parent = &clk_hclk_msys.clk,
527 .ctrlbit = (1 << 5),
528 .enable = s5pv210_clk_ip0_ctrl,
529 .ops = &clk_hclk_imem_ops,
530 }, {
0c1945d3 531 .name = "uart",
b2a9dd46 532 .devname = "s5pv210-uart.0",
f44cf78b 533 .parent = &clk_pclk_psys.clk,
0c1945d3 534 .enable = s5pv210_clk_ip3_ctrl,
154d62e4 535 .ctrlbit = (1 << 17),
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536 }, {
537 .name = "uart",
b2a9dd46 538 .devname = "s5pv210-uart.1",
f44cf78b 539 .parent = &clk_pclk_psys.clk,
0c1945d3 540 .enable = s5pv210_clk_ip3_ctrl,
154d62e4 541 .ctrlbit = (1 << 18),
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542 }, {
543 .name = "uart",
b2a9dd46 544 .devname = "s5pv210-uart.2",
f44cf78b 545 .parent = &clk_pclk_psys.clk,
0c1945d3 546 .enable = s5pv210_clk_ip3_ctrl,
154d62e4 547 .ctrlbit = (1 << 19),
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548 }, {
549 .name = "uart",
b2a9dd46 550 .devname = "s5pv210-uart.3",
f44cf78b 551 .parent = &clk_pclk_psys.clk,
0c1945d3 552 .enable = s5pv210_clk_ip3_ctrl,
154d62e4 553 .ctrlbit = (1 << 20),
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554 }, {
555 .name = "sromc",
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TA
556 .parent = &clk_hclk_psys.clk,
557 .enable = s5pv210_clk_ip1_ctrl,
558 .ctrlbit = (1 << 26),
0c1945d3
KK
559 },
560};
561
0c1945d3
KK
562static struct clk *clkset_uart_list[] = {
563 [6] = &clk_mout_mpll.clk,
564 [7] = &clk_mout_epll.clk,
565};
566
567static struct clksrc_sources clkset_uart = {
568 .sources = clkset_uart_list,
569 .nr_sources = ARRAY_SIZE(clkset_uart_list),
570};
571
2cf4c2e6
TA
572static struct clk *clkset_group1_list[] = {
573 [0] = &clk_sclk_a2m.clk,
574 [1] = &clk_mout_mpll.clk,
575 [2] = &clk_mout_epll.clk,
576 [3] = &clk_sclk_vpll.clk,
577};
578
579static struct clksrc_sources clkset_group1 = {
580 .sources = clkset_group1_list,
581 .nr_sources = ARRAY_SIZE(clkset_group1_list),
582};
583
584static struct clk *clkset_sclk_onenand_list[] = {
585 [0] = &clk_hclk_psys.clk,
586 [1] = &clk_hclk_dsys.clk,
587};
588
589static struct clksrc_sources clkset_sclk_onenand = {
590 .sources = clkset_sclk_onenand_list,
591 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
592};
593
9e20614b
TA
594static struct clk *clkset_sclk_dac_list[] = {
595 [0] = &clk_sclk_vpll.clk,
596 [1] = &clk_sclk_hdmiphy,
597};
598
599static struct clksrc_sources clkset_sclk_dac = {
600 .sources = clkset_sclk_dac_list,
601 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
602};
603
604static struct clksrc_clk clk_sclk_dac = {
605 .clk = {
606 .name = "sclk_dac",
154d62e4
MH
607 .enable = s5pv210_clk_mask0_ctrl,
608 .ctrlbit = (1 << 2),
9e20614b
TA
609 },
610 .sources = &clkset_sclk_dac,
611 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
612};
613
614static struct clksrc_clk clk_sclk_pixel = {
615 .clk = {
616 .name = "sclk_pixel",
9e20614b
TA
617 .parent = &clk_sclk_vpll.clk,
618 },
619 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
620};
621
622static struct clk *clkset_sclk_hdmi_list[] = {
623 [0] = &clk_sclk_pixel.clk,
624 [1] = &clk_sclk_hdmiphy,
625};
626
627static struct clksrc_sources clkset_sclk_hdmi = {
628 .sources = clkset_sclk_hdmi_list,
629 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
630};
631
632static struct clksrc_clk clk_sclk_hdmi = {
633 .clk = {
634 .name = "sclk_hdmi",
154d62e4
MH
635 .enable = s5pv210_clk_mask0_ctrl,
636 .ctrlbit = (1 << 0),
9e20614b
TA
637 },
638 .sources = &clkset_sclk_hdmi,
639 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
640};
641
642static struct clk *clkset_sclk_mixer_list[] = {
643 [0] = &clk_sclk_dac.clk,
644 [1] = &clk_sclk_hdmi.clk,
645};
646
647static struct clksrc_sources clkset_sclk_mixer = {
648 .sources = clkset_sclk_mixer_list,
649 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
650};
651
fbf05563
TS
652static struct clksrc_clk clk_sclk_mixer = {
653 .clk = {
654 .name = "sclk_mixer",
655 .enable = s5pv210_clk_mask0_ctrl,
656 .ctrlbit = (1 << 1),
657 },
658 .sources = &clkset_sclk_mixer,
659 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
660};
661
662static struct clksrc_clk *sclk_tv[] = {
663 &clk_sclk_dac,
664 &clk_sclk_pixel,
665 &clk_sclk_hdmi,
666 &clk_sclk_mixer,
667};
668
4583487c
TA
669static struct clk *clkset_sclk_audio0_list[] = {
670 [0] = &clk_ext_xtal_mux,
671 [1] = &clk_pcmcdclk0,
672 [2] = &clk_sclk_hdmi27m,
673 [3] = &clk_sclk_usbphy0,
674 [4] = &clk_sclk_usbphy1,
675 [5] = &clk_sclk_hdmiphy,
676 [6] = &clk_mout_mpll.clk,
677 [7] = &clk_mout_epll.clk,
678 [8] = &clk_sclk_vpll.clk,
679};
680
681static struct clksrc_sources clkset_sclk_audio0 = {
682 .sources = clkset_sclk_audio0_list,
683 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
684};
685
686static struct clksrc_clk clk_sclk_audio0 = {
687 .clk = {
688 .name = "sclk_audio",
b2a9dd46 689 .devname = "soc-audio.0",
154d62e4
MH
690 .enable = s5pv210_clk_mask0_ctrl,
691 .ctrlbit = (1 << 24),
4583487c
TA
692 },
693 .sources = &clkset_sclk_audio0,
694 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
695 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
696};
697
698static struct clk *clkset_sclk_audio1_list[] = {
699 [0] = &clk_ext_xtal_mux,
700 [1] = &clk_pcmcdclk1,
701 [2] = &clk_sclk_hdmi27m,
702 [3] = &clk_sclk_usbphy0,
703 [4] = &clk_sclk_usbphy1,
704 [5] = &clk_sclk_hdmiphy,
705 [6] = &clk_mout_mpll.clk,
706 [7] = &clk_mout_epll.clk,
707 [8] = &clk_sclk_vpll.clk,
708};
709
710static struct clksrc_sources clkset_sclk_audio1 = {
711 .sources = clkset_sclk_audio1_list,
712 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
713};
714
715static struct clksrc_clk clk_sclk_audio1 = {
716 .clk = {
717 .name = "sclk_audio",
b2a9dd46 718 .devname = "soc-audio.1",
154d62e4
MH
719 .enable = s5pv210_clk_mask0_ctrl,
720 .ctrlbit = (1 << 25),
4583487c
TA
721 },
722 .sources = &clkset_sclk_audio1,
723 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
724 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
725};
726
727static struct clk *clkset_sclk_audio2_list[] = {
728 [0] = &clk_ext_xtal_mux,
729 [1] = &clk_pcmcdclk0,
730 [2] = &clk_sclk_hdmi27m,
731 [3] = &clk_sclk_usbphy0,
732 [4] = &clk_sclk_usbphy1,
733 [5] = &clk_sclk_hdmiphy,
734 [6] = &clk_mout_mpll.clk,
735 [7] = &clk_mout_epll.clk,
736 [8] = &clk_sclk_vpll.clk,
737};
738
739static struct clksrc_sources clkset_sclk_audio2 = {
740 .sources = clkset_sclk_audio2_list,
741 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
742};
743
744static struct clksrc_clk clk_sclk_audio2 = {
745 .clk = {
746 .name = "sclk_audio",
b2a9dd46 747 .devname = "soc-audio.2",
154d62e4
MH
748 .enable = s5pv210_clk_mask0_ctrl,
749 .ctrlbit = (1 << 26),
4583487c
TA
750 },
751 .sources = &clkset_sclk_audio2,
752 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
753 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
754};
755
756static struct clk *clkset_sclk_spdif_list[] = {
757 [0] = &clk_sclk_audio0.clk,
758 [1] = &clk_sclk_audio1.clk,
759 [2] = &clk_sclk_audio2.clk,
760};
761
762static struct clksrc_sources clkset_sclk_spdif = {
763 .sources = clkset_sclk_spdif_list,
764 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
765};
766
aa21ae3d
SY
767static struct clksrc_clk clk_sclk_spdif = {
768 .clk = {
769 .name = "sclk_spdif",
aa21ae3d
SY
770 .enable = s5pv210_clk_mask0_ctrl,
771 .ctrlbit = (1 << 27),
65f5eaa2 772 .ops = &s5p_sclk_spdif_ops,
aa21ae3d
SY
773 },
774 .sources = &clkset_sclk_spdif,
775 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
776};
777
f64cacc3
TA
778static struct clk *clkset_group2_list[] = {
779 [0] = &clk_ext_xtal_mux,
780 [1] = &clk_xusbxti,
781 [2] = &clk_sclk_hdmi27m,
782 [3] = &clk_sclk_usbphy0,
783 [4] = &clk_sclk_usbphy1,
784 [5] = &clk_sclk_hdmiphy,
785 [6] = &clk_mout_mpll.clk,
786 [7] = &clk_mout_epll.clk,
787 [8] = &clk_sclk_vpll.clk,
788};
789
790static struct clksrc_sources clkset_group2 = {
791 .sources = clkset_group2_list,
792 .nr_sources = ARRAY_SIZE(clkset_group2_list),
793};
794
0c1945d3
KK
795static struct clksrc_clk clksrcs[] = {
796 {
2cf4c2e6
TA
797 .clk = {
798 .name = "sclk_dmc",
2cf4c2e6
TA
799 },
800 .sources = &clkset_group1,
801 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
802 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
803 }, {
804 .clk = {
805 .name = "sclk_onenand",
2cf4c2e6
TA
806 },
807 .sources = &clkset_sclk_onenand,
808 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
809 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
810 }, {
0c1945d3
KK
811 .clk = {
812 .name = "uclk1",
b2a9dd46 813 .devname = "s5pv210-uart.0",
154d62e4
MH
814 .enable = s5pv210_clk_mask0_ctrl,
815 .ctrlbit = (1 << 12),
0c1945d3
KK
816 },
817 .sources = &clkset_uart,
818 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
819 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
f64cacc3
TA
820 }, {
821 .clk = {
822 .name = "uclk1",
b2a9dd46 823 .devname = "s5pv210-uart.1",
154d62e4
MH
824 .enable = s5pv210_clk_mask0_ctrl,
825 .ctrlbit = (1 << 13),
f64cacc3
TA
826 },
827 .sources = &clkset_uart,
828 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
830 }, {
831 .clk = {
832 .name = "uclk1",
b2a9dd46 833 .devname = "s5pv210-uart.2",
154d62e4
MH
834 .enable = s5pv210_clk_mask0_ctrl,
835 .ctrlbit = (1 << 14),
f64cacc3
TA
836 },
837 .sources = &clkset_uart,
838 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
839 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
840 }, {
841 .clk = {
842 .name = "uclk1",
b2a9dd46 843 .devname = "s5pv210-uart.3",
154d62e4
MH
844 .enable = s5pv210_clk_mask0_ctrl,
845 .ctrlbit = (1 << 15),
f64cacc3
TA
846 },
847 .sources = &clkset_uart,
848 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
849 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
f64cacc3
TA
850 }, {
851 .clk = {
852 .name = "sclk_fimc",
b2a9dd46 853 .devname = "s5pv210-fimc.0",
154d62e4
MH
854 .enable = s5pv210_clk_mask1_ctrl,
855 .ctrlbit = (1 << 2),
f64cacc3
TA
856 },
857 .sources = &clkset_group2,
858 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
859 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
860 }, {
861 .clk = {
862 .name = "sclk_fimc",
b2a9dd46 863 .devname = "s5pv210-fimc.1",
154d62e4
MH
864 .enable = s5pv210_clk_mask1_ctrl,
865 .ctrlbit = (1 << 3),
f64cacc3
TA
866 },
867 .sources = &clkset_group2,
868 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
869 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
870 }, {
871 .clk = {
872 .name = "sclk_fimc",
b2a9dd46 873 .devname = "s5pv210-fimc.2",
154d62e4
MH
874 .enable = s5pv210_clk_mask1_ctrl,
875 .ctrlbit = (1 << 4),
f64cacc3
TA
876 },
877 .sources = &clkset_group2,
878 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
879 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
880 }, {
881 .clk = {
83427c23 882 .name = "sclk_cam0",
154d62e4
MH
883 .enable = s5pv210_clk_mask0_ctrl,
884 .ctrlbit = (1 << 3),
f64cacc3
TA
885 },
886 .sources = &clkset_group2,
887 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
888 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
889 }, {
890 .clk = {
83427c23 891 .name = "sclk_cam1",
154d62e4
MH
892 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 4),
f64cacc3
TA
894 },
895 .sources = &clkset_group2,
896 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
897 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
898 }, {
899 .clk = {
900 .name = "sclk_fimd",
154d62e4
MH
901 .enable = s5pv210_clk_mask0_ctrl,
902 .ctrlbit = (1 << 5),
f64cacc3
TA
903 },
904 .sources = &clkset_group2,
905 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
906 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
907 }, {
908 .clk = {
909 .name = "sclk_mmc",
b2a9dd46 910 .devname = "s3c-sdhci.0",
154d62e4
MH
911 .enable = s5pv210_clk_mask0_ctrl,
912 .ctrlbit = (1 << 8),
f64cacc3
TA
913 },
914 .sources = &clkset_group2,
915 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
916 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
917 }, {
918 .clk = {
919 .name = "sclk_mmc",
b2a9dd46 920 .devname = "s3c-sdhci.1",
154d62e4
MH
921 .enable = s5pv210_clk_mask0_ctrl,
922 .ctrlbit = (1 << 9),
f64cacc3
TA
923 },
924 .sources = &clkset_group2,
925 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
926 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
927 }, {
928 .clk = {
929 .name = "sclk_mmc",
b2a9dd46 930 .devname = "s3c-sdhci.2",
154d62e4
MH
931 .enable = s5pv210_clk_mask0_ctrl,
932 .ctrlbit = (1 << 10),
f64cacc3
TA
933 },
934 .sources = &clkset_group2,
935 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
936 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
937 }, {
938 .clk = {
939 .name = "sclk_mmc",
b2a9dd46 940 .devname = "s3c-sdhci.3",
154d62e4
MH
941 .enable = s5pv210_clk_mask0_ctrl,
942 .ctrlbit = (1 << 11),
f64cacc3
TA
943 },
944 .sources = &clkset_group2,
945 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
946 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
947 }, {
948 .clk = {
949 .name = "sclk_mfc",
0f75a96b 950 .devname = "s5p-mfc",
f64cacc3
TA
951 .enable = s5pv210_clk_ip0_ctrl,
952 .ctrlbit = (1 << 16),
953 },
954 .sources = &clkset_group1,
955 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
956 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
957 }, {
958 .clk = {
959 .name = "sclk_g2d",
f64cacc3
TA
960 .enable = s5pv210_clk_ip0_ctrl,
961 .ctrlbit = (1 << 12),
962 },
963 .sources = &clkset_group1,
964 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
965 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
966 }, {
967 .clk = {
968 .name = "sclk_g3d",
f64cacc3
TA
969 .enable = s5pv210_clk_ip0_ctrl,
970 .ctrlbit = (1 << 8),
971 },
972 .sources = &clkset_group1,
973 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
974 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
975 }, {
976 .clk = {
977 .name = "sclk_csis",
154d62e4
MH
978 .enable = s5pv210_clk_mask0_ctrl,
979 .ctrlbit = (1 << 6),
f64cacc3
TA
980 },
981 .sources = &clkset_group2,
982 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
983 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
984 }, {
985 .clk = {
986 .name = "sclk_spi",
b2a9dd46 987 .devname = "s3c64xx-spi.0",
154d62e4
MH
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 16),
f64cacc3
TA
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
994 }, {
995 .clk = {
996 .name = "sclk_spi",
b2a9dd46 997 .devname = "s3c64xx-spi.1",
154d62e4
MH
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 17),
f64cacc3
TA
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1004 }, {
1005 .clk = {
1006 .name = "sclk_pwi",
154d62e4
MH
1007 .enable = s5pv210_clk_mask0_ctrl,
1008 .ctrlbit = (1 << 29),
f64cacc3
TA
1009 },
1010 .sources = &clkset_group2,
1011 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
1012 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
1013 }, {
1014 .clk = {
1015 .name = "sclk_pwm",
154d62e4
MH
1016 .enable = s5pv210_clk_mask0_ctrl,
1017 .ctrlbit = (1 << 19),
f64cacc3
TA
1018 },
1019 .sources = &clkset_group2,
1020 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
1021 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
9e20614b 1022 },
0c1945d3
KK
1023};
1024
1025/* Clock initialisation code */
eb1ef1ed 1026static struct clksrc_clk *sysclks[] = {
0c1945d3
KK
1027 &clk_mout_apll,
1028 &clk_mout_epll,
1029 &clk_mout_mpll,
374e0bf5 1030 &clk_armclk,
af76a201 1031 &clk_hclk_msys,
0fe967a1
TA
1032 &clk_sclk_a2m,
1033 &clk_hclk_dsys,
acfa245f 1034 &clk_hclk_psys,
6ed91a20 1035 &clk_pclk_msys,
58772cd3 1036 &clk_pclk_dsys,
f44cf78b 1037 &clk_pclk_psys,
f445dbd5
TA
1038 &clk_vpllsrc,
1039 &clk_sclk_vpll,
08f49d11
JL
1040 &clk_mout_dmc0,
1041 &clk_sclk_dmc0,
900fa019
SY
1042 &clk_sclk_audio0,
1043 &clk_sclk_audio1,
1044 &clk_sclk_audio2,
1045 &clk_sclk_spdif,
0c1945d3
KK
1046};
1047
c9fa7a08
SY
1048static u32 epll_div[][6] = {
1049 { 48000000, 0, 48, 3, 3, 0 },
1050 { 96000000, 0, 48, 3, 2, 0 },
1051 { 144000000, 1, 72, 3, 2, 0 },
1052 { 192000000, 0, 48, 3, 1, 0 },
1053 { 288000000, 1, 72, 3, 1, 0 },
1054 { 32750000, 1, 65, 3, 4, 35127 },
1055 { 32768000, 1, 65, 3, 4, 35127 },
1056 { 45158400, 0, 45, 3, 3, 10355 },
1057 { 45000000, 0, 45, 3, 3, 10355 },
1058 { 45158000, 0, 45, 3, 3, 10355 },
1059 { 49125000, 0, 49, 3, 3, 9961 },
1060 { 49152000, 0, 49, 3, 3, 9961 },
1061 { 67737600, 1, 67, 3, 3, 48366 },
1062 { 67738000, 1, 67, 3, 3, 48366 },
1063 { 73800000, 1, 73, 3, 3, 47710 },
1064 { 73728000, 1, 73, 3, 3, 47710 },
1065 { 36000000, 1, 32, 3, 4, 0 },
1066 { 60000000, 1, 60, 3, 3, 0 },
1067 { 72000000, 1, 72, 3, 3, 0 },
1068 { 80000000, 1, 80, 3, 3, 0 },
1069 { 84000000, 0, 42, 3, 2, 0 },
1070 { 50000000, 0, 50, 3, 3, 0 },
1071};
1072
1073static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1074{
1075 unsigned int epll_con, epll_con_k;
1076 unsigned int i;
1077
1078 /* Return if nothing changed */
1079 if (clk->rate == rate)
1080 return 0;
1081
1082 epll_con = __raw_readl(S5P_EPLL_CON);
1083 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1084
1085 epll_con_k &= ~PLL46XX_KDIV_MASK;
1086 epll_con &= ~(1 << 27 |
1087 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1088 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1089 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1090
1091 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1092 if (epll_div[i][0] == rate) {
1093 epll_con_k |= epll_div[i][5] << 0;
1094 epll_con |= (epll_div[i][1] << 27 |
1095 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1096 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1097 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1098 break;
1099 }
1100 }
1101
1102 if (i == ARRAY_SIZE(epll_div)) {
1103 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1104 __func__);
1105 return -EINVAL;
1106 }
1107
1108 __raw_writel(epll_con, S5P_EPLL_CON);
1109 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1110
9616674a
SY
1111 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1112 clk->rate, rate);
1113
c9fa7a08
SY
1114 clk->rate = rate;
1115
1116 return 0;
1117}
1118
1119static struct clk_ops s5pv210_epll_ops = {
1120 .set_rate = s5pv210_epll_set_rate,
1121 .get_rate = s5p_epll_get_rate,
1122};
1123
fbf05563
TS
1124static u32 vpll_div[][5] = {
1125 { 54000000, 3, 53, 3, 0 },
1126 { 108000000, 3, 53, 2, 0 },
1127};
1128
1129static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
1130{
1131 return clk->rate;
1132}
1133
1134static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
1135{
1136 unsigned int vpll_con;
1137 unsigned int i;
1138
1139 /* Return if nothing changed */
1140 if (clk->rate == rate)
1141 return 0;
1142
1143 vpll_con = __raw_readl(S5P_VPLL_CON);
1144 vpll_con &= ~(0x1 << 27 | \
1145 PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
1146 PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
1147 PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
1148
1149 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1150 if (vpll_div[i][0] == rate) {
1151 vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
1152 vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
1153 vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
1154 vpll_con |= vpll_div[i][4] << 27;
1155 break;
1156 }
1157 }
1158
1159 if (i == ARRAY_SIZE(vpll_div)) {
1160 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1161 __func__);
1162 return -EINVAL;
1163 }
1164
1165 __raw_writel(vpll_con, S5P_VPLL_CON);
1166
1167 /* Wait for VPLL lock */
1168 while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
1169 continue;
1170
1171 clk->rate = rate;
1172 return 0;
1173}
1174static struct clk_ops s5pv210_vpll_ops = {
1175 .get_rate = s5pv210_vpll_get_rate,
1176 .set_rate = s5pv210_vpll_set_rate,
1177};
1178
0c1945d3
KK
1179void __init_or_cpufreq s5pv210_setup_clocks(void)
1180{
1181 struct clk *xtal_clk;
f445dbd5 1182 unsigned long vpllsrc;
0c1945d3 1183 unsigned long armclk;
af76a201 1184 unsigned long hclk_msys;
0fe967a1 1185 unsigned long hclk_dsys;
acfa245f 1186 unsigned long hclk_psys;
6ed91a20 1187 unsigned long pclk_msys;
58772cd3 1188 unsigned long pclk_dsys;
f44cf78b 1189 unsigned long pclk_psys;
0c1945d3
KK
1190 unsigned long apll;
1191 unsigned long mpll;
1192 unsigned long epll;
f445dbd5 1193 unsigned long vpll;
0c1945d3
KK
1194 unsigned int ptr;
1195 u32 clkdiv0, clkdiv1;
1196
c9fa7a08
SY
1197 /* Set functions for clk_fout_epll */
1198 clk_fout_epll.enable = s5p_epll_enable;
1199 clk_fout_epll.ops = &s5pv210_epll_ops;
1200
0c1945d3
KK
1201 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1202
1203 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1204 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1205
1206 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1207 __func__, clkdiv0, clkdiv1);
1208
1209 xtal_clk = clk_get(NULL, "xtal");
1210 BUG_ON(IS_ERR(xtal_clk));
1211
1212 xtal = clk_get_rate(xtal_clk);
1213 clk_put(xtal_clk);
1214
1215 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1216
1217 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1218 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
42a6e20e
SY
1219 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1220 __raw_readl(S5P_EPLL_CON1), pll_4600);
f445dbd5
TA
1221 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1222 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
0c1945d3 1223
88695843 1224 clk_fout_apll.ops = &clk_fout_apll_ops;
c62ec6a9
TA
1225 clk_fout_mpll.rate = mpll;
1226 clk_fout_epll.rate = epll;
fbf05563 1227 clk_fout_vpll.ops = &s5pv210_vpll_ops;
f445dbd5 1228 clk_fout_vpll.rate = vpll;
c62ec6a9 1229
f445dbd5
TA
1230 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1231 apll, mpll, epll, vpll);
0c1945d3 1232
374e0bf5 1233 armclk = clk_get_rate(&clk_armclk.clk);
af76a201 1234 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
0fe967a1 1235 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
acfa245f 1236 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
6ed91a20 1237 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
58772cd3 1238 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
f44cf78b 1239 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
0c1945d3 1240
acfa245f
TA
1241 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1242 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1243 armclk, hclk_msys, hclk_dsys, hclk_psys,
f44cf78b 1244 pclk_msys, pclk_dsys, pclk_psys);
0c1945d3 1245
0c1945d3 1246 clk_f.rate = armclk;
acfa245f 1247 clk_h.rate = hclk_psys;
f44cf78b 1248 clk_p.rate = pclk_psys;
0c1945d3 1249
0c1945d3
KK
1250 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1251 s3c_set_clksrc(&clksrcs[ptr], true);
1252}
1253
1254static struct clk *clks[] __initdata = {
f445dbd5 1255 &clk_sclk_hdmi27m,
2cf4c2e6
TA
1256 &clk_sclk_hdmiphy,
1257 &clk_sclk_usbphy0,
1258 &clk_sclk_usbphy1,
4583487c
TA
1259 &clk_pcmcdclk0,
1260 &clk_pcmcdclk1,
1261 &clk_pcmcdclk2,
0c1945d3
KK
1262};
1263
1264void __init s5pv210_register_clocks(void)
1265{
0c1945d3
KK
1266 int ptr;
1267
3c0fa647 1268 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
0c1945d3 1269
eb1ef1ed
TA
1270 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1271 s3c_register_clksrc(sysclks[ptr], 1);
1272
fbf05563
TS
1273 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1274 s3c_register_clksrc(sclk_tv[ptr], 1);
1275
0c1945d3
KK
1276 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1277 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1278
3c0fa647
KK
1279 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1280 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
0c1945d3 1281
dafc9543 1282 s3c24xx_register_clock(&dummy_apb_pclk);
0c1945d3
KK
1283 s3c_pwmclk_init();
1284}