[linux-2.6-block.git] / arch / arm / mach-s5p64x0 / clock-s5p6450.c

/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * S5P6450 - Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>

#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6450.h>

static struct clksrc_clk clk_mout_dpll = {
	.clk	= {
		.name		= "mout_dpll",
	},
	.sources	= &clk_src_dpll,
	.reg_src	= { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
};

static u32 epll_div[][5] = {
	{ 133000000,	27307,	55, 2, 2 },
	{ 100000000,	43691,	41, 2, 2 },
	{ 480000000,	0,	80, 2, 0 },
};

static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned int epll_con, epll_con_k;
	unsigned int i;

	if (clk->rate == rate)	/* Return if nothing changed */
		return 0;

	epll_con = __raw_readl(S5P64X0_EPLL_CON);
	epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);

	epll_con_k &= ~(PLL90XX_KDIV_MASK);
	epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);

	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
		 if (epll_div[i][0] == rate) {
			epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
			epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
				    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
				    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
			break;
		}
	}

	if (i == ARRAY_SIZE(epll_div)) {
		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
		return -EINVAL;
	}

	__raw_writel(epll_con, S5P64X0_EPLL_CON);
	__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);

	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
			clk->rate, rate);

	clk->rate = rate;

	return 0;
}

static struct clk_ops s5p6450_epll_ops = {
	.get_rate = s5p_epll_get_rate,
	.set_rate = s5p6450_epll_set_rate,
};

static struct clksrc_clk clk_dout_epll = {
	.clk	= {
		.name		= "dout_epll",
		.parent		= &clk_mout_epll.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
};

static struct clksrc_clk clk_mout_hclk_sel = {
	.clk	= {
		.name		= "mout_hclk_sel",
	},
	.sources	= &clkset_hclk_low,
	.reg_src	= { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
};

static struct clk *clkset_hclk_list[] = {
	&clk_mout_hclk_sel.clk,
	&clk_armclk.clk,
};

static struct clksrc_sources clkset_hclk = {
	.sources	= clkset_hclk_list,
	.nr_sources	= ARRAY_SIZE(clkset_hclk_list),
};

static struct clksrc_clk clk_hclk = {
	.clk	= {
		.name		= "clk_hclk",
	},
	.sources	= &clkset_hclk,
	.reg_src	= { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
	.reg_div	= { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
};

static struct clksrc_clk clk_pclk = {
	.clk	= {
		.name		= "clk_pclk",
		.parent		= &clk_hclk.clk,
	},
	.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clksrc_clk clk_dout_pwm_ratio0 = {
	.clk	= {
		.name		= "clk_dout_pwm_ratio0",
		.parent		= &clk_mout_hclk_sel.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
};

static struct clksrc_clk clk_pclk_to_wdt_pwm = {
	.clk	= {
		.name		= "clk_pclk_to_wdt_pwm",
		.parent		= &clk_dout_pwm_ratio0.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
};

static struct clksrc_clk clk_hclk_low = {
	.clk	= {
		.name		= "clk_hclk_low",
	},
	.sources	= &clkset_hclk_low,
	.reg_src	= { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
	.reg_div	= { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
};

static struct clksrc_clk clk_pclk_low = {
	.clk	= {
		.name		= "clk_pclk_low",
		.parent		= &clk_hclk_low.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
};

/*
 * The following clocks will be disabled during clock initialization. It is
 * recommended to keep the following clocks disabled until the driver requests
 * for enabling the clock.
 */
static struct clk init_clocks_off[] = {
	{
		.name		= "usbhost",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "dma",
		.devname	= "dma-pl330",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 12),
	}, {
		.name		= "hsmmc",
		.devname	= "s3c-sdhci.0",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 17),
	}, {
		.name		= "hsmmc",
		.devname	= "s3c-sdhci.1",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 18),
	}, {
		.name		= "hsmmc",
		.devname	= "s3c-sdhci.2",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 19),
	}, {
		.name		= "usbotg",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 20),
	}, {
		.name		= "lcd",
		.parent		= &clk_h,
		.enable		= s5p64x0_hclk1_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "watchdog",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 5),
	}, {
		.name		= "rtc",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 6),
	}, {
		.name		= "adc",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 12),
	}, {
		.name		= "i2c",
		.devname	= "s3c2440-i2c.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 17),
	}, {
		.name		= "spi",
		.devname	= "s3c64xx-spi.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 21),
	}, {
		.name		= "spi",
		.devname	= "s3c64xx-spi.1",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 22),
	}, {
		.name		= "iis",
		.devname	= "samsung-i2s.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 26),
	}, {
		.name		= "iis",
		.devname	= "samsung-i2s.1",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 15),
	}, {
		.name		= "iis",
		.devname	= "samsung-i2s.2",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 16),
	}, {
		.name		= "i2c",
		.devname	= "s3c2440-i2c.1",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 27),
	}, {
		.name		= "dmc0",
		.parent		= &clk_pclk.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 30),
	}
};

/*
 * The following clocks will be enabled during clock initialization.
 */
static struct clk init_clocks[] = {
	{
		.name		= "intc",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "mem",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 21),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.1",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.2",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.3",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "timers",
		.parent		= &clk_pclk_to_wdt_pwm.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 7),
	}, {
		.name		= "gpio",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 18),
	},
};

static struct clk *clkset_uart_list[] = {
	&clk_dout_epll.clk,
	&clk_dout_mpll.clk,
};

static struct clksrc_sources clkset_uart = {
	.sources	= clkset_uart_list,
	.nr_sources	= ARRAY_SIZE(clkset_uart_list),
};

static struct clk *clkset_mali_list[] = {
	&clk_mout_epll.clk,
	&clk_mout_apll.clk,
	&clk_mout_mpll.clk,
};

static struct clksrc_sources clkset_mali = {
	.sources	= clkset_mali_list,
	.nr_sources	= ARRAY_SIZE(clkset_mali_list),
};

static struct clk *clkset_group2_list[] = {
	&clk_dout_epll.clk,
	&clk_dout_mpll.clk,
	&clk_ext_xtal_mux,
};

static struct clksrc_sources clkset_group2 = {
	.sources	= clkset_group2_list,
	.nr_sources	= ARRAY_SIZE(clkset_group2_list),
};

static struct clk *clkset_dispcon_list[] = {
	&clk_dout_epll.clk,
	&clk_dout_mpll.clk,
	&clk_ext_xtal_mux,
	&clk_mout_dpll.clk,
};

static struct clksrc_sources clkset_dispcon = {
	.sources	= clkset_dispcon_list,
	.nr_sources	= ARRAY_SIZE(clkset_dispcon_list),
};

static struct clk *clkset_hsmmc44_list[] = {
	&clk_dout_epll.clk,
	&clk_dout_mpll.clk,
	&clk_ext_xtal_mux,
	&s5p_clk_27m,
	&clk_48m,
};

static struct clksrc_sources clkset_hsmmc44 = {
	.sources	= clkset_hsmmc44_list,
	.nr_sources	= ARRAY_SIZE(clkset_hsmmc44_list),
};

static struct clk *clkset_sclk_audio0_list[] = {
	[0] = &clk_dout_epll.clk,
	[1] = &clk_dout_mpll.clk,
	[2] = &clk_ext_xtal_mux,
	[3] = NULL,
	[4] = NULL,
};

static struct clksrc_sources clkset_sclk_audio0 = {
	.sources	= clkset_sclk_audio0_list,
	.nr_sources	= ARRAY_SIZE(clkset_sclk_audio0_list),
};

static struct clksrc_clk clk_sclk_audio0 = {
	.clk		= {
		.name		= "audio-bus",
		.enable		= s5p64x0_sclk_ctrl,
		.ctrlbit	= (1 << 8),
		.parent		= &clk_dout_epll.clk,
	},
	.sources	= &clkset_sclk_audio0,
	.reg_src	= { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
	.reg_div	= { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "sclk_mmc",
			.devname	= "s3c-sdhci.0",
			.ctrlbit	= (1 << 24),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_mmc",
			.devname	= "s3c-sdhci.1",
			.ctrlbit	= (1 << 25),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_mmc",
			.devname	= "s3c-sdhci.2",
			.ctrlbit	= (1 << 26),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_fimc",
			.ctrlbit	= (1 << 10),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
	}, {
		.clk	= {
			.name		= "aclk_mali",
			.ctrlbit	= (1 << 2),
			.enable		= s5p64x0_sclk1_ctrl,
		},
		.sources = &clkset_mali,
		.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_2d",
			.ctrlbit	= (1 << 12),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_mali,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_usi",
			.ctrlbit	= (1 << 7),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_camif",
			.ctrlbit	= (1 << 6),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_dispcon",
			.ctrlbit	= (1 << 1),
			.enable		= s5p64x0_sclk1_ctrl,
		},
		.sources = &clkset_dispcon,
		.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_hsmmc44",
			.ctrlbit	= (1 << 30),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_hsmmc44,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
	},
};

static struct clksrc_clk clk_sclk_uclk = {
	.clk	= {
		.name		= "uclk1",
		.ctrlbit	= (1 << 5),
		.enable		= s5p64x0_sclk_ctrl,
	},
	.sources = &clkset_uart,
	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
};

static struct clksrc_clk clk_sclk_spi0 = {
	.clk	= {
		.name		= "sclk_spi",
		.devname	= "s3c64xx-spi.0",
		.ctrlbit	= (1 << 20),
		.enable		= s5p64x0_sclk_ctrl,
	},
	.sources = &clkset_group2,
	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
};

static struct clksrc_clk clk_sclk_spi1 = {
	.clk	= {
		.name		= "sclk_spi",
		.devname	= "s3c64xx-spi.1",
		.ctrlbit	= (1 << 21),
		.enable		= s5p64x0_sclk_ctrl,
	},
	.sources = &clkset_group2,
	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
};

static struct clksrc_clk *clksrc_cdev[] = {
	&clk_sclk_uclk,
	&clk_sclk_spi0,
	&clk_sclk_spi1,
};

static struct clk_lookup s5p6450_clk_lookup[] = {
	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
};

/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
	&clk_mout_apll,
	&clk_mout_epll,
	&clk_dout_epll,
	&clk_mout_mpll,
	&clk_dout_mpll,
	&clk_armclk,
	&clk_mout_hclk_sel,
	&clk_dout_pwm_ratio0,
	&clk_pclk_to_wdt_pwm,
	&clk_hclk,
	&clk_pclk,
	&clk_hclk_low,
	&clk_pclk_low,
	&clk_sclk_audio0,
};

static struct clk dummy_apb_pclk = {
	.name		= "apb_pclk",
	.id		= -1,
};

void __init_or_cpufreq s5p6450_setup_clocks(void)
{
	struct clk *xtal_clk;

	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk_low;
	unsigned long pclk;
	unsigned long pclk_low;

	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long dpll;
	unsigned int ptr;

	/* Set S5P6450 functions for clk_fout_epll */

	clk_fout_epll.enable = s5p_epll_enable;
	clk_fout_epll.ops = &s5p6450_epll_ops;

	clk_48m.enable = s5p64x0_clk48m_ctrl;

	xtal_clk = clk_get(NULL, "ext_xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
				__raw_readl(S5P64X0_EPLL_CON_K));
	dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
				__raw_readl(S5P6450_DPLL_CON_K), pll_4650c);

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_dpll.rate = dpll;

	printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
			" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
			print_mhz(apll), print_mhz(mpll), print_mhz(epll),
			print_mhz(dpll));

	fclk = clk_get_rate(&clk_armclk.clk);
	hclk = clk_get_rate(&clk_hclk.clk);
	pclk = clk_get_rate(&clk_pclk.clk);
	hclk_low = clk_get_rate(&clk_hclk_low.clk);
	pclk_low = clk_get_rate(&clk_pclk_low.clk);

	printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
			" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
			print_mhz(hclk), print_mhz(hclk_low),
			print_mhz(pclk), print_mhz(pclk_low));

	clk_f.rate = fclk;
	clk_h.rate = hclk;
	clk_p.rate = pclk;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

void __init s5p6450_register_clocks(void)
{
	int ptr;

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
		s3c_register_clksrc(sysclks[ptr], 1);

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
		s3c_register_clksrc(clksrc_cdev[ptr], 1);

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));

	s3c24xx_register_clock(&dummy_apb_pclk);

	s3c_pwmclk_init();
}
Commit	Line	Data
3109e550 KK	1	/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* S5P6450 - Clock support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/list.h>
	17	#include <linux/errno.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20	#include <linux/sysdev.h>
	21	#include <linux/io.h>
	22
	23	#include <mach/hardware.h>
	24	#include <mach/map.h>
	25	#include <mach/regs-clock.h>
	26	#include <mach/s5p64x0-clock.h>
	27
	28	#include <plat/cpu-freq.h>
	29	#include <plat/clock.h>
	30	#include <plat/cpu.h>
	31	#include <plat/pll.h>
	32	#include <plat/s5p-clock.h>
	33	#include <plat/clock-clksrc.h>
	34	#include <plat/s5p6450.h>
	35
	36	static struct clksrc_clk clk_mout_dpll = {
	37	.clk = {
	38	.name = "mout_dpll",
3109e550 KK	39	},
	40	.sources = &clk_src_dpll,
	41	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
	42	};
	43
	44	static u32 epll_div[][5] = {
	45	{ 133000000, 27307, 55, 2, 2 },
	46	{ 100000000, 43691, 41, 2, 2 },
	47	{ 480000000, 0, 80, 2, 0 },
	48	};
	49
	50	static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
	51	{
	52	unsigned int epll_con, epll_con_k;
	53	unsigned int i;
	54
	55	if (clk->rate == rate) /* Return if nothing changed */
	56	return 0;
	57
	58	epll_con = __raw_readl(S5P64X0_EPLL_CON);
	59	epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
	60
	61	epll_con_k &= ~(PLL90XX_KDIV_MASK);
	62	epll_con &= ~(PLL90XX_MDIV_MASK \| PLL90XX_PDIV_MASK \| PLL90XX_SDIV_MASK);
	63
	64	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
	65	if (epll_div[i][0] == rate) {
	66	epll_con_k \|= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
	67	epll_con \|= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) \|
	68	(epll_div[i][3] << PLL90XX_PDIV_SHIFT) \|
	69	(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
	70	break;
	71	}
	72	}
	73
	74	if (i == ARRAY_SIZE(epll_div)) {
	75	printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
	76	return -EINVAL;
	77	}
	78
	79	__raw_writel(epll_con, S5P64X0_EPLL_CON);
	80	__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
	81
9616674a SY	82	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
	83	clk->rate, rate);
	84
3109e550 KK	85	clk->rate = rate;
	86
	87	return 0;
	88	}
	89
	90	static struct clk_ops s5p6450_epll_ops = {
d4b34c6c	91	.get_rate = s5p_epll_get_rate,
3109e550 KK	92	.set_rate = s5p6450_epll_set_rate,
	93	};
	94
	95	static struct clksrc_clk clk_dout_epll = {
	96	.clk = {
	97	.name = "dout_epll",
3109e550 KK	98	.parent = &clk_mout_epll.clk,
	99	},
	100	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
	101	};
	102
	103	static struct clksrc_clk clk_mout_hclk_sel = {
	104	.clk = {
	105	.name = "mout_hclk_sel",
3109e550 KK	106	},
	107	.sources = &clkset_hclk_low,
	108	.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
	109	};
	110
	111	static struct clk *clkset_hclk_list[] = {
	112	&clk_mout_hclk_sel.clk,
	113	&clk_armclk.clk,
	114	};
	115
	116	static struct clksrc_sources clkset_hclk = {
	117	.sources = clkset_hclk_list,
	118	.nr_sources = ARRAY_SIZE(clkset_hclk_list),
	119	};
	120
	121	static struct clksrc_clk clk_hclk = {
	122	.clk = {
	123	.name = "clk_hclk",
3109e550 KK	124	},
	125	.sources = &clkset_hclk,
	126	.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
	127	.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
	128	};
	129
	130	static struct clksrc_clk clk_pclk = {
	131	.clk = {
	132	.name = "clk_pclk",
3109e550 KK	133	.parent = &clk_hclk.clk,
	134	},
	135	.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
	136	};
	137	static struct clksrc_clk clk_dout_pwm_ratio0 = {
	138	.clk = {
	139	.name = "clk_dout_pwm_ratio0",
3109e550 KK	140	.parent = &clk_mout_hclk_sel.clk,
	141	},
	142	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
	143	};
	144
	145	static struct clksrc_clk clk_pclk_to_wdt_pwm = {
	146	.clk = {
	147	.name = "clk_pclk_to_wdt_pwm",
3109e550 KK	148	.parent = &clk_dout_pwm_ratio0.clk,
	149	},
	150	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
	151	};
	152
	153	static struct clksrc_clk clk_hclk_low = {
	154	.clk = {
	155	.name = "clk_hclk_low",
3109e550 KK	156	},
	157	.sources = &clkset_hclk_low,
	158	.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
	159	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
	160	};
	161
	162	static struct clksrc_clk clk_pclk_low = {
	163	.clk = {
	164	.name = "clk_pclk_low",
3109e550 KK	165	.parent = &clk_hclk_low.clk,
	166	},
	167	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
	168	};
	169
	170	/*
	171	* The following clocks will be disabled during clock initialization. It is
	172	* recommended to keep the following clocks disabled until the driver requests
	173	* for enabling the clock.
	174	*/
1526631d	175	static struct clk init_clocks_off[] = {
3109e550 KK	176	{
3109e550 KK	177	.name = "usbhost",
3109e550 KK	178	.parent = &clk_hclk_low.clk,
	179	.enable = s5p64x0_hclk0_ctrl,
	180	.ctrlbit = (1 << 3),
b05d8535	181	}, {
3091e611	182	.name = "dma",
2213d0c0	183	.devname = "dma-pl330",
b05d8535 SY	184	.parent = &clk_hclk_low.clk,
	185	.enable = s5p64x0_hclk0_ctrl,
	186	.ctrlbit = (1 << 12),
3109e550 KK	187	}, {
3109e550 KK	188	.name = "hsmmc",
d8b22d25	189	.devname = "s3c-sdhci.0",
3109e550 KK	190	.parent = &clk_hclk_low.clk,
	191	.enable = s5p64x0_hclk0_ctrl,
	192	.ctrlbit = (1 << 17),
	193	}, {
	194	.name = "hsmmc",
d8b22d25	195	.devname = "s3c-sdhci.1",
3109e550 KK	196	.parent = &clk_hclk_low.clk,
	197	.enable = s5p64x0_hclk0_ctrl,
	198	.ctrlbit = (1 << 18),
	199	}, {
	200	.name = "hsmmc",
d8b22d25	201	.devname = "s3c-sdhci.2",
3109e550 KK	202	.parent = &clk_hclk_low.clk,
	203	.enable = s5p64x0_hclk0_ctrl,
	204	.ctrlbit = (1 << 19),
	205	}, {
	206	.name = "usbotg",
3109e550 KK	207	.parent = &clk_hclk_low.clk,
	208	.enable = s5p64x0_hclk0_ctrl,
	209	.ctrlbit = (1 << 20),
	210	}, {
	211	.name = "lcd",
3109e550 KK	212	.parent = &clk_h,
	213	.enable = s5p64x0_hclk1_ctrl,
	214	.ctrlbit = (1 << 1),
	215	}, {
	216	.name = "watchdog",
3109e550 KK	217	.parent = &clk_pclk_low.clk,
	218	.enable = s5p64x0_pclk_ctrl,
	219	.ctrlbit = (1 << 5),
232d1006 AD	220	}, {
232d1006 AD	221	.name = "rtc",
232d1006 AD	222	.parent = &clk_pclk_low.clk,
	223	.enable = s5p64x0_pclk_ctrl,
	224	.ctrlbit = (1 << 6),
3109e550 KK	225	}, {
3109e550 KK	226	.name = "adc",
3109e550 KK	227	.parent = &clk_pclk_low.clk,
	228	.enable = s5p64x0_pclk_ctrl,
	229	.ctrlbit = (1 << 12),
	230	}, {
	231	.name = "i2c",
d8b22d25	232	.devname = "s3c2440-i2c.0",
3109e550 KK	233	.parent = &clk_pclk_low.clk,
	234	.enable = s5p64x0_pclk_ctrl,
	235	.ctrlbit = (1 << 17),
	236	}, {
	237	.name = "spi",
d8b22d25	238	.devname = "s3c64xx-spi.0",
3109e550 KK	239	.parent = &clk_pclk_low.clk,
	240	.enable = s5p64x0_pclk_ctrl,
	241	.ctrlbit = (1 << 21),
	242	}, {
	243	.name = "spi",
d8b22d25	244	.devname = "s3c64xx-spi.1",
3109e550 KK	245	.parent = &clk_pclk_low.clk,
	246	.enable = s5p64x0_pclk_ctrl,
	247	.ctrlbit = (1 << 22),
	248	}, {
	249	.name = "iis",
d8b22d25	250	.devname = "samsung-i2s.0",
3109e550 KK	251	.parent = &clk_pclk_low.clk,
	252	.enable = s5p64x0_pclk_ctrl,
	253	.ctrlbit = (1 << 26),
6cb26da8 JB	254	}, {
6cb26da8 JB	255	.name = "iis",
d8b22d25	256	.devname = "samsung-i2s.1",
6cb26da8 JB	257	.parent = &clk_pclk_low.clk,
	258	.enable = s5p64x0_pclk_ctrl,
	259	.ctrlbit = (1 << 15),
	260	}, {
	261	.name = "iis",
d8b22d25	262	.devname = "samsung-i2s.2",
6cb26da8 JB	263	.parent = &clk_pclk_low.clk,
	264	.enable = s5p64x0_pclk_ctrl,
	265	.ctrlbit = (1 << 16),
3109e550 KK	266	}, {
3109e550 KK	267	.name = "i2c",
d8b22d25	268	.devname = "s3c2440-i2c.1",
3109e550 KK	269	.parent = &clk_pclk_low.clk,
	270	.enable = s5p64x0_pclk_ctrl,
	271	.ctrlbit = (1 << 27),
	272	}, {
	273	.name = "dmc0",
3109e550 KK	274	.parent = &clk_pclk.clk,
	275	.enable = s5p64x0_pclk_ctrl,
	276	.ctrlbit = (1 << 30),
	277	}
	278	};
	279
	280	/*
	281	* The following clocks will be enabled during clock initialization.
	282	*/
	283	static struct clk init_clocks[] = {
	284	{
	285	.name = "intc",
3109e550 KK	286	.parent = &clk_hclk.clk,
	287	.enable = s5p64x0_hclk0_ctrl,
	288	.ctrlbit = (1 << 1),
	289	}, {
	290	.name = "mem",
3109e550 KK	291	.parent = &clk_hclk.clk,
	292	.enable = s5p64x0_hclk0_ctrl,
	293	.ctrlbit = (1 << 21),
3109e550 KK	294	}, {
3109e550 KK	295	.name = "uart",
d8b22d25	296	.devname = "s3c6400-uart.0",
3109e550 KK	297	.parent = &clk_pclk_low.clk,
	298	.enable = s5p64x0_pclk_ctrl,
	299	.ctrlbit = (1 << 1),
	300	}, {
	301	.name = "uart",
d8b22d25	302	.devname = "s3c6400-uart.1",
3109e550 KK	303	.parent = &clk_pclk_low.clk,
	304	.enable = s5p64x0_pclk_ctrl,
	305	.ctrlbit = (1 << 2),
	306	}, {
	307	.name = "uart",
d8b22d25	308	.devname = "s3c6400-uart.2",
3109e550 KK	309	.parent = &clk_pclk_low.clk,
	310	.enable = s5p64x0_pclk_ctrl,
	311	.ctrlbit = (1 << 3),
	312	}, {
	313	.name = "uart",
d8b22d25	314	.devname = "s3c6400-uart.3",
3109e550 KK	315	.parent = &clk_pclk_low.clk,
	316	.enable = s5p64x0_pclk_ctrl,
	317	.ctrlbit = (1 << 4),
	318	}, {
	319	.name = "timers",
3109e550 KK	320	.parent = &clk_pclk_to_wdt_pwm.clk,
	321	.enable = s5p64x0_pclk_ctrl,
	322	.ctrlbit = (1 << 7),
	323	}, {
	324	.name = "gpio",
3109e550 KK	325	.parent = &clk_pclk_low.clk,
	326	.enable = s5p64x0_pclk_ctrl,
	327	.ctrlbit = (1 << 18),
	328	},
	329	};
	330
	331	static struct clk *clkset_uart_list[] = {
	332	&clk_dout_epll.clk,
	333	&clk_dout_mpll.clk,
	334	};
	335
	336	static struct clksrc_sources clkset_uart = {
	337	.sources = clkset_uart_list,
	338	.nr_sources = ARRAY_SIZE(clkset_uart_list),
	339	};
	340
	341	static struct clk *clkset_mali_list[] = {
	342	&clk_mout_epll.clk,
	343	&clk_mout_apll.clk,
	344	&clk_mout_mpll.clk,
	345	};
	346
	347	static struct clksrc_sources clkset_mali = {
	348	.sources = clkset_mali_list,
	349	.nr_sources = ARRAY_SIZE(clkset_mali_list),
	350	};
	351
	352	static struct clk *clkset_group2_list[] = {
	353	&clk_dout_epll.clk,
	354	&clk_dout_mpll.clk,
	355	&clk_ext_xtal_mux,
	356	};
	357
	358	static struct clksrc_sources clkset_group2 = {
	359	.sources = clkset_group2_list,
	360	.nr_sources = ARRAY_SIZE(clkset_group2_list),
	361	};
	362
	363	static struct clk *clkset_dispcon_list[] = {
	364	&clk_dout_epll.clk,
	365	&clk_dout_mpll.clk,
	366	&clk_ext_xtal_mux,
	367	&clk_mout_dpll.clk,
	368	};
	369
	370	static struct clksrc_sources clkset_dispcon = {
	371	.sources = clkset_dispcon_list,
	372	.nr_sources = ARRAY_SIZE(clkset_dispcon_list),
	373	};
	374
	375	static struct clk *clkset_hsmmc44_list[] = {
	376	&clk_dout_epll.clk,
	377	&clk_dout_mpll.clk,
	378	&clk_ext_xtal_mux,
	379	&s5p_clk_27m,
	380	&clk_48m,
	381	};
	382
	383	static struct clksrc_sources clkset_hsmmc44 = {
	384	.sources = clkset_hsmmc44_list,
	385	.nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
	386	};
	387
	388	static struct clk *clkset_sclk_audio0_list[] = {
389	[0] = &clk_dout_epll.clk,
390	[1] = &clk_dout_mpll.clk,
391	[2] = &clk_ext_xtal_mux,
392	[3] = NULL,
393	[4] = NULL,
394	};
395
396	static struct clksrc_sources clkset_sclk_audio0 = {
397	.sources = clkset_sclk_audio0_list,
398	.nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
399	};
400
401	static struct clksrc_clk clk_sclk_audio0 = {
402	.clk = {
403	.name = "audio-bus",
3109e550 KK	404	.enable = s5p64x0_sclk_ctrl,
	405	.ctrlbit = (1 << 8),
	406	.parent = &clk_dout_epll.clk,
	407	},
	408	.sources = &clkset_sclk_audio0,
	409	.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
	410	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
	411	};
	412
	413	static struct clksrc_clk clksrcs[] = {
	414	{
	415	.clk = {
	416	.name = "sclk_mmc",
d8b22d25	417	.devname = "s3c-sdhci.0",
3109e550 KK	418	.ctrlbit = (1 << 24),
	419	.enable = s5p64x0_sclk_ctrl,
	420	},
	421	.sources = &clkset_group2,
	422	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
	423	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
	424	}, {
	425	.clk = {
	426	.name = "sclk_mmc",
d8b22d25	427	.devname = "s3c-sdhci.1",
3109e550 KK	428	.ctrlbit = (1 << 25),
	429	.enable = s5p64x0_sclk_ctrl,
	430	},
	431	.sources = &clkset_group2,
	432	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
	433	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
	434	}, {
	435	.clk = {
	436	.name = "sclk_mmc",
d8b22d25	437	.devname = "s3c-sdhci.2",
3109e550 KK	438	.ctrlbit = (1 << 26),
	439	.enable = s5p64x0_sclk_ctrl,
	440	},
	441	.sources = &clkset_group2,
	442	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
	443	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
3109e550 KK	444	}, {
	445	.clk = {
	446	.name = "sclk_fimc",
3109e550 KK	447	.ctrlbit = (1 << 10),
	448	.enable = s5p64x0_sclk_ctrl,
	449	},
	450	.sources = &clkset_group2,
	451	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
	452	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
	453	}, {
	454	.clk = {
	455	.name = "aclk_mali",
3109e550 KK	456	.ctrlbit = (1 << 2),
	457	.enable = s5p64x0_sclk1_ctrl,
	458	},
	459	.sources = &clkset_mali,
	460	.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
	461	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
	462	}, {
	463	.clk = {
	464	.name = "sclk_2d",
3109e550 KK	465	.ctrlbit = (1 << 12),
	466	.enable = s5p64x0_sclk_ctrl,
	467	},
	468	.sources = &clkset_mali,
	469	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
	470	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
	471	}, {
	472	.clk = {
	473	.name = "sclk_usi",
3109e550 KK	474	.ctrlbit = (1 << 7),
	475	.enable = s5p64x0_sclk_ctrl,
	476	},
	477	.sources = &clkset_group2,
	478	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
	479	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
	480	}, {
	481	.clk = {
	482	.name = "sclk_camif",
3109e550 KK	483	.ctrlbit = (1 << 6),
	484	.enable = s5p64x0_sclk_ctrl,
	485	},
	486	.sources = &clkset_group2,
	487	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
	488	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
	489	}, {
	490	.clk = {
	491	.name = "sclk_dispcon",
3109e550 KK	492	.ctrlbit = (1 << 1),
	493	.enable = s5p64x0_sclk1_ctrl,
	494	},
	495	.sources = &clkset_dispcon,
	496	.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
	497	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
	498	}, {
	499	.clk = {
	500	.name = "sclk_hsmmc44",
3109e550 KK	501	.ctrlbit = (1 << 30),
	502	.enable = s5p64x0_sclk_ctrl,
	503	},
	504	.sources = &clkset_hsmmc44,
	505	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
	506	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
	507	},
	508	};
	509
0cfb26e1 TA	510	static struct clksrc_clk clk_sclk_uclk = {
	511	.clk = {
	512	.name = "uclk1",
	513	.ctrlbit = (1 << 5),
	514	.enable = s5p64x0_sclk_ctrl,
	515	},
	516	.sources = &clkset_uart,
	517	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
	518	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
	519	};
	520
c596704f PV	521	static struct clksrc_clk clk_sclk_spi0 = {
	522	.clk = {
	523	.name = "sclk_spi",
	524	.devname = "s3c64xx-spi.0",
	525	.ctrlbit = (1 << 20),
	526	.enable = s5p64x0_sclk_ctrl,
	527	},
	528	.sources = &clkset_group2,
	529	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
	530	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
	531	};
	532
	533	static struct clksrc_clk clk_sclk_spi1 = {
	534	.clk = {
	535	.name = "sclk_spi",
	536	.devname = "s3c64xx-spi.1",
	537	.ctrlbit = (1 << 21),
	538	.enable = s5p64x0_sclk_ctrl,
	539	},
	540	.sources = &clkset_group2,
	541	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
	542	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
	543	};
	544
0cfb26e1 TA	545	static struct clksrc_clk *clksrc_cdev[] = {
0cfb26e1 TA	546	&clk_sclk_uclk,
c596704f PV	547	&clk_sclk_spi0,
c596704f PV	548	&clk_sclk_spi1,
0cfb26e1 TA	549	};
	550
	551	static struct clk_lookup s5p6450_clk_lookup[] = {
	552	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
	553	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
c596704f PV	554	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
	555	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
	556	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
0cfb26e1 TA	557	};
0cfb26e1 TA	558
3109e550 KK	559	/* Clock initialization code */
	560	static struct clksrc_clk *sysclks[] = {
	561	&clk_mout_apll,
	562	&clk_mout_epll,
	563	&clk_dout_epll,
	564	&clk_mout_mpll,
	565	&clk_dout_mpll,
	566	&clk_armclk,
	567	&clk_mout_hclk_sel,
	568	&clk_dout_pwm_ratio0,
	569	&clk_pclk_to_wdt_pwm,
	570	&clk_hclk,
	571	&clk_pclk,
	572	&clk_hclk_low,
	573	&clk_pclk_low,
	574	&clk_sclk_audio0,
	575	};
	576
3091e611 BK	577	static struct clk dummy_apb_pclk = {
	578	.name = "apb_pclk",
	579	.id = -1,
	580	};
	581
3109e550 KK	582	void __init_or_cpufreq s5p6450_setup_clocks(void)
	583	{
	584	struct clk *xtal_clk;
	585
	586	unsigned long xtal;
	587	unsigned long fclk;
	588	unsigned long hclk;
	589	unsigned long hclk_low;
	590	unsigned long pclk;
	591	unsigned long pclk_low;
	592
	593	unsigned long apll;
	594	unsigned long mpll;
	595	unsigned long epll;
	596	unsigned long dpll;
	597	unsigned int ptr;
	598
	599	/* Set S5P6450 functions for clk_fout_epll */
	600
d4b34c6c	601	clk_fout_epll.enable = s5p_epll_enable;
3109e550 KK	602	clk_fout_epll.ops = &s5p6450_epll_ops;
	603
	604	clk_48m.enable = s5p64x0_clk48m_ctrl;
	605
	606	xtal_clk = clk_get(NULL, "ext_xtal");
	607	BUG_ON(IS_ERR(xtal_clk));
	608
	609	xtal = clk_get_rate(xtal_clk);
	610	clk_put(xtal_clk);
	611
	612	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
	613	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
	614	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
	615	__raw_readl(S5P64X0_EPLL_CON_K));
	616	dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
	617	__raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
	618
	619	clk_fout_apll.rate = apll;
	620	clk_fout_mpll.rate = mpll;
	621	clk_fout_epll.rate = epll;
	622	clk_fout_dpll.rate = dpll;
	623
	624	printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
	625	" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
	626	print_mhz(apll), print_mhz(mpll), print_mhz(epll),
	627	print_mhz(dpll));
	628
	629	fclk = clk_get_rate(&clk_armclk.clk);
	630	hclk = clk_get_rate(&clk_hclk.clk);
	631	pclk = clk_get_rate(&clk_pclk.clk);
	632	hclk_low = clk_get_rate(&clk_hclk_low.clk);
	633	pclk_low = clk_get_rate(&clk_pclk_low.clk);
	634
	635	printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
	636	" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
	637	print_mhz(hclk), print_mhz(hclk_low),
	638	print_mhz(pclk), print_mhz(pclk_low));
	639
	640	clk_f.rate = fclk;
	641	clk_h.rate = hclk;
	642	clk_p.rate = pclk;
	643
	644	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	645	s3c_set_clksrc(&clksrcs[ptr], true);
	646	}
	647
	648	void __init s5p6450_register_clocks(void)
	649	{
3109e550 KK	650	int ptr;
	651
	652	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
	653	s3c_register_clksrc(sysclks[ptr], 1);
	654
	655	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	656	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
0cfb26e1 TA	657	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
0cfb26e1 TA	658	s3c_register_clksrc(clksrc_cdev[ptr], 1);
3109e550	659
1526631d KK	660	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1526631d KK	661	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
0cfb26e1	662	clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
3109e550	663
3091e611 BK	664	s3c24xx_register_clock(&dummy_apb_pclk);
3091e611 BK	665
3109e550 KK	666	s3c_pwmclk_init();
3109e550 KK	667	}