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3109e550 KK |
1 | /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c |
2 | * | |
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * S5P6440 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | #include <mach/hardware.h> | |
24 | #include <mach/map.h> | |
25 | #include <mach/regs-clock.h> | |
26 | #include <mach/s5p64x0-clock.h> | |
27 | ||
28 | #include <plat/cpu-freq.h> | |
29 | #include <plat/clock.h> | |
30 | #include <plat/cpu.h> | |
31 | #include <plat/pll.h> | |
32 | #include <plat/s5p-clock.h> | |
33 | #include <plat/clock-clksrc.h> | |
95af214b KK |
34 | |
35 | #include "common.h" | |
3109e550 KK |
36 | |
37 | static u32 epll_div[][5] = { | |
38 | { 36000000, 0, 48, 1, 4 }, | |
39 | { 48000000, 0, 32, 1, 3 }, | |
40 | { 60000000, 0, 40, 1, 3 }, | |
41 | { 72000000, 0, 48, 1, 3 }, | |
42 | { 84000000, 0, 28, 1, 2 }, | |
43 | { 96000000, 0, 32, 1, 2 }, | |
44 | { 32768000, 45264, 43, 1, 4 }, | |
45 | { 45158000, 6903, 30, 1, 3 }, | |
46 | { 49152000, 50332, 32, 1, 3 }, | |
47 | { 67738000, 10398, 45, 1, 3 }, | |
48 | { 73728000, 9961, 49, 1, 3 } | |
49 | }; | |
50 | ||
51 | static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate) | |
52 | { | |
53 | unsigned int epll_con, epll_con_k; | |
54 | unsigned int i; | |
55 | ||
56 | if (clk->rate == rate) /* Return if nothing changed */ | |
57 | return 0; | |
58 | ||
59 | epll_con = __raw_readl(S5P64X0_EPLL_CON); | |
60 | epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K); | |
61 | ||
62 | epll_con_k &= ~(PLL90XX_KDIV_MASK); | |
63 | epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); | |
64 | ||
65 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
66 | if (epll_div[i][0] == rate) { | |
67 | epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); | |
68 | epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | | |
69 | (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | | |
70 | (epll_div[i][4] << PLL90XX_SDIV_SHIFT); | |
71 | break; | |
72 | } | |
73 | } | |
74 | ||
75 | if (i == ARRAY_SIZE(epll_div)) { | |
76 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | |
77 | return -EINVAL; | |
78 | } | |
79 | ||
80 | __raw_writel(epll_con, S5P64X0_EPLL_CON); | |
81 | __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K); | |
82 | ||
9616674a SY |
83 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
84 | clk->rate, rate); | |
85 | ||
3109e550 KK |
86 | clk->rate = rate; |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
91 | static struct clk_ops s5p6440_epll_ops = { | |
d4b34c6c | 92 | .get_rate = s5p_epll_get_rate, |
3109e550 KK |
93 | .set_rate = s5p6440_epll_set_rate, |
94 | }; | |
95 | ||
96 | static struct clksrc_clk clk_hclk = { | |
97 | .clk = { | |
98 | .name = "clk_hclk", | |
3109e550 KK |
99 | .parent = &clk_armclk.clk, |
100 | }, | |
101 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, | |
102 | }; | |
103 | ||
104 | static struct clksrc_clk clk_pclk = { | |
105 | .clk = { | |
106 | .name = "clk_pclk", | |
3109e550 KK |
107 | .parent = &clk_hclk.clk, |
108 | }, | |
109 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, | |
110 | }; | |
111 | static struct clksrc_clk clk_hclk_low = { | |
112 | .clk = { | |
113 | .name = "clk_hclk_low", | |
3109e550 KK |
114 | }, |
115 | .sources = &clkset_hclk_low, | |
116 | .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, | |
117 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 }, | |
118 | }; | |
119 | ||
120 | static struct clksrc_clk clk_pclk_low = { | |
121 | .clk = { | |
122 | .name = "clk_pclk_low", | |
3109e550 KK |
123 | .parent = &clk_hclk_low.clk, |
124 | }, | |
125 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, | |
126 | }; | |
127 | ||
128 | /* | |
129 | * The following clocks will be disabled during clock initialization. It is | |
130 | * recommended to keep the following clocks disabled until the driver requests | |
131 | * for enabling the clock. | |
132 | */ | |
9f6bb3f5 | 133 | static struct clk init_clocks_off[] = { |
3109e550 KK |
134 | { |
135 | .name = "nand", | |
3109e550 KK |
136 | .parent = &clk_hclk.clk, |
137 | .enable = s5p64x0_mem_ctrl, | |
138 | .ctrlbit = (1 << 2), | |
139 | }, { | |
140 | .name = "post", | |
3109e550 KK |
141 | .parent = &clk_hclk_low.clk, |
142 | .enable = s5p64x0_hclk0_ctrl, | |
143 | .ctrlbit = (1 << 5) | |
144 | }, { | |
145 | .name = "2d", | |
3109e550 KK |
146 | .parent = &clk_hclk.clk, |
147 | .enable = s5p64x0_hclk0_ctrl, | |
148 | .ctrlbit = (1 << 8), | |
b05d8535 | 149 | }, { |
3091e611 | 150 | .name = "dma", |
2213d0c0 | 151 | .devname = "dma-pl330", |
b05d8535 SY |
152 | .parent = &clk_hclk_low.clk, |
153 | .enable = s5p64x0_hclk0_ctrl, | |
154 | .ctrlbit = (1 << 12), | |
3109e550 KK |
155 | }, { |
156 | .name = "hsmmc", | |
d8b22d25 | 157 | .devname = "s3c-sdhci.0", |
3109e550 KK |
158 | .parent = &clk_hclk_low.clk, |
159 | .enable = s5p64x0_hclk0_ctrl, | |
160 | .ctrlbit = (1 << 17), | |
161 | }, { | |
162 | .name = "hsmmc", | |
d8b22d25 | 163 | .devname = "s3c-sdhci.1", |
3109e550 KK |
164 | .parent = &clk_hclk_low.clk, |
165 | .enable = s5p64x0_hclk0_ctrl, | |
166 | .ctrlbit = (1 << 18), | |
167 | }, { | |
168 | .name = "hsmmc", | |
d8b22d25 | 169 | .devname = "s3c-sdhci.2", |
3109e550 KK |
170 | .parent = &clk_hclk_low.clk, |
171 | .enable = s5p64x0_hclk0_ctrl, | |
172 | .ctrlbit = (1 << 19), | |
173 | }, { | |
174 | .name = "otg", | |
3109e550 KK |
175 | .parent = &clk_hclk_low.clk, |
176 | .enable = s5p64x0_hclk0_ctrl, | |
177 | .ctrlbit = (1 << 20) | |
178 | }, { | |
179 | .name = "irom", | |
3109e550 KK |
180 | .parent = &clk_hclk.clk, |
181 | .enable = s5p64x0_hclk0_ctrl, | |
182 | .ctrlbit = (1 << 25), | |
183 | }, { | |
184 | .name = "lcd", | |
3109e550 KK |
185 | .parent = &clk_hclk_low.clk, |
186 | .enable = s5p64x0_hclk1_ctrl, | |
187 | .ctrlbit = (1 << 1), | |
188 | }, { | |
189 | .name = "hclk_fimgvg", | |
3109e550 KK |
190 | .parent = &clk_hclk.clk, |
191 | .enable = s5p64x0_hclk1_ctrl, | |
192 | .ctrlbit = (1 << 2), | |
193 | }, { | |
194 | .name = "tsi", | |
3109e550 KK |
195 | .parent = &clk_hclk_low.clk, |
196 | .enable = s5p64x0_hclk1_ctrl, | |
197 | .ctrlbit = (1 << 0), | |
198 | }, { | |
199 | .name = "watchdog", | |
3109e550 KK |
200 | .parent = &clk_pclk_low.clk, |
201 | .enable = s5p64x0_pclk_ctrl, | |
202 | .ctrlbit = (1 << 5), | |
203 | }, { | |
204 | .name = "rtc", | |
3109e550 KK |
205 | .parent = &clk_pclk_low.clk, |
206 | .enable = s5p64x0_pclk_ctrl, | |
207 | .ctrlbit = (1 << 6), | |
208 | }, { | |
209 | .name = "timers", | |
3109e550 KK |
210 | .parent = &clk_pclk_low.clk, |
211 | .enable = s5p64x0_pclk_ctrl, | |
212 | .ctrlbit = (1 << 7), | |
213 | }, { | |
214 | .name = "pcm", | |
3109e550 KK |
215 | .parent = &clk_pclk_low.clk, |
216 | .enable = s5p64x0_pclk_ctrl, | |
217 | .ctrlbit = (1 << 8), | |
218 | }, { | |
219 | .name = "adc", | |
3109e550 KK |
220 | .parent = &clk_pclk_low.clk, |
221 | .enable = s5p64x0_pclk_ctrl, | |
222 | .ctrlbit = (1 << 12), | |
223 | }, { | |
224 | .name = "i2c", | |
3109e550 KK |
225 | .parent = &clk_pclk_low.clk, |
226 | .enable = s5p64x0_pclk_ctrl, | |
227 | .ctrlbit = (1 << 17), | |
228 | }, { | |
229 | .name = "spi", | |
d8b22d25 | 230 | .devname = "s3c64xx-spi.0", |
3109e550 KK |
231 | .parent = &clk_pclk_low.clk, |
232 | .enable = s5p64x0_pclk_ctrl, | |
233 | .ctrlbit = (1 << 21), | |
234 | }, { | |
235 | .name = "spi", | |
d8b22d25 | 236 | .devname = "s3c64xx-spi.1", |
3109e550 KK |
237 | .parent = &clk_pclk_low.clk, |
238 | .enable = s5p64x0_pclk_ctrl, | |
239 | .ctrlbit = (1 << 22), | |
240 | }, { | |
241 | .name = "gps", | |
3109e550 KK |
242 | .parent = &clk_pclk_low.clk, |
243 | .enable = s5p64x0_pclk_ctrl, | |
244 | .ctrlbit = (1 << 25), | |
245 | }, { | |
d9a93c34 | 246 | .name = "iis", |
d8b22d25 | 247 | .devname = "samsung-i2s.0", |
3109e550 KK |
248 | .parent = &clk_pclk_low.clk, |
249 | .enable = s5p64x0_pclk_ctrl, | |
250 | .ctrlbit = (1 << 26), | |
251 | }, { | |
252 | .name = "dsim", | |
3109e550 KK |
253 | .parent = &clk_pclk_low.clk, |
254 | .enable = s5p64x0_pclk_ctrl, | |
255 | .ctrlbit = (1 << 28), | |
256 | }, { | |
257 | .name = "etm", | |
3109e550 KK |
258 | .parent = &clk_pclk.clk, |
259 | .enable = s5p64x0_pclk_ctrl, | |
260 | .ctrlbit = (1 << 29), | |
261 | }, { | |
262 | .name = "dmc0", | |
3109e550 KK |
263 | .parent = &clk_pclk.clk, |
264 | .enable = s5p64x0_pclk_ctrl, | |
265 | .ctrlbit = (1 << 30), | |
266 | }, { | |
267 | .name = "pclk_fimgvg", | |
3109e550 KK |
268 | .parent = &clk_pclk.clk, |
269 | .enable = s5p64x0_pclk_ctrl, | |
270 | .ctrlbit = (1 << 31), | |
271 | }, { | |
272 | .name = "sclk_spi_48", | |
d8b22d25 | 273 | .devname = "s3c64xx-spi.0", |
3109e550 KK |
274 | .parent = &clk_48m, |
275 | .enable = s5p64x0_sclk_ctrl, | |
276 | .ctrlbit = (1 << 22), | |
277 | }, { | |
278 | .name = "sclk_spi_48", | |
d8b22d25 | 279 | .devname = "s3c64xx-spi.1", |
3109e550 KK |
280 | .parent = &clk_48m, |
281 | .enable = s5p64x0_sclk_ctrl, | |
282 | .ctrlbit = (1 << 23), | |
283 | }, { | |
284 | .name = "mmc_48m", | |
d8b22d25 | 285 | .devname = "s3c-sdhci.0", |
3109e550 KK |
286 | .parent = &clk_48m, |
287 | .enable = s5p64x0_sclk_ctrl, | |
288 | .ctrlbit = (1 << 27), | |
289 | }, { | |
290 | .name = "mmc_48m", | |
d8b22d25 | 291 | .devname = "s3c-sdhci.1", |
3109e550 KK |
292 | .parent = &clk_48m, |
293 | .enable = s5p64x0_sclk_ctrl, | |
294 | .ctrlbit = (1 << 28), | |
295 | }, { | |
296 | .name = "mmc_48m", | |
d8b22d25 | 297 | .devname = "s3c-sdhci.2", |
3109e550 KK |
298 | .parent = &clk_48m, |
299 | .enable = s5p64x0_sclk_ctrl, | |
300 | .ctrlbit = (1 << 29), | |
301 | }, | |
302 | }; | |
303 | ||
304 | /* | |
305 | * The following clocks will be enabled during clock initialization. | |
306 | */ | |
307 | static struct clk init_clocks[] = { | |
308 | { | |
309 | .name = "intc", | |
3109e550 KK |
310 | .parent = &clk_hclk.clk, |
311 | .enable = s5p64x0_hclk0_ctrl, | |
312 | .ctrlbit = (1 << 1), | |
313 | }, { | |
314 | .name = "mem", | |
3109e550 KK |
315 | .parent = &clk_hclk.clk, |
316 | .enable = s5p64x0_hclk0_ctrl, | |
317 | .ctrlbit = (1 << 21), | |
3109e550 KK |
318 | }, { |
319 | .name = "uart", | |
d8b22d25 | 320 | .devname = "s3c6400-uart.0", |
3109e550 KK |
321 | .parent = &clk_pclk_low.clk, |
322 | .enable = s5p64x0_pclk_ctrl, | |
323 | .ctrlbit = (1 << 1), | |
324 | }, { | |
325 | .name = "uart", | |
d8b22d25 | 326 | .devname = "s3c6400-uart.1", |
3109e550 KK |
327 | .parent = &clk_pclk_low.clk, |
328 | .enable = s5p64x0_pclk_ctrl, | |
329 | .ctrlbit = (1 << 2), | |
330 | }, { | |
331 | .name = "uart", | |
d8b22d25 | 332 | .devname = "s3c6400-uart.2", |
3109e550 KK |
333 | .parent = &clk_pclk_low.clk, |
334 | .enable = s5p64x0_pclk_ctrl, | |
335 | .ctrlbit = (1 << 3), | |
336 | }, { | |
337 | .name = "uart", | |
d8b22d25 | 338 | .devname = "s3c6400-uart.3", |
3109e550 KK |
339 | .parent = &clk_pclk_low.clk, |
340 | .enable = s5p64x0_pclk_ctrl, | |
341 | .ctrlbit = (1 << 4), | |
342 | }, { | |
343 | .name = "gpio", | |
3109e550 KK |
344 | .parent = &clk_pclk_low.clk, |
345 | .enable = s5p64x0_pclk_ctrl, | |
346 | .ctrlbit = (1 << 18), | |
347 | }, | |
348 | }; | |
349 | ||
350 | static struct clk clk_iis_cd_v40 = { | |
351 | .name = "iis_cdclk_v40", | |
3109e550 KK |
352 | }; |
353 | ||
354 | static struct clk clk_pcm_cd = { | |
355 | .name = "pcm_cdclk", | |
3109e550 KK |
356 | }; |
357 | ||
358 | static struct clk *clkset_group1_list[] = { | |
359 | &clk_mout_epll.clk, | |
360 | &clk_dout_mpll.clk, | |
361 | &clk_fin_epll, | |
362 | }; | |
363 | ||
364 | static struct clksrc_sources clkset_group1 = { | |
365 | .sources = clkset_group1_list, | |
366 | .nr_sources = ARRAY_SIZE(clkset_group1_list), | |
367 | }; | |
368 | ||
369 | static struct clk *clkset_uart_list[] = { | |
370 | &clk_mout_epll.clk, | |
371 | &clk_dout_mpll.clk, | |
372 | }; | |
373 | ||
374 | static struct clksrc_sources clkset_uart = { | |
375 | .sources = clkset_uart_list, | |
376 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | |
377 | }; | |
378 | ||
379 | static struct clk *clkset_audio_list[] = { | |
380 | &clk_mout_epll.clk, | |
381 | &clk_dout_mpll.clk, | |
382 | &clk_fin_epll, | |
383 | &clk_iis_cd_v40, | |
384 | &clk_pcm_cd, | |
385 | }; | |
386 | ||
387 | static struct clksrc_sources clkset_audio = { | |
388 | .sources = clkset_audio_list, | |
389 | .nr_sources = ARRAY_SIZE(clkset_audio_list), | |
390 | }; | |
391 | ||
392 | static struct clksrc_clk clksrcs[] = { | |
393 | { | |
394 | .clk = { | |
9af7d94f | 395 | .name = "sclk_mmc", |
d8b22d25 | 396 | .devname = "s3c-sdhci.0", |
3109e550 KK |
397 | .ctrlbit = (1 << 24), |
398 | .enable = s5p64x0_sclk_ctrl, | |
399 | }, | |
400 | .sources = &clkset_group1, | |
401 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, | |
402 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, | |
403 | }, { | |
404 | .clk = { | |
9af7d94f | 405 | .name = "sclk_mmc", |
d8b22d25 | 406 | .devname = "s3c-sdhci.1", |
3109e550 KK |
407 | .ctrlbit = (1 << 25), |
408 | .enable = s5p64x0_sclk_ctrl, | |
409 | }, | |
410 | .sources = &clkset_group1, | |
411 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, | |
412 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, | |
413 | }, { | |
414 | .clk = { | |
9af7d94f | 415 | .name = "sclk_mmc", |
d8b22d25 | 416 | .devname = "s3c-sdhci.2", |
3109e550 KK |
417 | .ctrlbit = (1 << 26), |
418 | .enable = s5p64x0_sclk_ctrl, | |
419 | }, | |
420 | .sources = &clkset_group1, | |
421 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, | |
422 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, | |
423 | }, { | |
424 | .clk = { | |
425 | .name = "uclk1", | |
3109e550 KK |
426 | .ctrlbit = (1 << 5), |
427 | .enable = s5p64x0_sclk_ctrl, | |
428 | }, | |
429 | .sources = &clkset_uart, | |
430 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, | |
431 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, | |
432 | }, { | |
433 | .clk = { | |
434 | .name = "sclk_spi", | |
d8b22d25 | 435 | .devname = "s3c64xx-spi.0", |
3109e550 KK |
436 | .ctrlbit = (1 << 20), |
437 | .enable = s5p64x0_sclk_ctrl, | |
438 | }, | |
439 | .sources = &clkset_group1, | |
440 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, | |
441 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, | |
442 | }, { | |
443 | .clk = { | |
444 | .name = "sclk_spi", | |
d8b22d25 | 445 | .devname = "s3c64xx-spi.1", |
3109e550 KK |
446 | .ctrlbit = (1 << 21), |
447 | .enable = s5p64x0_sclk_ctrl, | |
448 | }, | |
449 | .sources = &clkset_group1, | |
450 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, | |
451 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, | |
452 | }, { | |
453 | .clk = { | |
454 | .name = "sclk_post", | |
3109e550 KK |
455 | .ctrlbit = (1 << 10), |
456 | .enable = s5p64x0_sclk_ctrl, | |
457 | }, | |
458 | .sources = &clkset_group1, | |
459 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 }, | |
460 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 }, | |
461 | }, { | |
462 | .clk = { | |
463 | .name = "sclk_dispcon", | |
3109e550 KK |
464 | .ctrlbit = (1 << 1), |
465 | .enable = s5p64x0_sclk1_ctrl, | |
466 | }, | |
467 | .sources = &clkset_group1, | |
468 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 }, | |
469 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 }, | |
470 | }, { | |
471 | .clk = { | |
472 | .name = "sclk_fimgvg", | |
3109e550 KK |
473 | .ctrlbit = (1 << 2), |
474 | .enable = s5p64x0_sclk1_ctrl, | |
475 | }, | |
476 | .sources = &clkset_group1, | |
477 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 }, | |
478 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 }, | |
479 | }, { | |
480 | .clk = { | |
481 | .name = "sclk_audio2", | |
3109e550 KK |
482 | .ctrlbit = (1 << 11), |
483 | .enable = s5p64x0_sclk_ctrl, | |
484 | }, | |
485 | .sources = &clkset_audio, | |
486 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 }, | |
487 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 }, | |
488 | }, | |
489 | }; | |
490 | ||
491 | /* Clock initialization code */ | |
492 | static struct clksrc_clk *sysclks[] = { | |
493 | &clk_mout_apll, | |
494 | &clk_mout_epll, | |
495 | &clk_mout_mpll, | |
496 | &clk_dout_mpll, | |
497 | &clk_armclk, | |
498 | &clk_hclk, | |
499 | &clk_pclk, | |
500 | &clk_hclk_low, | |
501 | &clk_pclk_low, | |
502 | }; | |
503 | ||
3091e611 BK |
504 | static struct clk dummy_apb_pclk = { |
505 | .name = "apb_pclk", | |
506 | .id = -1, | |
507 | }; | |
508 | ||
3109e550 KK |
509 | void __init_or_cpufreq s5p6440_setup_clocks(void) |
510 | { | |
511 | struct clk *xtal_clk; | |
512 | ||
513 | unsigned long xtal; | |
514 | unsigned long fclk; | |
515 | unsigned long hclk; | |
516 | unsigned long hclk_low; | |
517 | unsigned long pclk; | |
518 | unsigned long pclk_low; | |
519 | ||
520 | unsigned long apll; | |
521 | unsigned long mpll; | |
522 | unsigned long epll; | |
523 | unsigned int ptr; | |
524 | ||
525 | /* Set S5P6440 functions for clk_fout_epll */ | |
526 | ||
d4b34c6c | 527 | clk_fout_epll.enable = s5p_epll_enable; |
3109e550 KK |
528 | clk_fout_epll.ops = &s5p6440_epll_ops; |
529 | ||
530 | clk_48m.enable = s5p64x0_clk48m_ctrl; | |
531 | ||
532 | xtal_clk = clk_get(NULL, "ext_xtal"); | |
533 | BUG_ON(IS_ERR(xtal_clk)); | |
534 | ||
535 | xtal = clk_get_rate(xtal_clk); | |
536 | clk_put(xtal_clk); | |
537 | ||
538 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502); | |
539 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502); | |
540 | epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON), | |
541 | __raw_readl(S5P64X0_EPLL_CON_K)); | |
542 | ||
543 | clk_fout_apll.rate = apll; | |
544 | clk_fout_mpll.rate = mpll; | |
545 | clk_fout_epll.rate = epll; | |
546 | ||
547 | printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ | |
548 | " E=%ld.%ldMHz\n", | |
549 | print_mhz(apll), print_mhz(mpll), print_mhz(epll)); | |
550 | ||
551 | fclk = clk_get_rate(&clk_armclk.clk); | |
552 | hclk = clk_get_rate(&clk_hclk.clk); | |
553 | pclk = clk_get_rate(&clk_pclk.clk); | |
554 | hclk_low = clk_get_rate(&clk_hclk_low.clk); | |
555 | pclk_low = clk_get_rate(&clk_pclk_low.clk); | |
556 | ||
557 | printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ | |
558 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", | |
559 | print_mhz(hclk), print_mhz(hclk_low), | |
560 | print_mhz(pclk), print_mhz(pclk_low)); | |
561 | ||
562 | clk_f.rate = fclk; | |
563 | clk_h.rate = hclk; | |
564 | clk_p.rate = pclk; | |
565 | ||
566 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | |
567 | s3c_set_clksrc(&clksrcs[ptr], true); | |
568 | } | |
569 | ||
570 | static struct clk *clks[] __initdata = { | |
571 | &clk_ext, | |
572 | &clk_iis_cd_v40, | |
573 | &clk_pcm_cd, | |
574 | }; | |
575 | ||
576 | void __init s5p6440_register_clocks(void) | |
577 | { | |
3109e550 KK |
578 | int ptr; |
579 | ||
580 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | |
581 | ||
582 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | |
583 | s3c_register_clksrc(sysclks[ptr], 1); | |
584 | ||
585 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | |
586 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
587 | ||
9f6bb3f5 KK |
588 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
589 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
3109e550 | 590 | |
3091e611 BK |
591 | s3c24xx_register_clock(&dummy_apb_pclk); |
592 | ||
3109e550 KK |
593 | s3c_pwmclk_init(); |
594 | } |