projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 3501c9ae | 1 | /* linux/arch/arm/plat-s3c64xx/sleep.S |
| bd117bd1 BD |
2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. | |
| 4 | * Copyright 2008 Simtec Electronics | |
| 5 | * Ben Dooks <ben@simtec.co.uk> | |
| 6 | * http://armlinux.simtec.co.uk/ | |
| 7 | * | |
| 8 | * S3C64XX CPU sleep code | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <linux/linkage.h> | |
| 16 | #include <asm/assembler.h> | |
| 17 | #include <mach/map.h> | |
| 18 | ||
| 19 | #undef S3C64XX_VA_GPIO | |
| 20 | #define S3C64XX_VA_GPIO (0x0) | |
| 21 | ||
| 3501c9ae BD |
22 | #include <mach/regs-gpio.h> |
| 23 | #include <mach/gpio-bank-n.h> | |
| bd117bd1 BD |
24 | |
| 25 | #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) | |
| 26 | ||
| 27 | .text | |
| 28 | ||
| 29 | /* s3c_cpu_save | |
| 30 | * | |
| 31 | * Save enough processor state to allow the restart of the pm.c | |
| 32 | * code after resume. | |
| 33 | * | |
| 34 | * entry: | |
| 2e2f3d37 | 35 | * r1 = v:p offset |
| bd117bd1 BD |
36 | */ |
| 37 | ||
| 38 | ENTRY(s3c_cpu_save) | |
| 39 | stmfd sp!, { r4 - r12, lr } | |
| 2e2f3d37 RK |
40 | ldr r3, =resume_with_mmu |
| 41 | bl cpu_suspend | |
| bd117bd1 BD |
42 | |
| 43 | @@ call final suspend code | |
| 44 | ldr r0, =pm_cpu_sleep | |
| 45 | ldr pc, [r0] | |
| 46 | ||
| 47 | @@ return to the caller, after the MMU is turned on. | |
| 48 | @@ restore the last bits of the stack and return. | |
| 49 | resume_with_mmu: | |
| 50 | ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save | |
| 51 | ||
| bd117bd1 BD |
52 | /* Sleep magic, the word before the resume entry point so that the |
| 53 | * bootloader can check for a resumeable image. */ | |
| 54 | ||
| 55 | .word 0x2bedf00d | |
| 56 | ||
| 57 | /* s3c_cpu_reusme | |
| 58 | * | |
| 59 | * This is the entry point, stored by whatever method the bootloader | |
| 60 | * requires to get the kernel runnign again. This code expects to be | |
| 61 | * entered with no caches live and the MMU disabled. It will then | |
| 62 | * restore the MMU and other basic CP registers saved and restart | |
| 63 | * the kernel C code to finish the resume code. | |
| 64 | */ | |
| 65 | ||
| 66 | ENTRY(s3c_cpu_resume) | |
| 67 | msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE | |
| 68 | ldr r2, =LL_UART /* for debug */ | |
| 69 | ||
| 70 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK | |
| 71 | /* Initialise the GPIO state if we are debugging via the SMDK LEDs, | |
| 72 | * as the uboot version supplied resets these to inputs during the | |
| 73 | * resume checks. | |
| 74 | */ | |
| 75 | ||
| 76 | ldr r3, =S3C64XX_PA_GPIO | |
| 77 | ldr r0, [ r3, #S3C64XX_GPNCON ] | |
| 78 | bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ | |
| 79 | S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) | |
| 80 | orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ | |
| 81 | S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) | |
| 82 | str r0, [ r3, #S3C64XX_GPNCON ] | |
| 83 | ||
| 84 | ldr r0, [ r3, #S3C64XX_GPNDAT ] | |
| 85 | bic r0, r0, #0xf << 12 @ GPN12..15 | |
| 86 | orr r0, r0, #1 << 15 @ GPN15 | |
| 87 | str r0, [ r3, #S3C64XX_GPNDAT ] | |
| 88 | #endif | |
| 2e2f3d37 | 89 | b cpu_resume |