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ARM: S3C64XX: Add hookup for Deanston module on Cragganmore
[linux-2.6-block.git] / arch / arm / mach-s3c64xx / mach-crag6410.c
CommitLineData
e1a3c74f
MB		 1/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * Copyright 2011 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/serial_core.h>
17#include <linux/platform_device.h>
18#include <linux/fb.h>
19#include <linux/io.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
66211f98 22#include <linux/leds.h>
e1a3c74f 23#include <linux/delay.h>
fb7f60f3 24#include <linux/mmc/host.h>
e1a3c74f 25#include <linux/regulator/machine.h>
ae24c263 26#include <linux/regulator/fixed.h>
e1a3c74f
MB		 27#include <linux/pwm_backlight.h>
28#include <linux/dm9000.h>
29#include <linux/gpio_keys.h>
30#include <linux/basic_mmio_gpio.h>
31#include <linux/spi/spi.h>
32
33#include <linux/i2c/pca953x.h>
126625e1 34#include <linux/platform_data/s3c-hsotg.h>
e1a3c74f
MB		 35
36#include <video/platform_lcd.h>
37
38#include <linux/mfd/wm831x/core.h>
39#include <linux/mfd/wm831x/pdata.h>
ae24c263 40#include <linux/mfd/wm831x/irq.h>
e1a3c74f
MB		 41#include <linux/mfd/wm831x/gpio.h>
42
8504a3cb
MB		 43#include <sound/wm1250-ev1.h>
44
774b51f8 45#include <asm/hardware/vic.h>
e1a3c74f
MB		 46#include <asm/mach/arch.h>
47#include <asm/mach-types.h>
48
5a213a55 49#include <video/samsung_fimd.h>
e1a3c74f
MB		 50#include <mach/hardware.h>
51#include <mach/map.h>
52
e1a3c74f
MB		 53#include <mach/regs-sys.h>
54#include <mach/regs-gpio.h>
55#include <mach/regs-modem.h>
d0f0b43f 56#include <mach/crag6410.h>
e1a3c74f 57
e1a3c74f
MB		 58#include <mach/regs-gpio-memport.h>
59
60#include <plat/regs-serial.h>
e1a3c74f
MB		 61#include <plat/fb.h>
62#include <plat/sdhci.h>
63#include <plat/gpio-cfg.h>
436d42c6 64#include <linux/platform_data/spi-s3c64xx.h>
e1a3c74f
MB		 65
66#include <plat/keypad.h>
67#include <plat/clock.h>
68#include <plat/devs.h>
69#include <plat/cpu.h>
70#include <plat/adc.h>
436d42c6 71#include <linux/platform_data/i2c-s3c2410.h>
e1a3c74f
MB		 72#include <plat/pm.h>
73
b024043b
KK		 74#include "common.h"
75
e1a3c74f
MB		 76/* serial port setup */
77
78#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
79#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
80#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
81
82static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
83 [0] = {
ae24c263
MB		 84 .hwport = 0,
85 .flags = 0,
86 .ucon = UCON,
87 .ulcon = ULCON,
88 .ufcon = UFCON,
e1a3c74f
MB		 89 },
90 [1] = {
ae24c263
MB		 91 .hwport = 1,
92 .flags = 0,
93 .ucon = UCON,
94 .ulcon = ULCON,
95 .ufcon = UFCON,
e1a3c74f
MB		 96 },
97 [2] = {
ae24c263
MB		 98 .hwport = 2,
99 .flags = 0,
100 .ucon = UCON,
101 .ulcon = ULCON,
102 .ufcon = UFCON,
e1a3c74f
MB		 103 },
104 [3] = {
ae24c263
MB		 105 .hwport = 3,
106 .flags = 0,
107 .ucon = UCON,
108 .ulcon = ULCON,
109 .ufcon = UFCON,
e1a3c74f
MB		 110 },
111};
112
113static struct platform_pwm_backlight_data crag6410_backlight_data = {
114 .pwm_id = 0,
115 .max_brightness = 1000,
116 .dft_brightness = 600,
117 .pwm_period_ns = 100000, /* about 1kHz */
118};
119
120static struct platform_device crag6410_backlight_device = {
121 .name = "pwm-backlight",
122 .id = -1,
123 .dev = {
124 .parent = &s3c_device_timer[0].dev,
125 .platform_data = &crag6410_backlight_data,
126 },
127};
128
129static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
130{
131 pr_debug("%s: setting power %d\n", __func__, power);
132
133 if (power) {
134 gpio_set_value(S3C64XX_GPB(0), 1);
135 msleep(1);
136 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
137 } else {
138 gpio_direction_output(S3C64XX_GPF(14), 0);
139 gpio_set_value(S3C64XX_GPB(0), 0);
140 }
141}
142
143static struct platform_device crag6410_lcd_powerdev = {
144 .name = "platform-lcd",
145 .id = -1,
146 .dev.parent = &s3c_device_fb.dev,
147 .dev.platform_data = &(struct plat_lcd_data) {
148 .set_power = crag6410_lcd_power_set,
149 },
150};
151
152/* 640x480 URT */
153static struct s3c_fb_pd_win crag6410_fb_win0 = {
e1a3c74f
MB		 154 .max_bpp = 32,
155 .default_bpp = 16,
79d3c41a
TA		 156 .xres = 640,
157 .yres = 480,
e1a3c74f
MB		 158 .virtual_y = 480 * 2,
159 .virtual_x = 640,
160};
161
79d3c41a
TA		 162static struct fb_videomode crag6410_lcd_timing = {
163 .left_margin = 150,
164 .right_margin = 80,
165 .upper_margin = 40,
166 .lower_margin = 5,
167 .hsync_len = 40,
168 .vsync_len = 5,
169 .xres = 640,
170 .yres = 480,
171};
172
e1a3c74f 173/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
70660e5d 174static struct s3c_fb_platdata crag6410_lcd_pdata __devinitdata = {
e1a3c74f 175 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
79d3c41a 176 .vtiming = &crag6410_lcd_timing,
e1a3c74f
MB		 177 .win[0] = &crag6410_fb_win0,
178 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
179 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
180};
181
182/* 2x6 keypad */
183
70660e5d 184static uint32_t crag6410_keymap[] __devinitdata = {
e1a3c74f
MB		 185 /* KEY(row, col, keycode) */
186 KEY(0, 0, KEY_VOLUMEUP),
187 KEY(0, 1, KEY_HOME),
188 KEY(0, 2, KEY_VOLUMEDOWN),
189 KEY(0, 3, KEY_HELP),
190 KEY(0, 4, KEY_MENU),
191 KEY(0, 5, KEY_MEDIA),
192 KEY(1, 0, 232),
193 KEY(1, 1, KEY_DOWN),
194 KEY(1, 2, KEY_LEFT),
195 KEY(1, 3, KEY_UP),
196 KEY(1, 4, KEY_RIGHT),
197 KEY(1, 5, KEY_CAMERA),
198};
199
70660e5d 200static struct matrix_keymap_data crag6410_keymap_data __devinitdata = {
e1a3c74f
MB		 201 .keymap = crag6410_keymap,
202 .keymap_size = ARRAY_SIZE(crag6410_keymap),
203};
204
70660e5d 205static struct samsung_keypad_platdata crag6410_keypad_data __devinitdata = {
e1a3c74f
MB		 206 .keymap_data = &crag6410_keymap_data,
207 .rows = 2,
208 .cols = 6,
209};
210
211static struct gpio_keys_button crag6410_gpio_keys[] = {
212 [0] = {
213 .code = KEY_SUSPEND,
214 .gpio = S3C64XX_GPL(10), /* EINT 18 */
ae24c263 215 .type = EV_KEY,
e1a3c74f
MB		 216 .wakeup = 1,
217 .active_low = 1,
218 },
ae24c263
MB		 219 [1] = {
220 .code = SW_FRONT_PROXIMITY,
221 .gpio = S3C64XX_GPN(11), /* EINT 11 */
222 .type = EV_SW,
223 },
e1a3c74f
MB		 224};
225
226static struct gpio_keys_platform_data crag6410_gpio_keydata = {
227 .buttons = crag6410_gpio_keys,
228 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
229};
230
231static struct platform_device crag6410_gpio_keydev = {
232 .name = "gpio-keys",
233 .id = 0,
234 .dev.platform_data = &crag6410_gpio_keydata,
235};
236
237static struct resource crag6410_dm9k_resource[] = {
8ebf148a
TB		 238 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2),
239 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2),
240 [2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \
241 | IORESOURCE_IRQ_HIGHLEVEL),
e1a3c74f
MB		 242};
243
244static struct dm9000_plat_data mini6410_dm9k_pdata = {
245 .flags = DM9000_PLATF_16BITONLY,
246};
247
248static struct platform_device crag6410_dm9k_device = {
249 .name = "dm9000",
250 .id = -1,
251 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
252 .resource = crag6410_dm9k_resource,
253 .dev.platform_data = &mini6410_dm9k_pdata,
254};
255
256static struct resource crag6410_mmgpio_resource[] = {
8ebf148a 257 [0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
e1a3c74f
MB		 258};
259
260static struct platform_device crag6410_mmgpio = {
261 .name = "basic-mmio-gpio",
262 .id = -1,
263 .resource = crag6410_mmgpio_resource,
264 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
265 .dev.platform_data = &(struct bgpio_pdata) {
91b60b1d 266 .base = MMGPIO_GPIO_BASE,
e1a3c74f
MB		 267 },
268};
269
ae24c263
MB		 270static struct platform_device speyside_device = {
271 .name = "speyside",
272 .id = -1,
273};
274
8c051ab4
MB		 275static struct platform_device lowland_device = {
276 .name = "lowland",
277 .id = -1,
278};
279
6414261f
MB		 280static struct platform_device tobermory_device = {
281 .name = "tobermory",
ae24c263
MB		 282 .id = -1,
283};
284
c5c32c96
MB		 285static struct platform_device littlemill_device = {
286 .name = "littlemill",
287 .id = -1,
288};
289
25752b78
MB		 290static struct platform_device bells_wm5102_device = {
291 .name = "bells",
292 .id = 0,
293};
294
295static struct platform_device bells_wm5110_device = {
296 .name = "bells",
297 .id = 1,
298};
299
ae24c263 300static struct regulator_consumer_supply wallvdd_consumers[] = {
554f01fb 301 REGULATOR_SUPPLY("SPKVDD", "1-001a"),
ae24c263
MB		 302 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
303 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
4ed12b50
MB		 304 REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
305 REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
402f624b 306
479535ed
MB		 307 REGULATOR_SUPPLY("SPKVDDL", "spi0.1"),
308 REGULATOR_SUPPLY("SPKVDDR", "spi0.1"),
309 REGULATOR_SUPPLY("SPKVDDL", "wm5102-codec"),
310 REGULATOR_SUPPLY("SPKVDDR", "wm5102-codec"),
311 REGULATOR_SUPPLY("SPKVDDL", "wm5110-codec"),
312 REGULATOR_SUPPLY("SPKVDDR", "wm5110-codec"),
313
402f624b
MB		 314 REGULATOR_SUPPLY("DC1VDD", "0-0034"),
315 REGULATOR_SUPPLY("DC2VDD", "0-0034"),
316 REGULATOR_SUPPLY("DC3VDD", "0-0034"),
317 REGULATOR_SUPPLY("LDO1VDD", "0-0034"),
318 REGULATOR_SUPPLY("LDO2VDD", "0-0034"),
319 REGULATOR_SUPPLY("LDO4VDD", "0-0034"),
320 REGULATOR_SUPPLY("LDO5VDD", "0-0034"),
321 REGULATOR_SUPPLY("LDO6VDD", "0-0034"),
322 REGULATOR_SUPPLY("LDO7VDD", "0-0034"),
323 REGULATOR_SUPPLY("LDO8VDD", "0-0034"),
324 REGULATOR_SUPPLY("LDO9VDD", "0-0034"),
325 REGULATOR_SUPPLY("LDO10VDD", "0-0034"),
326 REGULATOR_SUPPLY("LDO11VDD", "0-0034"),
327
328 REGULATOR_SUPPLY("DC1VDD", "1-0034"),
329 REGULATOR_SUPPLY("DC2VDD", "1-0034"),
330 REGULATOR_SUPPLY("DC3VDD", "1-0034"),
ae24c263
MB		 331};
332
333static struct regulator_init_data wallvdd_data = {
334 .constraints = {
335 .always_on = 1,
336 },
337 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
338 .consumer_supplies = wallvdd_consumers,
339};
340
341static struct fixed_voltage_config wallvdd_pdata = {
342 .supply_name = "WALLVDD",
343 .microvolts = 5000000,
344 .init_data = &wallvdd_data,
345 .gpio = -EINVAL,
346};
347
348static struct platform_device wallvdd_device = {
349 .name = "reg-fixed-voltage",
350 .id = -1,
351 .dev = {
352 .platform_data = &wallvdd_pdata,
353 },
354};
355
e1a3c74f
MB		 356static struct platform_device *crag6410_devices[] __initdata = {
357 &s3c_device_hsmmc0,
e1a3c74f
MB		 358 &s3c_device_hsmmc2,
359 &s3c_device_i2c0,
360 &s3c_device_i2c1,
361 &s3c_device_fb,
362 &s3c_device_ohci,
363 &s3c_device_usb_hsotg,
e1a3c74f
MB		 364 &s3c_device_timer[0],
365 &s3c64xx_device_iis0,
366 &s3c64xx_device_iis1,
367 &samsung_asoc_dma,
368 &samsung_device_keypad,
369 &crag6410_gpio_keydev,
370 &crag6410_dm9k_device,
371 &s3c64xx_device_spi0,
372 &crag6410_mmgpio,
373 &crag6410_lcd_powerdev,
374 &crag6410_backlight_device,
ae24c263 375 &speyside_device,
6414261f 376 &tobermory_device,
c5c32c96 377 &littlemill_device,
8c051ab4 378 &lowland_device,
25752b78
MB		 379 &bells_wm5102_device,
380 &bells_wm5110_device,
ae24c263 381 &wallvdd_device,
e1a3c74f
MB		 382};
383
384static struct pca953x_platform_data crag6410_pca_data = {
385 .gpio_base = PCA935X_GPIO_BASE,
6e11e0bd 386 .irq_base = -1,
e1a3c74f
MB		 387};
388
986afc98
MB		 389/* VDDARM is controlled by DVS1 connected to GPK(0) */
390static struct wm831x_buckv_pdata vddarm_pdata = {
391 .dvs_control_src = 1,
392 .dvs_gpio = S3C64XX_GPK(0),
393};
394
70660e5d 395static struct regulator_consumer_supply vddarm_consumers[] __devinitdata = {
e1a3c74f
MB		 396 REGULATOR_SUPPLY("vddarm", NULL),
397};
398
70660e5d 399static struct regulator_init_data vddarm __devinitdata = {
e1a3c74f
MB		 400 .constraints = {
401 .name = "VDDARM",
402 .min_uV = 1000000,
403 .max_uV = 1300000,
404 .always_on = 1,
405 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
406 },
407 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
408 .consumer_supplies = vddarm_consumers,
35127296 409 .supply_regulator = "WALLVDD",
986afc98 410 .driver_data = &vddarm_pdata,
e1a3c74f
MB		 411};
412
70660e5d 413static struct regulator_consumer_supply vddint_consumers[] __devinitdata = {
39cb263e
MB		 414 REGULATOR_SUPPLY("vddint", NULL),
415};
416
70660e5d 417static struct regulator_init_data vddint __devinitdata = {
e1a3c74f
MB		 418 .constraints = {
419 .name = "VDDINT",
420 .min_uV = 1000000,
421 .max_uV = 1200000,
422 .always_on = 1,
423 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
424 },
39cb263e
MB		 425 .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
426 .consumer_supplies = vddint_consumers,
427 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 428};
429
70660e5d 430static struct regulator_init_data vddmem __devinitdata = {
e1a3c74f
MB		 431 .constraints = {
432 .name = "VDDMEM",
433 .always_on = 1,
434 },
435};
436
70660e5d 437static struct regulator_init_data vddsys __devinitdata = {
e1a3c74f
MB		 438 .constraints = {
439 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
440 .always_on = 1,
441 },
442};
443
70660e5d 444static struct regulator_consumer_supply vddmmc_consumers[] __devinitdata = {
e1a3c74f
MB		 445 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
446 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
447 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
448};
449
70660e5d 450static struct regulator_init_data vddmmc __devinitdata = {
e1a3c74f
MB		 451 .constraints = {
452 .name = "VDDMMC,UH",
453 .always_on = 1,
454 },
455 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
456 .consumer_supplies = vddmmc_consumers,
35127296 457 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 458};
459
70660e5d 460static struct regulator_init_data vddotgi __devinitdata = {
e1a3c74f
MB		 461 .constraints = {
462 .name = "VDDOTGi",
463 .always_on = 1,
464 },
35127296 465 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 466};
467
70660e5d 468static struct regulator_init_data vddotg __devinitdata = {
e1a3c74f
MB		 469 .constraints = {
470 .name = "VDDOTG",
471 .always_on = 1,
472 },
35127296 473 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 474};
475
70660e5d 476static struct regulator_init_data vddhi __devinitdata = {
e1a3c74f
MB		 477 .constraints = {
478 .name = "VDDHI",
479 .always_on = 1,
480 },
35127296 481 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 482};
483
70660e5d 484static struct regulator_init_data vddadc __devinitdata = {
e1a3c74f
MB		 485 .constraints = {
486 .name = "VDDADC,VDDDAC",
487 .always_on = 1,
488 },
35127296 489 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 490};
491
70660e5d 492static struct regulator_init_data vddmem0 __devinitdata = {
e1a3c74f
MB		 493 .constraints = {
494 .name = "VDDMEM0",
495 .always_on = 1,
496 },
35127296 497 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 498};
499
70660e5d 500static struct regulator_init_data vddpll __devinitdata = {
e1a3c74f
MB		 501 .constraints = {
502 .name = "VDDPLL",
503 .always_on = 1,
504 },
35127296 505 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 506};
507
70660e5d 508static struct regulator_init_data vddlcd __devinitdata = {
e1a3c74f
MB		 509 .constraints = {
510 .name = "VDDLCD",
511 .always_on = 1,
512 },
35127296 513 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 514};
515
70660e5d 516static struct regulator_init_data vddalive __devinitdata = {
e1a3c74f
MB		 517 .constraints = {
518 .name = "VDDALIVE",
519 .always_on = 1,
520 },
35127296 521 .supply_regulator = "WALLVDD",
e1a3c74f
MB		 522};
523
70660e5d 524static struct wm831x_backup_pdata banff_backup_pdata __devinitdata = {
89e1c3d0
MB		 525 .charger_enable = 1,
526 .vlim = 2500, /* mV */
527 .ilim = 200, /* uA */
528};
529
70660e5d 530static struct wm831x_status_pdata banff_red_led __devinitdata = {
e1a3c74f
MB		 531 .name = "banff:red:",
532 .default_src = WM831X_STATUS_MANUAL,
533};
534
70660e5d 535static struct wm831x_status_pdata banff_green_led __devinitdata = {
e1a3c74f
MB		 536 .name = "banff:green:",
537 .default_src = WM831X_STATUS_MANUAL,
538};
539
70660e5d 540static struct wm831x_touch_pdata touch_pdata __devinitdata = {
e1a3c74f 541 .data_irq = S3C_EINT(26),
ae24c263 542 .pd_irq = S3C_EINT(27),
e1a3c74f
MB		 543};
544
70660e5d 545static struct wm831x_pdata crag_pmic_pdata __devinitdata = {
ae24c263 546 .wm831x_num = 1,
aaed44e1 547 .gpio_base = BANFF_PMIC_GPIO_BASE,
dcf3580a 548 .soft_shutdown = true,
e1a3c74f 549
89e1c3d0
MB		 550 .backup = &banff_backup_pdata,
551
ae24c263 552 .gpio_defaults = {
986afc98
MB		 553 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
554 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
ae24c263
MB		 555 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
556 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
557 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
558 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
559 },
560
e1a3c74f
MB		 561 .dcdc = {
562 &vddarm, /* DCDC1 */
563 &vddint, /* DCDC2 */
564 &vddmem, /* DCDC3 */
565 },
566
567 .ldo = {
568 &vddsys, /* LDO1 */
569 &vddmmc, /* LDO2 */
570 NULL, /* LDO3 */
571 &vddotgi, /* LDO4 */
572 &vddotg, /* LDO5 */
573 &vddhi, /* LDO6 */
574 &vddadc, /* LDO7 */
575 &vddmem0, /* LDO8 */
576 &vddpll, /* LDO9 */
577 &vddlcd, /* LDO10 */
578 &vddalive, /* LDO11 */
579 },
580
581 .status = {
582 &banff_green_led,
583 &banff_red_led,
584 },
585
586 .touch = &touch_pdata,
587};
588
70660e5d 589static struct i2c_board_info i2c_devs0[] __devinitdata = {
e1a3c74f
MB		 590 { I2C_BOARD_INFO("24c08", 0x50), },
591 { I2C_BOARD_INFO("tca6408", 0x20),
592 .platform_data = &crag6410_pca_data,
593 },
594 { I2C_BOARD_INFO("wm8312", 0x34),
595 .platform_data = &crag_pmic_pdata,
596 .irq = S3C_EINT(23),
597 },
598};
599
600static struct s3c2410_platform_i2c i2c0_pdata = {
601 .frequency = 400000,
602};
603
70660e5d 604static struct regulator_consumer_supply pvdd_1v2_consumers[] __devinitdata = {
cda2349a
MB		 605 REGULATOR_SUPPLY("DCVDD", "spi0.0"),
606 REGULATOR_SUPPLY("AVDD", "spi0.0"),
479535ed 607 REGULATOR_SUPPLY("AVDD", "spi0.1"),
cda2349a
MB		 608};
609
70660e5d 610static struct regulator_init_data pvdd_1v2 __devinitdata = {
ae24c263
MB		 611 .constraints = {
612 .name = "PVDD_1V2",
cda2349a 613 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
ae24c263 614 },
cda2349a
MB		 615
616 .consumer_supplies = pvdd_1v2_consumers,
617 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
ae24c263
MB		 618};
619
70660e5d 620static struct regulator_consumer_supply pvdd_1v8_consumers[] __devinitdata = {
d5160ecf 621 REGULATOR_SUPPLY("LDOVDD", "1-001a"),
ae24c263
MB		 622 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
623 REGULATOR_SUPPLY("DBVDD", "1-001a"),
4ed12b50
MB		 624 REGULATOR_SUPPLY("DBVDD1", "1-001a"),
625 REGULATOR_SUPPLY("DBVDD2", "1-001a"),
626 REGULATOR_SUPPLY("DBVDD3", "1-001a"),
ae24c263
MB		 627 REGULATOR_SUPPLY("CPVDD", "1-001a"),
628 REGULATOR_SUPPLY("AVDD2", "1-001a"),
629 REGULATOR_SUPPLY("DCVDD", "1-001a"),
630 REGULATOR_SUPPLY("AVDD", "1-001a"),
cda2349a 631 REGULATOR_SUPPLY("DBVDD", "spi0.0"),
479535ed
MB		 632 REGULATOR_SUPPLY("DBVDD1", "spi0.1"),
633 REGULATOR_SUPPLY("DBVDD2", "spi0.1"),
634 REGULATOR_SUPPLY("DBVDD3", "spi0.1"),
635 REGULATOR_SUPPLY("LDOVDD", "spi0.1"),
636 REGULATOR_SUPPLY("CPVDD", "spi0.1"),
637
638 REGULATOR_SUPPLY("DBVDD2", "wm5102-codec"),
639 REGULATOR_SUPPLY("DBVDD3", "wm5102-codec"),
640 REGULATOR_SUPPLY("CPVDD", "wm5102-codec"),
641
642 REGULATOR_SUPPLY("DBVDD2", "wm5110-codec"),
643 REGULATOR_SUPPLY("DBVDD3", "wm5110-codec"),
644 REGULATOR_SUPPLY("CPVDD", "wm5110-codec"),
ae24c263
MB		 645};
646
70660e5d 647static struct regulator_init_data pvdd_1v8 __devinitdata = {
ae24c263
MB		 648 .constraints = {
649 .name = "PVDD_1V8",
650 .always_on = 1,
651 },
652
653 .consumer_supplies = pvdd_1v8_consumers,
654 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
655};
656
70660e5d 657static struct regulator_consumer_supply pvdd_3v3_consumers[] __devinitdata = {
ae24c263
MB		 658 REGULATOR_SUPPLY("MICVDD", "1-001a"),
659 REGULATOR_SUPPLY("AVDD1", "1-001a"),
660};
661
70660e5d 662static struct regulator_init_data pvdd_3v3 __devinitdata = {
ae24c263
MB		 663 .constraints = {
664 .name = "PVDD_3V3",
665 .always_on = 1,
666 },
667
668 .consumer_supplies = pvdd_3v3_consumers,
669 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
670};
671
70660e5d 672static struct wm831x_pdata glenfarclas_pmic_pdata __devinitdata = {
ae24c263
MB		 673 .wm831x_num = 2,
674 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
675 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
dcf3580a 676 .soft_shutdown = true,
ae24c263
MB		 677
678 .gpio_defaults = {
679 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
680 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
681 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
682 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
683 },
684
685 .dcdc = {
686 &pvdd_1v2, /* DCDC1 */
687 &pvdd_1v8, /* DCDC2 */
688 &pvdd_3v3, /* DCDC3 */
689 },
690
691 .disable_touch = true,
692};
693
8504a3cb
MB		 694static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
695 .gpios = {
696 [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
697 [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
698 [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
699 [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
700 [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
701 },
702};
703
70660e5d 704static struct i2c_board_info i2c_devs1[] __devinitdata = {
e1a3c74f 705 { I2C_BOARD_INFO("wm8311", 0x34),
ae24c263
MB		 706 .irq = S3C_EINT(0),
707 .platform_data = &glenfarclas_pmic_pdata },
708
ea070cd2 709 { I2C_BOARD_INFO("wlf-gf-module", 0x22) },
d0f0b43f
MB		 710 { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
711 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
712 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
713
8504a3cb
MB		 714 { I2C_BOARD_INFO("wm1250-ev1", 0x27),
715 .platform_data = &wm1250_ev1_pdata },
e1a3c74f
MB		 716};
717
8351c7aa
MB		 718static struct s3c2410_platform_i2c i2c1_pdata = {
719 .frequency = 400000,
720 .bus_num = 1,
e1a3c74f
MB		 721};
722
723static void __init crag6410_map_io(void)
724{
725 s3c64xx_init_io(NULL, 0);
726 s3c24xx_init_clocks(12000000);
727 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
728
729 /* LCD type and Bypass set by bootloader */
730}
731
732static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
733 .max_width = 4,
734 .cd_type = S3C_SDHCI_CD_PERMANENT,
a9294cdc 735 .host_caps = MMC_CAP_POWER_OFF_CARD,
e1a3c74f
MB		 736};
737
e1a3c74f
MB		 738static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
739{
740 /* Set all the necessary GPG pins to special-function 2 */
741 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
742
743 /* force card-detected for prototype 0 */
744 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
745}
746
747static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
748 .max_width = 4,
749 .cd_type = S3C_SDHCI_CD_INTERNAL,
750 .cfg_gpio = crag6410_cfg_sdhci0,
fb7f60f3 751 .host_caps = MMC_CAP_POWER_OFF_CARD,
e1a3c74f
MB		 752};
753
66211f98
MB		 754static const struct gpio_led gpio_leds[] = {
755 {
756 .name = "d13:green:",
757 .gpio = MMGPIO_GPIO_BASE + 0,
758 .default_state = LEDS_GPIO_DEFSTATE_ON,
759 },
760 {
761 .name = "d14:green:",
762 .gpio = MMGPIO_GPIO_BASE + 1,
763 .default_state = LEDS_GPIO_DEFSTATE_ON,
764 },
765 {
766 .name = "d15:green:",
767 .gpio = MMGPIO_GPIO_BASE + 2,
768 .default_state = LEDS_GPIO_DEFSTATE_ON,
769 },
770 {
771 .name = "d16:green:",
772 .gpio = MMGPIO_GPIO_BASE + 3,
773 .default_state = LEDS_GPIO_DEFSTATE_ON,
774 },
775 {
776 .name = "d17:green:",
777 .gpio = MMGPIO_GPIO_BASE + 4,
778 .default_state = LEDS_GPIO_DEFSTATE_ON,
779 },
780 {
781 .name = "d18:green:",
782 .gpio = MMGPIO_GPIO_BASE + 5,
783 .default_state = LEDS_GPIO_DEFSTATE_ON,
784 },
785 {
786 .name = "d19:green:",
787 .gpio = MMGPIO_GPIO_BASE + 6,
788 .default_state = LEDS_GPIO_DEFSTATE_ON,
789 },
790 {
791 .name = "d20:green:",
792 .gpio = MMGPIO_GPIO_BASE + 7,
793 .default_state = LEDS_GPIO_DEFSTATE_ON,
794 },
795};
796
797static const struct gpio_led_platform_data gpio_leds_pdata = {
798 .leds = gpio_leds,
799 .num_leds = ARRAY_SIZE(gpio_leds),
e1a3c74f
MB		 800};
801
99f6e1f5
JS		 802static struct s3c_hsotg_plat crag6410_hsotg_pdata;
803
e1a3c74f
MB		 804static void __init crag6410_machine_init(void)
805{
806 /* Open drain IRQs need pullups */
807 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
808 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
809
810 gpio_request(S3C64XX_GPB(0), "LCD power");
811 gpio_direction_output(S3C64XX_GPB(0), 0);
812
813 gpio_request(S3C64XX_GPF(14), "LCD PWM");
814 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
815
816 gpio_request(S3C64XX_GPB(1), "SD power");
817 gpio_direction_output(S3C64XX_GPB(1), 0);
818
819 gpio_request(S3C64XX_GPF(10), "nRESETSEL");
820 gpio_direction_output(S3C64XX_GPF(10), 1);
821
822 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
e1a3c74f
MB		 823 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
824
825 s3c_i2c0_set_platdata(&i2c0_pdata);
8351c7aa 826 s3c_i2c1_set_platdata(&i2c1_pdata);
e1a3c74f 827 s3c_fb_set_platdata(&crag6410_lcd_pdata);
99f6e1f5 828 s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
e1a3c74f
MB		 829
830 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
831 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
832
833 samsung_keypad_set_platdata(&crag6410_keypad_data);
479535ed 834 s3c64xx_spi0_set_platdata(NULL, 0, 2);
e1a3c74f
MB		 835
836 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
837
66211f98
MB		 838 gpio_led_register_device(-1, &gpio_leds_pdata);
839
ae24c263
MB		 840 regulator_has_full_constraints();
841
c656c306 842 s3c64xx_pm_init();
e1a3c74f
MB		 843}
844
845MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
846 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
170a5908 847 .atag_offset = 0x100,
e1a3c74f 848 .init_irq = s3c6410_init_irq,
774b51f8 849 .handle_irq = vic_handle_irq,
e1a3c74f
MB		 850 .map_io = crag6410_map_io,
851 .init_machine = crag6410_machine_init,
cc8f252b 852 .init_late = s3c64xx_init_late,
e1a3c74f 853 .timer = &s3c24xx_timer,
ff84ded2 854 .restart = s3c64xx_restart,
e1a3c74f 855MACHINE_END
Linux 6.x block layer and io_uring tree(s)