Merge branches 'amd-iommu/fixes' and 'dma-debug/fixes' into iommu/fixes
[linux-2.6-block.git] / arch / arm / mach-s3c6410 / mach-smdk6410.c
CommitLineData
5718df9d
BD
1/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
096941ed 23#include <linux/i2c.h>
438a5d42
BD
24#include <linux/fb.h>
25#include <linux/gpio.h>
26#include <linux/delay.h>
3056ea0a 27#include <linux/smsc911x.h>
42015c13 28#include <linux/regulator/fixed.h>
438a5d42 29
ecc558ac
MB
30#ifdef CONFIG_SMDK6410_WM1190_EV1
31#include <linux/mfd/wm8350/core.h>
32#include <linux/mfd/wm8350/pmic.h>
33#endif
438a5d42
BD
34
35#include <video/platform_lcd.h>
5718df9d
BD
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
438a5d42 42#include <mach/regs-fb.h>
5718df9d
BD
43#include <mach/map.h>
44
45#include <asm/irq.h>
46#include <asm/mach-types.h>
47
48#include <plat/regs-serial.h>
d6662c35
BD
49#include <plat/regs-modem.h>
50#include <plat/regs-gpio.h>
51#include <plat/regs-sys.h>
d85fa24c 52#include <plat/iic.h>
438a5d42 53#include <plat/fb.h>
3056ea0a 54#include <plat/gpio-cfg.h>
5718df9d
BD
55
56#include <plat/s3c6410.h>
57#include <plat/clock.h>
58#include <plat/devs.h>
59#include <plat/cpu.h>
60
61#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
62#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
63#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
64
65static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
66 [0] = {
67 .hwport = 0,
68 .flags = 0,
bd258e52
MH
69 .ucon = UCON,
70 .ulcon = ULCON,
71 .ufcon = UFCON,
5718df9d
BD
72 },
73 [1] = {
74 .hwport = 1,
75 .flags = 0,
bd258e52
MH
76 .ucon = UCON,
77 .ulcon = ULCON,
78 .ufcon = UFCON,
79 },
80 [2] = {
81 .hwport = 2,
82 .flags = 0,
83 .ucon = UCON,
84 .ulcon = ULCON,
85 .ufcon = UFCON,
86 },
87 [3] = {
88 .hwport = 3,
89 .flags = 0,
90 .ucon = UCON,
91 .ulcon = ULCON,
92 .ufcon = UFCON,
5718df9d
BD
93 },
94};
95
438a5d42
BD
96/* framebuffer and LCD setup. */
97
98/* GPF15 = LCD backlight control
99 * GPF13 => Panel power
100 * GPN5 = LCD nRESET signal
101 * PWM_TOUT1 => backlight brightness
102 */
103
104static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
105 unsigned int power)
106{
107 if (power) {
108 gpio_direction_output(S3C64XX_GPF(13), 1);
109 gpio_direction_output(S3C64XX_GPF(15), 1);
110
111 /* fire nRESET on power up */
112 gpio_direction_output(S3C64XX_GPN(5), 0);
113 msleep(10);
114 gpio_direction_output(S3C64XX_GPN(5), 1);
115 msleep(1);
116 } else {
117 gpio_direction_output(S3C64XX_GPF(15), 0);
118 gpio_direction_output(S3C64XX_GPF(13), 0);
119 }
120}
121
122static struct plat_lcd_data smdk6410_lcd_power_data = {
123 .set_power = smdk6410_lcd_power_set,
124};
125
126static struct platform_device smdk6410_lcd_powerdev = {
127 .name = "platform-lcd",
128 .dev.parent = &s3c_device_fb.dev,
129 .dev.platform_data = &smdk6410_lcd_power_data,
130};
131
132static struct s3c_fb_pd_win smdk6410_fb_win0 = {
133 /* this is to ensure we use win0 */
134 .win_mode = {
135 .pixclock = 41094,
136 .left_margin = 8,
137 .right_margin = 13,
138 .upper_margin = 7,
139 .lower_margin = 5,
140 .hsync_len = 3,
141 .vsync_len = 1,
142 .xres = 800,
143 .yres = 480,
144 },
145 .max_bpp = 32,
146 .default_bpp = 16,
147};
148
149/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
150static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
151 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
152 .win[0] = &smdk6410_fb_win0,
153 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
154 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
155};
156
3056ea0a
MB
157static struct resource smdk6410_smsc911x_resources[] = {
158 [0] = {
159 .start = 0x18000000,
160 .end = 0x18000000 + SZ_64K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = S3C_EINT(10),
165 .end = S3C_EINT(10),
166 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
167 },
168};
169
170static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
171 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
172 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
173 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
174 .phy_interface = PHY_INTERFACE_MODE_MII,
175};
176
177
178static struct platform_device smdk6410_smsc911x = {
179 .name = "smsc911x",
180 .id = -1,
181 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
182 .resource = &smdk6410_smsc911x_resources[0],
183 .dev = {
184 .platform_data = &smdk6410_smsc911x_pdata,
185 },
186};
187
42015c13
MB
188#ifdef CONFIG_REGULATOR
189static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
190 {
191 /* WM8580 */
192 .supply = "PVDD",
193 .dev_name = "0-001b",
194 },
195 {
196 /* WM8580 */
197 .supply = "AVDD",
198 .dev_name = "0-001b",
199 },
200};
201
202static struct regulator_init_data smdk6410_b_pwr_5v_data = {
203 .constraints = {
204 .always_on = 1,
205 },
206 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
207 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
208};
209
210static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
211 .supply_name = "B_PWR_5V",
212 .microvolts = 5000000,
213 .init_data = &smdk6410_b_pwr_5v_data,
d3cf4489 214 .gpio = -EINVAL,
42015c13
MB
215};
216
217static struct platform_device smdk6410_b_pwr_5v = {
218 .name = "reg-fixed-voltage",
219 .id = -1,
220 .dev = {
221 .platform_data = &smdk6410_b_pwr_5v_pdata,
222 },
223};
224#endif
225
027191a8 226static struct map_desc smdk6410_iodesc[] = {};
5718df9d
BD
227
228static struct platform_device *smdk6410_devices[] __initdata = {
b24636cf 229#ifdef CONFIG_SMDK6410_SD_CH0
39057f23 230 &s3c_device_hsmmc0,
b24636cf
BD
231#endif
232#ifdef CONFIG_SMDK6410_SD_CH1
233 &s3c_device_hsmmc1,
234#endif
d85fa24c 235 &s3c_device_i2c0,
d7ea3743 236 &s3c_device_i2c1,
438a5d42 237 &s3c_device_fb,
98fd63ba 238 &s3c_device_usb,
06fa1d37 239 &s3c_device_usb_hsotg,
42015c13
MB
240
241#ifdef CONFIG_REGULATOR
242 &smdk6410_b_pwr_5v,
243#endif
438a5d42 244 &smdk6410_lcd_powerdev,
3056ea0a
MB
245
246 &smdk6410_smsc911x,
5718df9d
BD
247};
248
ecc558ac
MB
249#ifdef CONFIG_SMDK6410_WM1190_EV1
250/* S3C64xx internal logic & PLL */
251static struct regulator_init_data wm8350_dcdc1_data = {
252 .constraints = {
253 .name = "PVDD_INT/PVDD_PLL",
254 .min_uV = 1200000,
255 .max_uV = 1200000,
256 .always_on = 1,
257 .apply_uV = 1,
258 },
259};
260
261/* Memory */
262static struct regulator_init_data wm8350_dcdc3_data = {
263 .constraints = {
264 .name = "PVDD_MEM",
265 .min_uV = 1800000,
266 .max_uV = 1800000,
267 .always_on = 1,
268 .state_mem = {
269 .uV = 1800000,
270 .mode = REGULATOR_MODE_NORMAL,
271 .enabled = 1,
272 },
273 .initial_state = PM_SUSPEND_MEM,
274 },
275};
276
277/* USB, EXT, PCM, ADC/DAC, USB, MMC */
42015c13
MB
278static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
279 {
280 /* WM8580 */
281 .supply = "DVDD",
282 .dev_name = "0-001b",
283 },
284};
285
ecc558ac
MB
286static struct regulator_init_data wm8350_dcdc4_data = {
287 .constraints = {
288 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
289 .min_uV = 3000000,
290 .max_uV = 3000000,
291 .always_on = 1,
292 },
42015c13
MB
293 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
294 .consumer_supplies = wm8350_dcdc4_consumers,
ecc558ac
MB
295};
296
297/* ARM core */
e3980b6a
MB
298static struct regulator_consumer_supply dcdc6_consumers[] = {
299 {
300 .supply = "vddarm",
301 }
302};
303
ecc558ac
MB
304static struct regulator_init_data wm8350_dcdc6_data = {
305 .constraints = {
306 .name = "PVDD_ARM",
307 .min_uV = 1000000,
308 .max_uV = 1300000,
309 .always_on = 1,
e3980b6a 310 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
ecc558ac 311 },
e3980b6a
MB
312 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
313 .consumer_supplies = dcdc6_consumers,
5718df9d
BD
314};
315
ecc558ac
MB
316/* Alive */
317static struct regulator_init_data wm8350_ldo1_data = {
318 .constraints = {
319 .name = "PVDD_ALIVE",
320 .min_uV = 1200000,
321 .max_uV = 1200000,
322 .always_on = 1,
323 .apply_uV = 1,
324 },
325};
326
327/* OTG */
328static struct regulator_init_data wm8350_ldo2_data = {
329 .constraints = {
330 .name = "PVDD_OTG",
331 .min_uV = 3300000,
332 .max_uV = 3300000,
f53aee29 333 .always_on = 1,
ecc558ac
MB
334 },
335};
336
337/* LCD */
338static struct regulator_init_data wm8350_ldo3_data = {
339 .constraints = {
340 .name = "PVDD_LCD",
341 .min_uV = 3000000,
342 .max_uV = 3000000,
f53aee29 343 .always_on = 1,
ecc558ac
MB
344 },
345};
346
347/* OTGi/1190-EV1 HPVDD & AVDD */
348static struct regulator_init_data wm8350_ldo4_data = {
349 .constraints = {
350 .name = "PVDD_OTGI/HPVDD/AVDD",
351 .min_uV = 1200000,
352 .max_uV = 1200000,
353 .apply_uV = 1,
f53aee29 354 .always_on = 1,
ecc558ac
MB
355 },
356};
357
358static struct {
359 int regulator;
360 struct regulator_init_data *initdata;
361} wm1190_regulators[] = {
362 { WM8350_DCDC_1, &wm8350_dcdc1_data },
363 { WM8350_DCDC_3, &wm8350_dcdc3_data },
364 { WM8350_DCDC_4, &wm8350_dcdc4_data },
365 { WM8350_DCDC_6, &wm8350_dcdc6_data },
366 { WM8350_LDO_1, &wm8350_ldo1_data },
367 { WM8350_LDO_2, &wm8350_ldo2_data },
368 { WM8350_LDO_3, &wm8350_ldo3_data },
369 { WM8350_LDO_4, &wm8350_ldo4_data },
370};
371
372static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
373{
374 int i;
375
a3323b72
MB
376 /* Configure the IRQ line */
377 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
378
ecc558ac
MB
379 /* Instantiate the regulators */
380 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
381 wm8350_register_regulator(wm8350,
382 wm1190_regulators[i].regulator,
383 wm1190_regulators[i].initdata);
384
385 return 0;
386}
387
388static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
389 .init = smdk6410_wm8350_init,
db9256f3 390 .irq_high = 1,
ecc558ac
MB
391};
392#endif
393
096941ed
BD
394static struct i2c_board_info i2c_devs0[] __initdata = {
395 { I2C_BOARD_INFO("24c08", 0x50), },
77897479 396 { I2C_BOARD_INFO("wm8580", 0x1b), },
ecc558ac
MB
397
398#ifdef CONFIG_SMDK6410_WM1190_EV1
399 { I2C_BOARD_INFO("wm8350", 0x1a),
400 .platform_data = &smdk6410_wm8350_pdata,
401 .irq = S3C_EINT(12),
402 },
403#endif
096941ed
BD
404};
405
406static struct i2c_board_info i2c_devs1[] __initdata = {
407 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
5718df9d
BD
408};
409
5718df9d
BD
410static void __init smdk6410_map_io(void)
411{
d6662c35
BD
412 u32 tmp;
413
5718df9d
BD
414 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
415 s3c24xx_init_clocks(12000000);
416 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
d6662c35
BD
417
418 /* set the LCD type */
419
420 tmp = __raw_readl(S3C64XX_SPCON);
421 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
422 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
423 __raw_writel(tmp, S3C64XX_SPCON);
424
425 /* remove the lcd bypass */
426 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
427 tmp &= ~MIFPCON_LCD_BYPASS;
428 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
5718df9d
BD
429}
430
431static void __init smdk6410_machine_init(void)
432{
d85fa24c 433 s3c_i2c0_set_platdata(NULL);
d7ea3743 434 s3c_i2c1_set_platdata(NULL);
438a5d42 435 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
096941ed 436
b7f9a94b
MB
437 gpio_request(S3C64XX_GPN(5), "LCD power");
438 gpio_request(S3C64XX_GPF(13), "LCD power");
439 gpio_request(S3C64XX_GPF(15), "LCD power");
440
096941ed
BD
441 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
442 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
443
5718df9d
BD
444 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
445}
446
447MACHINE_START(SMDK6410, "SMDK6410")
448 /* Maintainer: Ben Dooks <ben@fluff.org> */
449 .phys_io = S3C_PA_UART & 0xfff00000,
450 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
451 .boot_params = S3C64XX_PA_SDRAM + 0x100,
452
453 .init_irq = s3c6410_init_irq,
454 .map_io = smdk6410_map_io,
455 .init_machine = smdk6410_machine_init,
456 .timer = &s3c24xx_timer,
457MACHINE_END