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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/s3c2410.c |
2 | * | |
3 | * Copyright (c) 2003-2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://www.simtec.co.uk/products/EB2410ITX/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
1ec7269f | 19 | #include <linux/gpio.h> |
e425382e | 20 | #include <linux/clk.h> |
4a858cfc | 21 | #include <linux/device.h> |
bb072c3c | 22 | #include <linux/syscore_ops.h> |
b6d1f542 | 23 | #include <linux/serial_core.h> |
d052d1be | 24 | #include <linux/platform_device.h> |
fced80c7 | 25 | #include <linux/io.h> |
1da177e4 LT |
26 | |
27 | #include <asm/mach/arch.h> | |
28 | #include <asm/mach/map.h> | |
29 | #include <asm/mach/irq.h> | |
30 | ||
a09e64fb | 31 | #include <mach/hardware.h> |
1da177e4 | 32 | #include <asm/irq.h> |
9f97da78 | 33 | #include <asm/system_misc.h> |
1da177e4 | 34 | |
e425382e BD |
35 | #include <plat/cpu-freq.h> |
36 | ||
a09e64fb | 37 | #include <mach/regs-clock.h> |
a2b7ba9c | 38 | #include <plat/regs-serial.h> |
1da177e4 | 39 | |
a2b7ba9c BD |
40 | #include <plat/cpu.h> |
41 | #include <plat/devs.h> | |
d5120ae7 | 42 | #include <plat/clock.h> |
e24b864a | 43 | #include <plat/pll.h> |
bb072c3c | 44 | #include <plat/pm.h> |
b27b0727 | 45 | #include <plat/watchdog-reset.h> |
1da177e4 | 46 | |
1ec7269f BD |
47 | #include <plat/gpio-core.h> |
48 | #include <plat/gpio-cfg.h> | |
49 | #include <plat/gpio-cfg-helpers.h> | |
50 | ||
d8fdec16 HS |
51 | #include "common.h" |
52 | ||
1da177e4 LT |
53 | /* Initial IO mappings */ |
54 | ||
55 | static struct map_desc s3c2410_iodesc[] __initdata = { | |
1da177e4 | 56 | IODESC_ENT(CLKPWR), |
1da177e4 | 57 | IODESC_ENT(TIMER), |
62ee914e | 58 | IODESC_ENT(WATCHDOG), |
1da177e4 LT |
59 | }; |
60 | ||
1da177e4 LT |
61 | /* our uart devices */ |
62 | ||
1da177e4 LT |
63 | /* uart registration process */ |
64 | ||
65 | void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
66 | { | |
66a9b49a | 67 | s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no); |
1da177e4 LT |
68 | } |
69 | ||
70 | /* s3c2410_map_io | |
71 | * | |
72 | * register the standard cpu IO areas, and any passed in from the | |
73 | * machine specific initialisation. | |
74 | */ | |
75 | ||
74b265d4 | 76 | void __init s3c2410_map_io(void) |
1da177e4 | 77 | { |
782d8a3c KK |
78 | s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; |
79 | s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; | |
1ec7269f | 80 | |
1da177e4 | 81 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); |
1da177e4 LT |
82 | } |
83 | ||
e425382e | 84 | void __init_or_cpufreq s3c2410_setup_clocks(void) |
1da177e4 | 85 | { |
e425382e | 86 | struct clk *xtal_clk; |
1da177e4 | 87 | unsigned long tmp; |
e425382e | 88 | unsigned long xtal; |
1da177e4 LT |
89 | unsigned long fclk; |
90 | unsigned long hclk; | |
91 | unsigned long pclk; | |
92 | ||
e425382e BD |
93 | xtal_clk = clk_get(NULL, "xtal"); |
94 | xtal = clk_get_rate(xtal_clk); | |
95 | clk_put(xtal_clk); | |
96 | ||
1da177e4 LT |
97 | /* now we've got our machine bits initialised, work out what |
98 | * clocks we've got */ | |
99 | ||
e24b864a | 100 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); |
1da177e4 LT |
101 | |
102 | tmp = __raw_readl(S3C2410_CLKDIVN); | |
103 | ||
104 | /* work out clock scalings */ | |
105 | ||
106 | hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); | |
107 | pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); | |
108 | ||
109 | /* print brieft summary of clocks, etc */ | |
110 | ||
111 | printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | |
112 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | |
113 | ||
114 | /* initialise the clocks here, to allow other things like the | |
115 | * console to use them | |
116 | */ | |
117 | ||
e425382e BD |
118 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
119 | } | |
120 | ||
ad787595 BD |
121 | /* fake ARMCLK for use with cpufreq, etc. */ |
122 | ||
123 | static struct clk s3c2410_armclk = { | |
124 | .name = "armclk", | |
125 | .parent = &clk_f, | |
126 | .id = -1, | |
127 | }; | |
128 | ||
0cfb26e1 TA |
129 | static struct clk_lookup s3c2410_clk_lookup[] = { |
130 | CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), | |
131 | CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), | |
132 | }; | |
133 | ||
e425382e BD |
134 | void __init s3c2410_init_clocks(int xtal) |
135 | { | |
136 | s3c24xx_register_baseclocks(xtal); | |
137 | s3c2410_setup_clocks(); | |
99c13853 | 138 | s3c2410_baseclk_add(); |
ad787595 | 139 | s3c24xx_register_clock(&s3c2410_armclk); |
0cfb26e1 | 140 | clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); |
1da177e4 LT |
141 | } |
142 | ||
4a858cfc | 143 | struct bus_type s3c2410_subsys = { |
af5ca3f4 | 144 | .name = "s3c2410-core", |
4a858cfc | 145 | .dev_name = "s3c2410-core", |
a341305e BD |
146 | }; |
147 | ||
f0176794 | 148 | /* Note, we would have liked to name this s3c2410-core, but we cannot |
4a858cfc | 149 | * register two subsystems with the same name. |
f0176794 | 150 | */ |
4a858cfc | 151 | struct bus_type s3c2410a_subsys = { |
f0176794 | 152 | .name = "s3c2410a-core", |
4a858cfc | 153 | .dev_name = "s3c2410a-core", |
f0176794 BD |
154 | }; |
155 | ||
4a858cfc KS |
156 | static struct device s3c2410_dev = { |
157 | .bus = &s3c2410_subsys, | |
a341305e BD |
158 | }; |
159 | ||
4a858cfc | 160 | /* need to register the subsystem before we actually register the device, and |
a341305e | 161 | * we also need to ensure that it has been initialised before any of the |
6db3eee4 | 162 | * drivers even try to use it (even if not on an s3c2410 based system) |
a341305e BD |
163 | * as a driver which may support both 2410 and 2440 may try and use it. |
164 | */ | |
165 | ||
166 | static int __init s3c2410_core_init(void) | |
167 | { | |
4a858cfc | 168 | return subsys_system_register(&s3c2410_subsys, NULL); |
a341305e BD |
169 | } |
170 | ||
171 | core_initcall(s3c2410_core_init); | |
172 | ||
f0176794 BD |
173 | static int __init s3c2410a_core_init(void) |
174 | { | |
4a858cfc | 175 | return subsys_system_register(&s3c2410a_subsys, NULL); |
f0176794 BD |
176 | } |
177 | ||
178 | core_initcall(s3c2410a_core_init); | |
179 | ||
1da177e4 LT |
180 | int __init s3c2410_init(void) |
181 | { | |
182 | printk("S3C2410: Initialising architecture\n"); | |
183 | ||
fb630b9f | 184 | #ifdef CONFIG_PM |
bb072c3c RW |
185 | register_syscore_ops(&s3c2410_pm_syscore_ops); |
186 | register_syscore_ops(&s3c24xx_irq_syscore_ops); | |
d8fdec16 | 187 | #endif |
bb072c3c | 188 | |
4a858cfc | 189 | return device_register(&s3c2410_dev); |
1da177e4 | 190 | } |
f0176794 BD |
191 | |
192 | int __init s3c2410a_init(void) | |
193 | { | |
4a858cfc | 194 | s3c2410_dev.bus = &s3c2410a_subsys; |
f0176794 BD |
195 | return s3c2410_init(); |
196 | } | |
b27b0727 KK |
197 | |
198 | void s3c2410_restart(char mode, const char *cmd) | |
199 | { | |
200 | if (mode == 's') { | |
201 | soft_restart(0); | |
202 | } | |
203 | ||
204 | arch_wdt_reset(); | |
205 | ||
206 | /* we'll take a jump through zero as a poor second */ | |
207 | soft_restart(0); | |
208 | } |