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1 | /* linux/arch/arm/plat-s3c24xx/pm.c |
2 | * | |
ccae941e | 3 | * Copyright (c) 2004-2006 Simtec Electronics |
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4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C24XX Power Manager (Suspend-To-RAM) support | |
7 | * | |
8 | * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Parts based on arch/arm/mach-pxa/pm.c | |
25 | * | |
26 | * Thanks to Dimitry Andric for debugging | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/suspend.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/time.h> | |
ec976d6e | 33 | #include <linux/gpio.h> |
a21765a7 | 34 | #include <linux/interrupt.h> |
a21765a7 | 35 | #include <linux/serial_core.h> |
fced80c7 | 36 | #include <linux/io.h> |
a21765a7 | 37 | |
a2b7ba9c | 38 | #include <plat/regs-serial.h> |
a09e64fb RK |
39 | #include <mach/regs-clock.h> |
40 | #include <mach/regs-gpio.h> | |
a09e64fb | 41 | #include <mach/regs-irq.h> |
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42 | |
43 | #include <asm/mach/time.h> | |
44 | ||
40b956f0 | 45 | #include <plat/gpio-cfg.h> |
a2b7ba9c | 46 | #include <plat/pm.h> |
a21765a7 | 47 | |
37c3adca KK |
48 | #include "regs-mem.h" |
49 | ||
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50 | #define PFX "s3c24xx-pm: " |
51 | ||
52 | static struct sleep_save core_save[] = { | |
53 | SAVE_ITEM(S3C2410_LOCKTIME), | |
54 | SAVE_ITEM(S3C2410_CLKCON), | |
55 | ||
56 | /* we restore the timings here, with the proviso that the board | |
57 | * brings the system up in an slower, or equal frequency setting | |
58 | * to the original system. | |
59 | * | |
60 | * if we cannot guarantee this, then things are going to go very | |
61 | * wrong here, as we modify the refresh and both pll settings. | |
62 | */ | |
63 | ||
64 | SAVE_ITEM(S3C2410_BWSCON), | |
65 | SAVE_ITEM(S3C2410_BANKCON0), | |
66 | SAVE_ITEM(S3C2410_BANKCON1), | |
67 | SAVE_ITEM(S3C2410_BANKCON2), | |
68 | SAVE_ITEM(S3C2410_BANKCON3), | |
69 | SAVE_ITEM(S3C2410_BANKCON4), | |
70 | SAVE_ITEM(S3C2410_BANKCON5), | |
71 | ||
e425382e | 72 | #ifndef CONFIG_CPU_FREQ |
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73 | SAVE_ITEM(S3C2410_CLKDIVN), |
74 | SAVE_ITEM(S3C2410_MPLLCON), | |
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75 | SAVE_ITEM(S3C2410_REFRESH), |
76 | #endif | |
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77 | SAVE_ITEM(S3C2410_UPLLCON), |
78 | SAVE_ITEM(S3C2410_CLKSLOW), | |
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79 | }; |
80 | ||
62feee64 | 81 | static struct sleep_save misc_save[] = { |
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82 | SAVE_ITEM(S3C2410_DCLKCON), |
83 | }; | |
84 | ||
549c7e33 | 85 | /* s3c_pm_check_resume_pin |
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86 | * |
87 | * check to see if the pin is configured correctly for sleep mode, and | |
88 | * make any necessary adjustments if it is not | |
89 | */ | |
90 | ||
549c7e33 | 91 | static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) |
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92 | { |
93 | unsigned long irqstate; | |
94 | unsigned long pinstate; | |
5690a626 | 95 | int irq = gpio_to_irq(pin); |
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96 | |
97 | if (irqoffs < 4) | |
98 | irqstate = s3c_irqwake_intmask & (1L<<irqoffs); | |
99 | else | |
100 | irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); | |
101 | ||
9933847b | 102 | pinstate = s3c_gpio_getcfg(pin); |
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103 | |
104 | if (!irqstate) { | |
105 | if (pinstate == S3C2410_GPIO_IRQ) | |
9933847b | 106 | S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); |
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107 | } else { |
108 | if (pinstate == S3C2410_GPIO_IRQ) { | |
6419711a | 109 | S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); |
40b956f0 | 110 | s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); |
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111 | } |
112 | } | |
113 | } | |
114 | ||
2261e0e6 | 115 | /* s3c_pm_configure_extint |
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116 | * |
117 | * configure all external interrupt pins | |
118 | */ | |
119 | ||
2261e0e6 | 120 | void s3c_pm_configure_extint(void) |
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121 | { |
122 | int pin; | |
123 | ||
124 | /* for each of the external interrupts (EINT0..EINT15) we | |
48fc7f7e | 125 | * need to check whether it is an external interrupt source, |
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126 | * and then configure it as an input if it is not |
127 | */ | |
128 | ||
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129 | for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) { |
130 | s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0)); | |
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131 | } |
132 | ||
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133 | for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) { |
134 | s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8); | |
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135 | } |
136 | } | |
137 | ||
62feee64 | 138 | |
2261e0e6 | 139 | void s3c_pm_restore_core(void) |
a21765a7 | 140 | { |
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141 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); |
142 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
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143 | } |
144 | ||
2261e0e6 | 145 | void s3c_pm_save_core(void) |
a21765a7 | 146 | { |
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147 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); |
148 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
a21765a7 | 149 | } |
2261e0e6 | 150 |