Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm...
[linux-2.6-block.git] / arch / arm / mach-s3c24xx / pm.c
CommitLineData
84b21701
KK
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2004-2006 Simtec Electronics
4// Ben Dooks <ben@simtec.co.uk>
5//
6// S3C24XX Power Manager (Suspend-To-RAM) support
7//
8// See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9//
10// Parts based on arch/arm/mach-pxa/pm.c
11//
12// Thanks to Dimitry Andric for debugging
a21765a7
BD
13
14#include <linux/init.h>
15#include <linux/suspend.h>
16#include <linux/errno.h>
17#include <linux/time.h>
ec976d6e 18#include <linux/gpio.h>
a21765a7 19#include <linux/interrupt.h>
a21765a7 20#include <linux/serial_core.h>
334a1c70 21#include <linux/serial_s3c.h>
fced80c7 22#include <linux/io.h>
a21765a7 23
a09e64fb
RK
24#include <mach/regs-clock.h>
25#include <mach/regs-gpio.h>
a09e64fb 26#include <mach/regs-irq.h>
b0161caa 27#include <mach/gpio-samsung.h>
a21765a7
BD
28
29#include <asm/mach/time.h>
30
40b956f0 31#include <plat/gpio-cfg.h>
a2b7ba9c 32#include <plat/pm.h>
a21765a7 33
37c3adca
KK
34#include "regs-mem.h"
35
a21765a7
BD
36#define PFX "s3c24xx-pm: "
37
4f506daf 38#ifdef CONFIG_PM_SLEEP
a21765a7 39static struct sleep_save core_save[] = {
a21765a7
BD
40 /* we restore the timings here, with the proviso that the board
41 * brings the system up in an slower, or equal frequency setting
42 * to the original system.
43 *
44 * if we cannot guarantee this, then things are going to go very
45 * wrong here, as we modify the refresh and both pll settings.
46 */
47
48 SAVE_ITEM(S3C2410_BWSCON),
49 SAVE_ITEM(S3C2410_BANKCON0),
50 SAVE_ITEM(S3C2410_BANKCON1),
51 SAVE_ITEM(S3C2410_BANKCON2),
52 SAVE_ITEM(S3C2410_BANKCON3),
53 SAVE_ITEM(S3C2410_BANKCON4),
54 SAVE_ITEM(S3C2410_BANKCON5),
a21765a7 55};
4f506daf 56#endif
a21765a7 57
549c7e33 58/* s3c_pm_check_resume_pin
a21765a7
BD
59 *
60 * check to see if the pin is configured correctly for sleep mode, and
61 * make any necessary adjustments if it is not
62*/
63
549c7e33 64static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
a21765a7
BD
65{
66 unsigned long irqstate;
67 unsigned long pinstate;
5690a626 68 int irq = gpio_to_irq(pin);
a21765a7
BD
69
70 if (irqoffs < 4)
71 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
72 else
73 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
74
9933847b 75 pinstate = s3c_gpio_getcfg(pin);
a21765a7
BD
76
77 if (!irqstate) {
78 if (pinstate == S3C2410_GPIO_IRQ)
9933847b 79 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
a21765a7
BD
80 } else {
81 if (pinstate == S3C2410_GPIO_IRQ) {
6419711a 82 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
40b956f0 83 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
a21765a7
BD
84 }
85 }
86}
87
2261e0e6 88/* s3c_pm_configure_extint
a21765a7
BD
89 *
90 * configure all external interrupt pins
91*/
92
2261e0e6 93void s3c_pm_configure_extint(void)
a21765a7
BD
94{
95 int pin;
96
97 /* for each of the external interrupts (EINT0..EINT15) we
48fc7f7e 98 * need to check whether it is an external interrupt source,
a21765a7
BD
99 * and then configure it as an input if it is not
100 */
101
070276d5
BD
102 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
103 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
a21765a7
BD
104 }
105
070276d5
BD
106 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
107 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
a21765a7
BD
108 }
109}
110
4f506daf 111#ifdef CONFIG_PM_SLEEP
2261e0e6 112void s3c_pm_restore_core(void)
a21765a7 113{
6419711a 114 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
a21765a7
BD
115}
116
2261e0e6 117void s3c_pm_save_core(void)
a21765a7 118{
2261e0e6 119 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
a21765a7 120}
4f506daf 121#endif