Commit | Line | Data |
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a21765a7 | 1 | /* linux/arch/arm/mach-s3c2440/mach-rx3715.c |
1da177e4 | 2 | * |
e02f8664 | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * http://www.handhelds.org/projects/rx3715.html | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
8d717a52 | 18 | #include <linux/memblock.h> |
1da177e4 LT |
19 | #include <linux/timer.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/console.h> | |
edbaa603 | 23 | #include <linux/device.h> |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/serial_core.h> |
26 | #include <linux/serial.h> | |
fced80c7 | 27 | #include <linux/io.h> |
272eb575 BD |
28 | #include <linux/mtd/mtd.h> |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/mtd/nand_ecc.h> | |
31 | #include <linux/mtd/partitions.h> | |
32 | ||
1da177e4 | 33 | #include <asm/mach/arch.h> |
1da177e4 | 34 | #include <asm/mach/irq.h> |
232910d6 KK |
35 | #include <asm/mach/map.h> |
36 | ||
37 | #include <linux/platform_data/mtd-nand-s3c2410.h> | |
1da177e4 | 38 | |
1da177e4 LT |
39 | #include <asm/irq.h> |
40 | #include <asm/mach-types.h> | |
41 | ||
232910d6 KK |
42 | #include <mach/fb.h> |
43 | #include <mach/hardware.h> | |
a09e64fb RK |
44 | #include <mach/regs-gpio.h> |
45 | #include <mach/regs-lcd.h> | |
e838ffc2 | 46 | |
d5120ae7 | 47 | #include <plat/clock.h> |
a2b7ba9c | 48 | #include <plat/cpu.h> |
232910d6 | 49 | #include <plat/devs.h> |
a2b7ba9c | 50 | #include <plat/pm.h> |
232910d6 | 51 | #include <plat/regs-serial.h> |
1da177e4 | 52 | |
b27b0727 | 53 | #include "common.h" |
232910d6 | 54 | #include "h1940.h" |
b27b0727 | 55 | |
1da177e4 LT |
56 | static struct map_desc rx3715_iodesc[] __initdata = { |
57 | /* dump ISA space somewhere unused */ | |
58 | ||
ff6ffa82 BD |
59 | { |
60 | .virtual = (u32)S3C24XX_VA_ISA_WORD, | |
61 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
62 | .length = SZ_1M, | |
63 | .type = MT_DEVICE, | |
64 | }, { | |
65 | .virtual = (u32)S3C24XX_VA_ISA_BYTE, | |
66 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
67 | .length = SZ_1M, | |
68 | .type = MT_DEVICE, | |
69 | }, | |
1da177e4 LT |
70 | }; |
71 | ||
1da177e4 LT |
72 | static struct s3c2410_uartcfg rx3715_uartcfgs[] = { |
73 | [0] = { | |
74 | .hwport = 0, | |
75 | .flags = 0, | |
76 | .ucon = 0x3c5, | |
77 | .ulcon = 0x03, | |
78 | .ufcon = 0x51, | |
afba7f91 | 79 | .clk_sel = S3C2410_UCON_CLKSEL3, |
1da177e4 LT |
80 | }, |
81 | [1] = { | |
82 | .hwport = 1, | |
83 | .flags = 0, | |
84 | .ucon = 0x3c5, | |
85 | .ulcon = 0x03, | |
86 | .ufcon = 0x00, | |
afba7f91 | 87 | .clk_sel = S3C2410_UCON_CLKSEL3, |
1da177e4 LT |
88 | }, |
89 | /* IR port */ | |
90 | [2] = { | |
91 | .hwport = 2, | |
92 | .uart_flags = UPF_CONS_FLOW, | |
93 | .ucon = 0x3c5, | |
94 | .ulcon = 0x43, | |
95 | .ufcon = 0x51, | |
afba7f91 | 96 | .clk_sel = S3C2410_UCON_CLKSEL3, |
1da177e4 LT |
97 | } |
98 | }; | |
99 | ||
e838ffc2 BD |
100 | /* framebuffer lcd controller information */ |
101 | ||
09fe75f6 | 102 | static struct s3c2410fb_display rx3715_lcdcfg __initdata = { |
f28ef573 KH |
103 | .lcdcon5 = S3C2410_LCDCON5_INVVLINE | |
104 | S3C2410_LCDCON5_FRM565 | | |
105 | S3C2410_LCDCON5_HWSWP, | |
e838ffc2 | 106 | |
1f411537 KH |
107 | .type = S3C2410_LCDCON1_TFT, |
108 | .width = 240, | |
109 | .height = 320, | |
110 | ||
69816699 | 111 | .pixclock = 260000, |
1f411537 KH |
112 | .xres = 240, |
113 | .yres = 320, | |
114 | .bpp = 16, | |
115 | .left_margin = 36, | |
116 | .right_margin = 36, | |
93d11f5a | 117 | .hsync_len = 8, |
5f20f69b KH |
118 | .upper_margin = 6, |
119 | .lower_margin = 7, | |
93d11f5a | 120 | .vsync_len = 3, |
09fe75f6 KH |
121 | }; |
122 | ||
123 | static struct s3c2410fb_mach_info rx3715_fb_info __initdata = { | |
124 | ||
125 | .displays = &rx3715_lcdcfg, | |
126 | .num_displays = 1, | |
127 | .default_display = 0, | |
128 | ||
e838ffc2 BD |
129 | .lpcsel = 0xf82, |
130 | ||
131 | .gpccon = 0xaa955699, | |
132 | .gpccon_mask = 0xffc003cc, | |
133 | .gpcup = 0x0000ffff, | |
134 | .gpcup_mask = 0xffffffff, | |
135 | ||
136 | .gpdcon = 0xaa95aaa1, | |
137 | .gpdcon_mask = 0xffc0fff0, | |
138 | .gpdup = 0x0000faff, | |
139 | .gpdup_mask = 0xffffffff, | |
e838ffc2 BD |
140 | }; |
141 | ||
2a3a1804 | 142 | static struct mtd_partition __initdata rx3715_nand_part[] = { |
272eb575 BD |
143 | [0] = { |
144 | .name = "Whole Flash", | |
145 | .offset = 0, | |
146 | .size = MTDPART_SIZ_FULL, | |
147 | .mask_flags = MTD_WRITEABLE, | |
148 | } | |
149 | }; | |
150 | ||
2a3a1804 | 151 | static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = { |
272eb575 BD |
152 | [0] = { |
153 | .name = "Internal", | |
154 | .nr_chips = 1, | |
155 | .nr_partitions = ARRAY_SIZE(rx3715_nand_part), | |
156 | .partitions = rx3715_nand_part, | |
157 | }, | |
158 | }; | |
159 | ||
2a3a1804 | 160 | static struct s3c2410_platform_nand __initdata rx3715_nand_info = { |
272eb575 BD |
161 | .tacls = 25, |
162 | .twrph0 = 50, | |
163 | .twrph1 = 15, | |
164 | .nr_sets = ARRAY_SIZE(rx3715_nand_sets), | |
165 | .sets = rx3715_nand_sets, | |
166 | }; | |
167 | ||
1da177e4 | 168 | static struct platform_device *rx3715_devices[] __initdata = { |
b813248c | 169 | &s3c_device_ohci, |
1da177e4 LT |
170 | &s3c_device_lcd, |
171 | &s3c_device_wdt, | |
3e1b776c | 172 | &s3c_device_i2c0, |
1da177e4 | 173 | &s3c_device_iis, |
272eb575 | 174 | &s3c_device_nand, |
1da177e4 LT |
175 | }; |
176 | ||
5fe10ab1 | 177 | static void __init rx3715_map_io(void) |
1da177e4 LT |
178 | { |
179 | s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); | |
180 | s3c24xx_init_clocks(16934000); | |
181 | s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); | |
1da177e4 LT |
182 | } |
183 | ||
98c672cf RK |
184 | /* H1940 and RX3715 need to reserve this for suspend */ |
185 | static void __init rx3715_reserve(void) | |
186 | { | |
8d717a52 RK |
187 | memblock_reserve(0x30003000, 0x1000); |
188 | memblock_reserve(0x30081000, 0x1000); | |
98c672cf RK |
189 | } |
190 | ||
5fe10ab1 | 191 | static void __init rx3715_init_irq(void) |
1da177e4 LT |
192 | { |
193 | s3c24xx_init_irq(); | |
194 | } | |
195 | ||
1da177e4 LT |
196 | static void __init rx3715_init_machine(void) |
197 | { | |
b1dfe1f1 | 198 | #ifdef CONFIG_PM_H1940 |
bbf6f280 | 199 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
b1dfe1f1 | 200 | #endif |
4e59c25d | 201 | s3c_pm_init(); |
bbf6f280 | 202 | |
2a3a1804 | 203 | s3c_nand_set_platdata(&rx3715_nand_info); |
09fe75f6 | 204 | s3c24xx_fb_set_platdata(&rx3715_fb_info); |
57e5171c | 205 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); |
1da177e4 | 206 | } |
e838ffc2 | 207 | |
1da177e4 | 208 | MACHINE_START(RX3715, "IPAQ-RX3715") |
afdd225d | 209 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
69d50710 | 210 | .atag_offset = 0x100, |
e9dea0c6 | 211 | .map_io = rx3715_map_io, |
98c672cf | 212 | .reserve = rx3715_reserve, |
e9dea0c6 RK |
213 | .init_irq = rx3715_init_irq, |
214 | .init_machine = rx3715_init_machine, | |
6bb27d73 | 215 | .init_time = s3c24xx_timer_init, |
c1ba544f | 216 | .restart = s3c244x_restart, |
1da177e4 | 217 | MACHINE_END |