[linux-2.6-block.git] / arch / arm / mach-s3c24xx / mach-jive.c

/* linux/arch/arm/mach-s3c2410/mach-jive.c
 *
 * Copyright 2007 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>

#include <video/ili9320.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/fb.h>
#include <mach/gpio-samsung.h>

#include <asm/mach-types.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <plat/samsung-time.h>

#include "common.h"
#include "s3c2412-power.h"

static struct map_desc jive_iodesc[] __initdata = {
};

#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg jive_uartcfgs[] = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	}
};

/* Jive flash assignment
 *
 * 0x00000000-0x00028000 : uboot
 * 0x00028000-0x0002c000 : uboot env
 * 0x0002c000-0x00030000 : spare
 * 0x00030000-0x00200000 : zimage A
 * 0x00200000-0x01600000 : cramfs A
 * 0x01600000-0x017d0000 : zimage B
 * 0x017d0000-0x02bd0000 : cramfs B
 * 0x02bd0000-0x03fd0000 : yaffs
 */
static struct mtd_partition __initdata jive_imageA_nand_part[] = {

#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	/* Don't allow access to the bootloader from linux */
	{
		.name           = "uboot",
		.offset         = 0,
		.size           = (160 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},

	/* spare */
        {
                .name           = "spare",
                .offset         = (176 * SZ_1K),
                .size           = (16 * SZ_1K),
        },
#endif

	/* booted images */
        {
		.name		= "kernel (ro)",
		.offset		= (192 * SZ_1K),
		.size		= (SZ_2M) - (192 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
        }, {
                .name           = "root (ro)",
                .offset         = (SZ_2M),
                .size           = (20 * SZ_1M),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
        },

	/* yaffs */
	{
		.name		= "yaffs",
		.offset		= (44 * SZ_1M),
		.size		= (20 * SZ_1M),
	},

	/* bootloader environment */
	{
                .name		= "env",
		.offset		= (160 * SZ_1K),
		.size		= (16 * SZ_1K),
	},

	/* upgrade images */
        {
		.name		= "zimage",
		.offset		= (22 * SZ_1M),
		.size		= (2 * SZ_1M) - (192 * SZ_1K),
        }, {
		.name		= "cramfs",
		.offset		= (24 * SZ_1M) - (192*SZ_1K),
		.size		= (20 * SZ_1M),
        },
};

static struct mtd_partition __initdata jive_imageB_nand_part[] = {

#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	/* Don't allow access to the bootloader from linux */
	{
		.name           = "uboot",
		.offset         = 0,
		.size           = (160 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},

	/* spare */
        {
                .name           = "spare",
                .offset         = (176 * SZ_1K),
                .size           = (16 * SZ_1K),
        },
#endif

	/* booted images */
        {
		.name           = "kernel (ro)",
		.offset         = (22 * SZ_1M),
		.size           = (2 * SZ_1M) - (192 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
        },
	{
		.name		= "root (ro)",
		.offset		= (24 * SZ_1M) - (192 * SZ_1K),
                .size		= (20 * SZ_1M),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},

	/* yaffs */
	{
		.name		= "yaffs",
		.offset		= (44 * SZ_1M),
		.size		= (20 * SZ_1M),
        },

	/* bootloader environment */
	{
		.name		= "env",
		.offset		= (160 * SZ_1K),
		.size		= (16 * SZ_1K),
	},

	/* upgrade images */
	{
		.name		= "zimage",
		.offset		= (192 * SZ_1K),
		.size		= (2 * SZ_1M) - (192 * SZ_1K),
        }, {
		.name		= "cramfs",
		.offset		= (2 * SZ_1M),
		.size		= (20 * SZ_1M),
        },
};

static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
	[0] = {
		.name           = "flash",
		.nr_chips       = 1,
		.nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
		.partitions     = jive_imageA_nand_part,
	},
};

static struct s3c2410_platform_nand __initdata jive_nand_info = {
	/* set taken from osiris nand timings, possibly still conservative */
	.tacls		= 30,
	.twrph0		= 55,
	.twrph1		= 40,
	.sets		= jive_nand_sets,
	.nr_sets	= ARRAY_SIZE(jive_nand_sets),
};

static int __init jive_mtdset(char *options)
{
	struct s3c2410_nand_set *nand = &jive_nand_sets[0];
	unsigned long set;

	if (options == NULL || options[0] == '\0')
		return 0;

	if (kstrtoul(options, 10, &set)) {
		printk(KERN_ERR "failed to parse mtdset=%s\n", options);
		return 0;
	}

	switch (set) {
	case 1:
		nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
		nand->partitions = jive_imageB_nand_part;
	case 0:
		/* this is already setup in the nand info */
		break;
	default:
		printk(KERN_ERR "Unknown mtd set %ld specified,"
		       "using default.", set);
	}

	return 0;
}

/* parse the mtdset= option given to the kernel command line */
__setup("mtdset=", jive_mtdset);

/* LCD timing and setup */

#define LCD_XRES	 (240)
#define LCD_YRES	 (320)
#define LCD_LEFT_MARGIN  (12)
#define LCD_RIGHT_MARGIN (12)
#define LCD_LOWER_MARGIN (12)
#define LCD_UPPER_MARGIN (12)
#define LCD_VSYNC	 (2)
#define LCD_HSYNC	 (2)

#define LCD_REFRESH	 (60)

#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)

static struct s3c2410fb_display jive_vgg2432a4_display[] = {
	[0] = {
		.width		= LCD_XRES,
		.height		= LCD_YRES,
		.xres		= LCD_XRES,
		.yres		= LCD_YRES,
		.left_margin	= LCD_LEFT_MARGIN,
		.right_margin	= LCD_RIGHT_MARGIN,
		.upper_margin	= LCD_UPPER_MARGIN,
		.lower_margin	= LCD_LOWER_MARGIN,
		.hsync_len	= LCD_HSYNC,
		.vsync_len	= LCD_VSYNC,

		.pixclock	= (1000000000000LL /
				   (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),

		.bpp		= 16,
		.type		= (S3C2410_LCDCON1_TFT16BPP |
				   S3C2410_LCDCON1_TFT),

		.lcdcon5	= (S3C2410_LCDCON5_FRM565 |
				   S3C2410_LCDCON5_INVVLINE |
				   S3C2410_LCDCON5_INVVFRAME |
				   S3C2410_LCDCON5_INVVDEN |
				   S3C2410_LCDCON5_PWREN),
	},
};

/* todo - put into gpio header */

#define S3C2410_GPCCON_MASK(x)	(3 << ((x) * 2))
#define S3C2410_GPDCON_MASK(x)	(3 << ((x) * 2))

static struct s3c2410fb_mach_info jive_lcd_config = {
	.displays	 = jive_vgg2432a4_display,
	.num_displays	 = ARRAY_SIZE(jive_vgg2432a4_display),
	.default_display = 0,

	/* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
	 * and disable the pull down resistors on pins we are using for LCD
	 * data. */

	.gpcup		= (0xf << 1) | (0x3f << 10),

	.gpccon		= (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
			   S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
			   S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
			   S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
			   S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),

	.gpccon_mask	= (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
			   S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
			   S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
			   S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
			   S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),

	.gpdup		= (0x3f << 2) | (0x3f << 10),

	.gpdcon		= (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
			   S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
			   S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
			   S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
			   S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
			   S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),

	.gpdcon_mask	= (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
			   S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
			   S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
			   S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
			   S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
			   S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
};

/* ILI9320 support. */

static void jive_lcm_reset(unsigned int set)
{
	printk(KERN_DEBUG "%s(%d)\n", __func__, set);

	gpio_set_value(S3C2410_GPG(13), set);
}

#undef LCD_UPPER_MARGIN
#define LCD_UPPER_MARGIN 2

static struct ili9320_platdata jive_lcm_config = {
	.hsize		= LCD_XRES,
	.vsize		= LCD_YRES,

	.reset		= jive_lcm_reset,
	.suspend	= ILI9320_SUSPEND_DEEP,

	.entry_mode	= ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
	.display2	= (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
			   ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
	.display3	= 0x0,
	.display4	= 0x0,
	.rgb_if1	= (ILI9320_RGBIF1_RIM_RGB18 |
			   ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
	.rgb_if2	= ILI9320_RGBIF2_DPL,
	.interface2	= 0x0,
	.interface3	= 0x3,
	.interface4	= (ILI9320_INTERFACE4_RTNE(16) |
			   ILI9320_INTERFACE4_DIVE(1)),
	.interface5	= 0x0,
	.interface6	= 0x0,
};

/* LCD SPI support */

static struct spi_gpio_platform_data jive_lcd_spi = {
	.sck		= S3C2410_GPG(8),
	.mosi		= S3C2410_GPB(8),
	.miso		= SPI_GPIO_NO_MISO,
};

static struct platform_device jive_device_lcdspi = {
	.name		= "spi-gpio",
	.id		= 1,
	.dev.platform_data = &jive_lcd_spi,
};


/* WM8750 audio code SPI definition */

static struct spi_gpio_platform_data jive_wm8750_spi = {
	.sck		= S3C2410_GPB(4),
	.mosi		= S3C2410_GPB(9),
	.miso		= SPI_GPIO_NO_MISO,
};

static struct platform_device jive_device_wm8750 = {
	.name		= "spi-gpio",
	.id		= 2,
	.dev.platform_data = &jive_wm8750_spi,
};

/* JIVE SPI devices. */

static struct spi_board_info __initdata jive_spi_devs[] = {
	[0] = {
		.modalias	= "VGG2432A4",
		.bus_num	= 1,
		.chip_select	= 0,
		.mode		= SPI_MODE_3,	/* CPOL=1, CPHA=1 */
		.max_speed_hz	= 100000,
		.platform_data	= &jive_lcm_config,
		.controller_data = (void *)S3C2410_GPB(7),
	}, {
		.modalias	= "WM8750",
		.bus_num	= 2,
		.chip_select	= 0,
		.mode		= SPI_MODE_0,	/* CPOL=0, CPHA=0 */
		.max_speed_hz	= 100000,
		.controller_data = (void *)S3C2410_GPH(10),
	},
};

/* I2C bus and device configuration. */

static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
	.frequency	= 80 * 1000,
	.flags		= S3C_IICFLG_FILTER,
	.sda_delay	= 2,
};

static struct i2c_board_info jive_i2c_devs[] __initdata = {
	[0] = {
		I2C_BOARD_INFO("lis302dl", 0x1c),
		.irq	= IRQ_EINT14,
	},
};

/* The platform devices being used. */

static struct platform_device *jive_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_rtc,
	&s3c_device_wdt,
	&s3c_device_i2c0,
	&s3c_device_lcd,
	&jive_device_lcdspi,
	&jive_device_wm8750,
	&s3c_device_nand,
	&s3c_device_usbgadget,
	&s3c2412_device_dma,
};

static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
	.vbus_pin	= S3C2410_GPG(1),		/* detect is on GPG1 */
};

/* Jive power management device */

#ifdef CONFIG_PM
static int jive_pm_suspend(void)
{
	/* Write the magic value u-boot uses to check for resume into
	 * the INFORM0 register, and ensure INFORM1 is set to the
	 * correct address to resume from. */

	__raw_writel(0x2BED, S3C2412_INFORM0);
	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);

	return 0;
}

static void jive_pm_resume(void)
{
	__raw_writel(0x0, S3C2412_INFORM0);
}

#else
#define jive_pm_suspend NULL
#define jive_pm_resume NULL
#endif

static struct syscore_ops jive_pm_syscore_ops = {
	.suspend	= jive_pm_suspend,
	.resume		= jive_pm_resume,
};

static void __init jive_map_io(void)
{
	s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
	s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}

static void __init jive_init_time(void)
{
	s3c2412_init_clocks(12000000);
	samsung_timer_init();
}

static void jive_power_off(void)
{
	printk(KERN_INFO "powering system down...\n");

	gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
	gpio_free(S3C2410_GPC(5));
}

static void __init jive_machine_init(void)
{
	/* register system core operations for managing low level suspend */

	register_syscore_ops(&jive_pm_syscore_ops);

	/* write our sleep configurations for the IO. Pull down all unused
	 * IO, ensure that we have turned off all peripherals we do not
	 * need, and configure the ones we do need. */

	/* Port B sleep */

	__raw_writel(S3C2412_SLPCON_IN(0)   |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_HIGH(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_HIGH(7) |
		     S3C2412_SLPCON_PULL(8) |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);

	/* Port C sleep */

	__raw_writel(S3C2412_SLPCON_PULL(0) |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_PULL(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_LOW(6)  |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_PULL(7) |
		     S3C2412_SLPCON_PULL(8) |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_PULL(10) |
		     S3C2412_SLPCON_PULL(11) |
		     S3C2412_SLPCON_PULL(12) |
		     S3C2412_SLPCON_PULL(13) |
		     S3C2412_SLPCON_PULL(14) |
		     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);

	/* Port D sleep */

	__raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);

	/* Port F sleep */

	__raw_writel(S3C2412_SLPCON_LOW(0)  |
		     S3C2412_SLPCON_LOW(1)  |
		     S3C2412_SLPCON_LOW(2)  |
		     S3C2412_SLPCON_EINT(3) |
		     S3C2412_SLPCON_EINT(4) |
		     S3C2412_SLPCON_EINT(5) |
		     S3C2412_SLPCON_EINT(6) |
		     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);

	/* Port G sleep */

	__raw_writel(S3C2412_SLPCON_IN(0)    |
		     S3C2412_SLPCON_IN(1)    |
		     S3C2412_SLPCON_IN(2)    |
		     S3C2412_SLPCON_IN(3)    |
		     S3C2412_SLPCON_IN(4)    |
		     S3C2412_SLPCON_IN(5)    |
		     S3C2412_SLPCON_IN(6)    |
		     S3C2412_SLPCON_IN(7)    |
		     S3C2412_SLPCON_PULL(8)  |
		     S3C2412_SLPCON_PULL(9)  |
		     S3C2412_SLPCON_IN(10)   |
		     S3C2412_SLPCON_PULL(11) |
		     S3C2412_SLPCON_PULL(12) |
		     S3C2412_SLPCON_PULL(13) |
		     S3C2412_SLPCON_IN(14)   |
		     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);

	/* Port H sleep */

	__raw_writel(S3C2412_SLPCON_PULL(0) |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_PULL(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_IN(7)   |
		     S3C2412_SLPCON_IN(8)   |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);

	/* initialise the power management now we've setup everything. */

	s3c_pm_init();

	/** TODO - check that this is after the cmdline option! */
	s3c_nand_set_platdata(&jive_nand_info);

	/* initialise the spi */

	gpio_request(S3C2410_GPG(13), "lcm reset");
	gpio_direction_output(S3C2410_GPG(13), 0);

	gpio_request(S3C2410_GPB(7), "jive spi");
	gpio_direction_output(S3C2410_GPB(7), 1);

	gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
	gpio_free(S3C2410_GPB(6));

	gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
	gpio_free(S3C2410_GPG(8));

	/* initialise the WM8750 spi */

	gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
	gpio_direction_output(S3C2410_GPH(10), 1);

	/* Turn off suspend on both USB ports, and switch the
	 * selectable USB port to USB device mode. */

	s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
			      S3C2410_MISCCR_USBSUSPND0 |
			      S3C2410_MISCCR_USBSUSPND1, 0x0);

	s3c24xx_udc_set_platdata(&jive_udc_cfg);
	s3c24xx_fb_set_platdata(&jive_lcd_config);

	spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));

	s3c_i2c0_set_platdata(&jive_i2c_cfg);
	i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));

	pm_power_off = jive_power_off;

	platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
}

MACHINE_START(JIVE, "JIVE")
	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
	.atag_offset	= 0x100,

	.init_irq	= s3c2412_init_irq,
	.map_io		= jive_map_io,
	.init_machine	= jive_machine_init,
	.init_time	= jive_init_time,
MACHINE_END
Commit	Line	Data
9db829f4 BD	1	/* linux/arch/arm/mach-s3c2410/mach-jive.c
	2	*
	3	* Copyright 2007 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
ec976d6e	19	#include <linux/gpio.h>
bb072c3c	20	#include <linux/syscore_ops.h>
9db829f4	21	#include <linux/serial_core.h>
334a1c70	22	#include <linux/serial_s3c.h>
9db829f4	23	#include <linux/platform_device.h>
d10d8a5f	24	#include <linux/i2c.h>
9db829f4	25
c2c1708f BD	26	#include <video/ili9320.h>
c2c1708f BD	27
a2ed4065	28	#include <linux/spi/spi.h>
932036ce	29	#include <linux/spi/spi_gpio.h>
a2ed4065	30
9db829f4 BD	31	#include <asm/mach/arch.h>
	32	#include <asm/mach/map.h>
	33	#include <asm/mach/irq.h>
	34
436d42c6 AB	35	#include <linux/platform_data/mtd-nand-s3c2410.h>
436d42c6 AB	36	#include <linux/platform_data/i2c-s3c2410.h>
9db829f4	37
a09e64fb	38	#include <mach/regs-gpio.h>
a09e64fb	39	#include <mach/regs-lcd.h>
a09e64fb	40	#include <mach/fb.h>
b0161caa	41	#include <mach/gpio-samsung.h>
9db829f4 BD	42
	43	#include <asm/mach-types.h>
	44
	45	#include <linux/mtd/mtd.h>
	46	#include <linux/mtd/nand.h>
	47	#include <linux/mtd/nand_ecc.h>
	48	#include <linux/mtd/partitions.h>
	49
40b956f0	50	#include <plat/gpio-cfg.h>
a2b7ba9c BD	51	#include <plat/devs.h>
	52	#include <plat/cpu.h>
	53	#include <plat/pm.h>
436d42c6	54	#include <linux/platform_data/usb-s3c2410_udc.h>
7f78b6eb	55	#include <plat/samsung-time.h>
9db829f4	56
e1a621da	57	#include "common.h"
14cce0e7 KK	58	#include "s3c2412-power.h"
14cce0e7 KK	59
9db829f4 BD	60	static struct map_desc jive_iodesc[] __initdata = {
	61	};
	62
	63	#define UCON S3C2410_UCON_DEFAULT
	64	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE
	65	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	66
	67	static struct s3c2410_uartcfg jive_uartcfgs[] = {
	68	[0] = {
	69	.hwport = 0,
	70	.flags = 0,
	71	.ucon = UCON,
	72	.ulcon = ULCON,
	73	.ufcon = UFCON,
	74	},
	75	[1] = {
	76	.hwport = 1,
	77	.flags = 0,
	78	.ucon = UCON,
	79	.ulcon = ULCON,
	80	.ufcon = UFCON,
	81	},
	82	[2] = {
	83	.hwport = 2,
	84	.flags = 0,
	85	.ucon = UCON,
	86	.ulcon = ULCON,
	87	.ufcon = UFCON,
	88	}
	89	};
	90
	91	/* Jive flash assignment
	92	*
	93	* 0x00000000-0x00028000 : uboot
	94	* 0x00028000-0x0002c000 : uboot env
	95	* 0x0002c000-0x00030000 : spare
	96	* 0x00030000-0x00200000 : zimage A
	97	* 0x00200000-0x01600000 : cramfs A
	98	* 0x01600000-0x017d0000 : zimage B
	99	* 0x017d0000-0x02bd0000 : cramfs B
	100	* 0x02bd0000-0x03fd0000 : yaffs
	101	*/
2a3a1804	102	static struct mtd_partition __initdata jive_imageA_nand_part[] = {
9db829f4 BD	103
	104	#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	105	/* Don't allow access to the bootloader from linux */
	106	{
	107	.name = "uboot",
	108	.offset = 0,
	109	.size = (160 * SZ_1K),
	110	.mask_flags = MTD_WRITEABLE, /* force read-only */
	111	},
	112
	113	/* spare */
	114	{
	115	.name = "spare",
	116	.offset = (176 * SZ_1K),
	117	.size = (16 * SZ_1K),
	118	},
	119	#endif
	120
	121	/* booted images */
	122	{
	123	.name = "kernel (ro)",
	124	.offset = (192 * SZ_1K),
	125	.size = (SZ_2M) - (192 * SZ_1K),
	126	.mask_flags = MTD_WRITEABLE, /* force read-only */
	127	}, {
	128	.name = "root (ro)",
	129	.offset = (SZ_2M),
	130	.size = (20 * SZ_1M),
	131	.mask_flags = MTD_WRITEABLE, /* force read-only */
	132	},
	133
	134	/* yaffs */
	135	{
	136	.name = "yaffs",
	137	.offset = (44 * SZ_1M),
	138	.size = (20 * SZ_1M),
	139	},
	140
	141	/* bootloader environment */
	142	{
	143	.name = "env",
	144	.offset = (160 * SZ_1K),
	145	.size = (16 * SZ_1K),
	146	},
	147
	148	/* upgrade images */
	149	{
	150	.name = "zimage",
	151	.offset = (22 * SZ_1M),
	152	.size = (2 * SZ_1M) - (192 * SZ_1K),
	153	}, {
	154	.name = "cramfs",
	155	.offset = (24 * SZ_1M) - (192*SZ_1K),
	156	.size = (20 * SZ_1M),
	157	},
	158	};
	159
2a3a1804	160	static struct mtd_partition __initdata jive_imageB_nand_part[] = {
9db829f4 BD	161
	162	#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	163	/* Don't allow access to the bootloader from linux */
	164	{
	165	.name = "uboot",
	166	.offset = 0,
	167	.size = (160 * SZ_1K),
	168	.mask_flags = MTD_WRITEABLE, /* force read-only */
	169	},
	170
	171	/* spare */
	172	{
	173	.name = "spare",
	174	.offset = (176 * SZ_1K),
	175	.size = (16 * SZ_1K),
	176	},
	177	#endif
	178
	179	/* booted images */
	180	{
	181	.name = "kernel (ro)",
	182	.offset = (22 * SZ_1M),
	183	.size = (2 * SZ_1M) - (192 * SZ_1K),
	184	.mask_flags = MTD_WRITEABLE, /* force read-only */
	185	},
	186	{
	187	.name = "root (ro)",
	188	.offset = (24 * SZ_1M) - (192 * SZ_1K),
	189	.size = (20 * SZ_1M),
	190	.mask_flags = MTD_WRITEABLE, /* force read-only */
	191	},
	192
	193	/* yaffs */
	194	{
	195	.name = "yaffs",
	196	.offset = (44 * SZ_1M),
	197	.size = (20 * SZ_1M),
	198	},
	199
	200	/* bootloader environment */
	201	{
	202	.name = "env",
	203	.offset = (160 * SZ_1K),
	204	.size = (16 * SZ_1K),
	205	},
	206
	207	/* upgrade images */
	208	{
	209	.name = "zimage",
	210	.offset = (192 * SZ_1K),
	211	.size = (2 * SZ_1M) - (192 * SZ_1K),
	212	}, {
	213	.name = "cramfs",
	214	.offset = (2 * SZ_1M),
	215	.size = (20 * SZ_1M),
	216	},
	217	};
	218
2a3a1804	219	static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
9db829f4 BD	220	[0] = {
	221	.name = "flash",
	222	.nr_chips = 1,
	223	.nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
	224	.partitions = jive_imageA_nand_part,
	225	},
	226	};
	227
2a3a1804	228	static struct s3c2410_platform_nand __initdata jive_nand_info = {
9db829f4 BD	229	/* set taken from osiris nand timings, possibly still conservative */
	230	.tacls = 30,
	231	.twrph0 = 55,
	232	.twrph1 = 40,
	233	.sets = jive_nand_sets,
	234	.nr_sets = ARRAY_SIZE(jive_nand_sets),
	235	};
	236
	237	static int __init jive_mtdset(char *options)
	238	{
	239	struct s3c2410_nand_set *nand = &jive_nand_sets[0];
	240	unsigned long set;
	241
	242	if (options == NULL \|\| options[0] == '\0')
	243	return 0;
	244
5c2432cb	245	if (kstrtoul(options, 10, &set)) {
9db829f4 BD	246	printk(KERN_ERR "failed to parse mtdset=%s\n", options);
	247	return 0;
	248	}
	249
	250	switch (set) {
	251	case 1:
	252	nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
	253	nand->partitions = jive_imageB_nand_part;
	254	case 0:
	255	/* this is already setup in the nand info */
	256	break;
	257	default:
	258	printk(KERN_ERR "Unknown mtd set %ld specified,"
	259	"using default.", set);
	260	}
	261
	262	return 0;
	263	}
	264
	265	/* parse the mtdset= option given to the kernel command line */
	266	__setup("mtdset=", jive_mtdset);
	267
0f99263c BD	268	/* LCD timing and setup */
	269
	270	#define LCD_XRES (240)
	271	#define LCD_YRES (320)
	272	#define LCD_LEFT_MARGIN (12)
	273	#define LCD_RIGHT_MARGIN (12)
	274	#define LCD_LOWER_MARGIN (12)
	275	#define LCD_UPPER_MARGIN (12)
	276	#define LCD_VSYNC (2)
	277	#define LCD_HSYNC (2)
	278
	279	#define LCD_REFRESH (60)
	280
	281	#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
	282	#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
	283
59c1ab60	284	static struct s3c2410fb_display jive_vgg2432a4_display[] = {
0f99263c BD	285	[0] = {
	286	.width = LCD_XRES,
	287	.height = LCD_YRES,
	288	.xres = LCD_XRES,
	289	.yres = LCD_YRES,
	290	.left_margin = LCD_LEFT_MARGIN,
	291	.right_margin = LCD_RIGHT_MARGIN,
	292	.upper_margin = LCD_UPPER_MARGIN,
	293	.lower_margin = LCD_LOWER_MARGIN,
	294	.hsync_len = LCD_HSYNC,
	295	.vsync_len = LCD_VSYNC,
	296
	297	.pixclock = (1000000000000LL /
	298	(LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
	299
	300	.bpp = 16,
	301	.type = (S3C2410_LCDCON1_TFT16BPP \|
	302	S3C2410_LCDCON1_TFT),
	303
	304	.lcdcon5 = (S3C2410_LCDCON5_FRM565 \|
	305	S3C2410_LCDCON5_INVVLINE \|
	306	S3C2410_LCDCON5_INVVFRAME \|
	307	S3C2410_LCDCON5_INVVDEN \|
	308	S3C2410_LCDCON5_PWREN),
	309	},
	310	};
	311
	312	/* todo - put into gpio header */
	313
	314	#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
	315	#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
	316
59c1ab60	317	static struct s3c2410fb_mach_info jive_lcd_config = {
0f99263c BD	318	.displays = jive_vgg2432a4_display,
	319	.num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
	320	.default_display = 0,
	321
	322	/* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
	323	* and disable the pull down resistors on pins we are using for LCD
	324	* data. */
	325
	326	.gpcup = (0xf << 1) \| (0x3f << 10),
	327
	328	.gpccon = (S3C2410_GPC1_VCLK \| S3C2410_GPC2_VLINE \|
	329	S3C2410_GPC3_VFRAME \| S3C2410_GPC4_VM \|
	330	S3C2410_GPC10_VD2 \| S3C2410_GPC11_VD3 \|
	331	S3C2410_GPC12_VD4 \| S3C2410_GPC13_VD5 \|
	332	S3C2410_GPC14_VD6 \| S3C2410_GPC15_VD7),
	333
	334	.gpccon_mask = (S3C2410_GPCCON_MASK(1) \| S3C2410_GPCCON_MASK(2) \|
	335	S3C2410_GPCCON_MASK(3) \| S3C2410_GPCCON_MASK(4) \|
	336	S3C2410_GPCCON_MASK(10) \| S3C2410_GPCCON_MASK(11) \|
	337	S3C2410_GPCCON_MASK(12) \| S3C2410_GPCCON_MASK(13) \|
	338	S3C2410_GPCCON_MASK(14) \| S3C2410_GPCCON_MASK(15)),
	339
	340	.gpdup = (0x3f << 2) \| (0x3f << 10),
	341
	342	.gpdcon = (S3C2410_GPD2_VD10 \| S3C2410_GPD3_VD11 \|
	343	S3C2410_GPD4_VD12 \| S3C2410_GPD5_VD13 \|
	344	S3C2410_GPD6_VD14 \| S3C2410_GPD7_VD15 \|
	345	S3C2410_GPD10_VD18 \| S3C2410_GPD11_VD19 \|
	346	S3C2410_GPD12_VD20 \| S3C2410_GPD13_VD21 \|
	347	S3C2410_GPD14_VD22 \| S3C2410_GPD15_VD23),
	348
	349	.gpdcon_mask = (S3C2410_GPDCON_MASK(2) \| S3C2410_GPDCON_MASK(3) \|
	350	S3C2410_GPDCON_MASK(4) \| S3C2410_GPDCON_MASK(5) \|
	351	S3C2410_GPDCON_MASK(6) \| S3C2410_GPDCON_MASK(7) \|
	352	S3C2410_GPDCON_MASK(10) \| S3C2410_GPDCON_MASK(11)\|
	353	S3C2410_GPDCON_MASK(12) \| S3C2410_GPDCON_MASK(13)\|
	354	S3C2410_GPDCON_MASK(14) \| S3C2410_GPDCON_MASK(15)),
	355	};
	356
c2c1708f BD	357	/* ILI9320 support. */
	358
	359	static void jive_lcm_reset(unsigned int set)
	360	{
	361	printk(KERN_DEBUG "%s(%d)\n", __func__, set);
	362
afc84ad1	363	gpio_set_value(S3C2410_GPG(13), set);
c2c1708f BD	364	}
	365
	366	#undef LCD_UPPER_MARGIN
	367	#define LCD_UPPER_MARGIN 2
	368
	369	static struct ili9320_platdata jive_lcm_config = {
	370	.hsize = LCD_XRES,
	371	.vsize = LCD_YRES,
	372
	373	.reset = jive_lcm_reset,
	374	.suspend = ILI9320_SUSPEND_DEEP,
	375
	376	.entry_mode = ILI9320_ENTRYMODE_ID(3) \| ILI9320_ENTRYMODE_BGR,
	377	.display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) \|
	378	ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
	379	.display3 = 0x0,
	380	.display4 = 0x0,
	381	.rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 \|
	382	ILI9320_RGBIF1_RM \| ILI9320_RGBIF1_CLK_RGBIF),
	383	.rgb_if2 = ILI9320_RGBIF2_DPL,
	384	.interface2 = 0x0,
	385	.interface3 = 0x3,
	386	.interface4 = (ILI9320_INTERFACE4_RTNE(16) \|
	387	ILI9320_INTERFACE4_DIVE(1)),
	388	.interface5 = 0x0,
	389	.interface6 = 0x0,
	390	};
	391
a2ed4065 BD	392	/* LCD SPI support */
a2ed4065 BD	393
932036ce PK	394	static struct spi_gpio_platform_data jive_lcd_spi = {
	395	.sck = S3C2410_GPG(8),
	396	.mosi = S3C2410_GPB(8),
	397	.miso = SPI_GPIO_NO_MISO,
a2ed4065 BD	398	};
	399
	400	static struct platform_device jive_device_lcdspi = {
932036ce	401	.name = "spi-gpio",
a2ed4065	402	.id = 1,
a2ed4065 BD	403	.dev.platform_data = &jive_lcd_spi,
	404	};
	405
fd2de272	406
932036ce	407	/* WM8750 audio code SPI definition */
fd2de272	408
932036ce PK	409	static struct spi_gpio_platform_data jive_wm8750_spi = {
	410	.sck = S3C2410_GPB(4),
	411	.mosi = S3C2410_GPB(9),
	412	.miso = SPI_GPIO_NO_MISO,
fd2de272 BD	413	};
	414
	415	static struct platform_device jive_device_wm8750 = {
932036ce	416	.name = "spi-gpio",
fd2de272	417	.id = 2,
fd2de272 BD	418	.dev.platform_data = &jive_wm8750_spi,
fd2de272 BD	419	};
a2ed4065	420
fd2de272	421	/* JIVE SPI devices. */
a2ed4065 BD	422
	423	static struct spi_board_info __initdata jive_spi_devs[] = {
	424	[0] = {
	425	.modalias = "VGG2432A4",
	426	.bus_num = 1,
	427	.chip_select = 0,
	428	.mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
	429	.max_speed_hz = 100000,
c2c1708f	430	.platform_data = &jive_lcm_config,
932036ce	431	.controller_data = (void *)S3C2410_GPB(7),
fd2de272 BD	432	}, {
	433	.modalias = "WM8750",
	434	.bus_num = 2,
	435	.chip_select = 0,
	436	.mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
	437	.max_speed_hz = 100000,
932036ce	438	.controller_data = (void *)S3C2410_GPH(10),
a2ed4065 BD	439	},
	440	};
	441
d10d8a5f BD	442	/* I2C bus and device configuration. */
d10d8a5f BD	443
3e1b776c	444	static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
c564e6ae	445	.frequency = 80 * 1000,
d10d8a5f BD	446	.flags = S3C_IICFLG_FILTER,
	447	.sda_delay = 2,
	448	};
	449
3e1b776c	450	static struct i2c_board_info jive_i2c_devs[] __initdata = {
d10d8a5f BD	451	[0] = {
	452	I2C_BOARD_INFO("lis302dl", 0x1c),
	453	.irq = IRQ_EINT14,
	454	},
	455	};
	456
	457	/* The platform devices being used. */
	458
9db829f4	459	static struct platform_device *jive_devices[] __initdata = {
b813248c	460	&s3c_device_ohci,
9db829f4 BD	461	&s3c_device_rtc,
9db829f4 BD	462	&s3c_device_wdt,
3e1b776c	463	&s3c_device_i2c0,
0f99263c	464	&s3c_device_lcd,
a2ed4065	465	&jive_device_lcdspi,
fd2de272	466	&jive_device_wm8750,
9db829f4 BD	467	&s3c_device_nand,
9db829f4 BD	468	&s3c_device_usbgadget,
f2dda07d	469	&s3c2412_device_dma,
9db829f4 BD	470	};
	471
	472	static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
070276d5	473	.vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
9db829f4 BD	474	};
	475
	476	/* Jive power management device */
	477
	478	#ifdef CONFIG_PM
bb072c3c	479	static int jive_pm_suspend(void)
9db829f4 BD	480	{
	481	/* Write the magic value u-boot uses to check for resume into
	482	* the INFORM0 register, and ensure INFORM1 is set to the
	483	* correct address to resume from. */
	484
	485	__raw_writel(0x2BED, S3C2412_INFORM0);
ef30e144	486	__raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
9db829f4 BD	487
	488	return 0;
	489	}
	490
bb072c3c	491	static void jive_pm_resume(void)
9db829f4 BD	492	{
9db829f4 BD	493	__raw_writel(0x0, S3C2412_INFORM0);
9db829f4 BD	494	}
	495
	496	#else
	497	#define jive_pm_suspend NULL
	498	#define jive_pm_resume NULL
	499	#endif
	500
bb072c3c	501	static struct syscore_ops jive_pm_syscore_ops = {
9db829f4 BD	502	.suspend = jive_pm_suspend,
	503	.resume = jive_pm_resume,
	504	};
	505
9db829f4 BD	506	static void __init jive_map_io(void)
	507	{
	508	s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
9db829f4	509	s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
7f78b6eb	510	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
9db829f4 BD	511	}
9db829f4 BD	512
3c27f314 HS	513	static void __init jive_init_time(void)
	514	{
	515	s3c2412_init_clocks(12000000);
	516	samsung_timer_init();
	517	}
	518
dd1086f4 BD	519	static void jive_power_off(void)
	520	{
	521	printk(KERN_INFO "powering system down...\n");
	522
42aa322c SN	523	gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
42aa322c SN	524	gpio_free(S3C2410_GPC(5));
dd1086f4 BD	525	}
dd1086f4 BD	526
9db829f4 BD	527	static void __init jive_machine_init(void)
9db829f4 BD	528	{
bb072c3c	529	/* register system core operations for managing low level suspend */
9db829f4	530
bb072c3c	531	register_syscore_ops(&jive_pm_syscore_ops);
9db829f4	532
54c272ac BD	533	/* write our sleep configurations for the IO. Pull down all unused
	534	* IO, ensure that we have turned off all peripherals we do not
	535	* need, and configure the ones we do need. */
	536
	537	/* Port B sleep */
	538
	539	__raw_writel(S3C2412_SLPCON_IN(0) \|
	540	S3C2412_SLPCON_PULL(1) \|
	541	S3C2412_SLPCON_HIGH(2) \|
	542	S3C2412_SLPCON_PULL(3) \|
	543	S3C2412_SLPCON_PULL(4) \|
	544	S3C2412_SLPCON_PULL(5) \|
	545	S3C2412_SLPCON_PULL(6) \|
	546	S3C2412_SLPCON_HIGH(7) \|
	547	S3C2412_SLPCON_PULL(8) \|
	548	S3C2412_SLPCON_PULL(9) \|
	549	S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
	550
	551	/* Port C sleep */
	552
	553	__raw_writel(S3C2412_SLPCON_PULL(0) \|
	554	S3C2412_SLPCON_PULL(1) \|
	555	S3C2412_SLPCON_PULL(2) \|
	556	S3C2412_SLPCON_PULL(3) \|
	557	S3C2412_SLPCON_PULL(4) \|
	558	S3C2412_SLPCON_PULL(5) \|
	559	S3C2412_SLPCON_LOW(6) \|
	560	S3C2412_SLPCON_PULL(6) \|
	561	S3C2412_SLPCON_PULL(7) \|
	562	S3C2412_SLPCON_PULL(8) \|
	563	S3C2412_SLPCON_PULL(9) \|
	564	S3C2412_SLPCON_PULL(10) \|
	565	S3C2412_SLPCON_PULL(11) \|
	566	S3C2412_SLPCON_PULL(12) \|
	567	S3C2412_SLPCON_PULL(13) \|
	568	S3C2412_SLPCON_PULL(14) \|
	569	S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
	570
	571	/* Port D sleep */
	572
	573	__raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
	574
	575	/* Port F sleep */
	576
	577	__raw_writel(S3C2412_SLPCON_LOW(0) \|
	578	S3C2412_SLPCON_LOW(1) \|
	579	S3C2412_SLPCON_LOW(2) \|
	580	S3C2412_SLPCON_EINT(3) \|
	581	S3C2412_SLPCON_EINT(4) \|
	582	S3C2412_SLPCON_EINT(5) \|
	583	S3C2412_SLPCON_EINT(6) \|
	584	S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
	585
	586	/* Port G sleep */
	587
	588	__raw_writel(S3C2412_SLPCON_IN(0) \|
	589	S3C2412_SLPCON_IN(1) \|
	590	S3C2412_SLPCON_IN(2) \|
	591	S3C2412_SLPCON_IN(3) \|
	592	S3C2412_SLPCON_IN(4) \|
	593	S3C2412_SLPCON_IN(5) \|
	594	S3C2412_SLPCON_IN(6) \|
	595	S3C2412_SLPCON_IN(7) \|
	596	S3C2412_SLPCON_PULL(8) \|
597	S3C2412_SLPCON_PULL(9) \|
598	S3C2412_SLPCON_IN(10) \|
599	S3C2412_SLPCON_PULL(11) \|
600	S3C2412_SLPCON_PULL(12) \|
601	S3C2412_SLPCON_PULL(13) \|
602	S3C2412_SLPCON_IN(14) \|
603	S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
604
605	/* Port H sleep */
606
607	__raw_writel(S3C2412_SLPCON_PULL(0) \|
608	S3C2412_SLPCON_PULL(1) \|
609	S3C2412_SLPCON_PULL(2) \|
610	S3C2412_SLPCON_PULL(3) \|
611	S3C2412_SLPCON_PULL(4) \|
612	S3C2412_SLPCON_PULL(5) \|
613	S3C2412_SLPCON_PULL(6) \|
614	S3C2412_SLPCON_IN(7) \|
615	S3C2412_SLPCON_IN(8) \|
616	S3C2412_SLPCON_PULL(9) \|
617	S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
618
619	/* initialise the power management now we've setup everything. */
620
4e59c25d	621	s3c_pm_init();
9db829f4	622
2a3a1804 BD	623	/** TODO - check that this is after the cmdline option! */
2a3a1804 BD	624	s3c_nand_set_platdata(&jive_nand_info);
9db829f4	625
a2ed4065 BD	626	/* initialise the spi */
a2ed4065 BD	627
afc84ad1 BD	628	gpio_request(S3C2410_GPG(13), "lcm reset");
afc84ad1 BD	629	gpio_direction_output(S3C2410_GPG(13), 0);
a2ed4065	630
afc84ad1 BD	631	gpio_request(S3C2410_GPB(7), "jive spi");
afc84ad1 BD	632	gpio_direction_output(S3C2410_GPB(7), 1);
a2ed4065	633
42aa322c SN	634	gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
42aa322c SN	635	gpio_free(S3C2410_GPB(6));
a2ed4065	636
42aa322c SN	637	gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
42aa322c SN	638	gpio_free(S3C2410_GPG(8));
a2ed4065	639
fd2de272 BD	640	/* initialise the WM8750 spi */
fd2de272 BD	641
afc84ad1 BD	642	gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
afc84ad1 BD	643	gpio_direction_output(S3C2410_GPH(10), 1);
fd2de272	644
9db829f4 BD	645	/* Turn off suspend on both USB ports, and switch the
	646	* selectable USB port to USB device mode. */
	647
	648	s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST \|
	649	S3C2410_MISCCR_USBSUSPND0 \|
	650	S3C2410_MISCCR_USBSUSPND1, 0x0);
	651
	652	s3c24xx_udc_set_platdata(&jive_udc_cfg);
0f99263c	653	s3c24xx_fb_set_platdata(&jive_lcd_config);
9db829f4	654
a2ed4065 BD	655	spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
a2ed4065 BD	656
3e1b776c	657	s3c_i2c0_set_platdata(&jive_i2c_cfg);
d10d8a5f BD	658	i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
d10d8a5f BD	659
dd1086f4 BD	660	pm_power_off = jive_power_off;
dd1086f4 BD	661
9db829f4 BD	662	platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
	663	}
	664
	665	MACHINE_START(JIVE, "JIVE")
afdd225d	666	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
69d50710	667	.atag_offset = 0x100,
9db829f4	668
0da09930	669	.init_irq = s3c2412_init_irq,
9db829f4 BD	670	.map_io = jive_map_io,
9db829f4 BD	671	.init_machine = jive_machine_init,
3c27f314	672	.init_time = jive_init_time,
9db829f4	673	MACHINE_END