[linux-2.6-block.git] / arch / arm / mach-s3c24xx / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>

#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <mach/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/gpio-cfg.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>

#include "simtec.h"
#include "common.h"

#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	}
};

/* NAND Flash on BAST board */

#ifdef CONFIG_PM
static int bast_pm_suspend(void)
{
	/* ensure that an nRESET is not generated on resume. */
	gpio_direction_output(S3C2410_GPA(21), 1);
	return 0;
}

static void bast_pm_resume(void)
{
	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
}

#else
#define bast_pm_suspend NULL
#define bast_pm_resume NULL
#endif

static struct syscore_ops bast_pm_syscore_ops = {
	.suspend	= bast_pm_suspend,
	.resume		= bast_pm_resume,
};

static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition __initdata bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.options        = NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.options        = NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.options        = NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand __initdata bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
	[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
	[2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
					| IORESOURCE_IRQ_HIGHLEVEL),
};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.frequency	= 100*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
	[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
	[2] = DEFINE_RES_IRQ(IRQ_ASIX),
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
					0x30 * 0x20),
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 1,
};

/* I2C devices fitted. */

static struct i2c_board_info bast_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tlv320aic23", 0x1a),
	}, {
		I2C_BOARD_INFO("simtec-pmu", 0x6b),
	}, {
		I2C_BOARD_INFO("ch7013", 0x75),
	},
};

static struct s3c_hwmon_pdata bast_hwmon_info = {
	/* LCD contrast (0-6.6V) */
	.in[0] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-contrast",
		.mult		= 3300,
		.div		= 512,
	},
	/* LED current feedback */
	.in[1] = &(struct s3c_hwmon_chcfg) {
		.name		= "led-feedback",
		.mult		= 3300,
		.div		= 1024,
	},
	/* LCD feedback (0-6.6V) */
	.in[2] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-feedback",
		.mult		= 3300,
		.div		= 512,
	},
	/* Vcore (1.8-2.0V), Vref 3.3V  */
	.in[3] = &(struct s3c_hwmon_chcfg) {
		.name		= "vcore",
		.mult		= 3300,
		.div		= 1024,
	},
};

/* Standard BAST devices */
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&s3c_device_adc,
	&s3c_device_hwmon,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	.refresh	= 7800, /* 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_hwmon_set_platdata(&bast_hwmon_info);

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
}

static void __init bast_init(void)
{
	register_syscore_ops(&bast_pm_syscore_ops);

	s3c_i2c0_set_platdata(&bast_i2c_info);
	s3c_nand_set_platdata(&bast_nand_info);
	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));

	i2c_register_board_info(0, bast_i2c_devs,
				ARRAY_SIZE(bast_i2c_devs));

	usb_simtec_init();
	nor_simtec_init();
	simtec_audio_add(NULL, true, &bast_audio);

	WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
	
	s3c_cpufreq_setboard(&bast_cpufreq);
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.atag_offset	= 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.init_time	= s3c24xx_timer_init,
	.restart	= s3c2410_restart,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
1da177e4 LT	2	*
ccae941e	3	* Copyright 2003-2008 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
ec976d6e	19	#include <linux/gpio.h>
bb072c3c	20	#include <linux/syscore_ops.h>
b6d1f542	21	#include <linux/serial_core.h>
d052d1be	22	#include <linux/platform_device.h>
d97a666f	23	#include <linux/dm9000.h>
b7a12d19	24	#include <linux/ata_platform.h>
042cf0f2	25	#include <linux/i2c.h>
fced80c7	26	#include <linux/io.h>
1da177e4	27
5ce4b1fe BD	28	#include <net/ax88796.h>
5ce4b1fe BD	29
1da177e4 LT	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/map.h>
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/bast-map.h>
	35	#include <mach/bast-irq.h>
	36	#include <mach/bast-cpld.h>
1da177e4	37
a09e64fb	38	#include <mach/hardware.h>
1da177e4 LT	39	#include <asm/irq.h>
	40	#include <asm/mach-types.h>
	41
	42	//#include <asm/debug-ll.h>
a2b7ba9c	43	#include <plat/regs-serial.h>
a09e64fb RK	44	#include <mach/regs-gpio.h>
	45	#include <mach/regs-mem.h>
	46	#include <mach/regs-lcd.h>
58c8d570	47
436d42c6 AB	48	#include <linux/platform_data/hwmon-s3c.h>
	49	#include <linux/platform_data/mtd-nand-s3c2410.h>
	50	#include <linux/platform_data/i2c-s3c2410.h>
a09e64fb	51	#include <mach/fb.h>
1da177e4 LT	52
	53	#include <linux/mtd/mtd.h>
	54	#include <linux/mtd/nand.h>
	55	#include <linux/mtd/nand_ecc.h>
	56	#include <linux/mtd/partitions.h>
	57
65cc3370 BD	58	#include <linux/serial_8250.h>
65cc3370 BD	59
d5120ae7	60	#include <plat/clock.h>
a2b7ba9c BD	61	#include <plat/devs.h>
a2b7ba9c BD	62	#include <plat/cpu.h>
ca0b4901	63	#include <plat/cpu-freq.h>
40b956f0	64	#include <plat/gpio-cfg.h>
436d42c6	65	#include <linux/platform_data/asoc-s3c24xx_simtec.h>
9d529c6e	66
ec2cc753	67	#include "simtec.h"
b27b0727	68	#include "common.h"
1da177e4	69
ccae941e	70	#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
1da177e4 LT	71
	72	/* macros for virtual address mods for the io space entries */
	73	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	74	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	75	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	76	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	77
	78	/* macros to modify the physical addresses for io space */
	79
1d23b65d BD	80	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	81	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	82	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	83	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	84
	85	static struct map_desc bast_iodesc[] __initdata = {
	86	/* ISA IO areas */
1d23b65d BD	87	{
	88	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	89	.pfn = PA_CS2(BAST_PA_ISAIO),
	90	.length = SZ_16M,
	91	.type = MT_DEVICE,
	92	}, {
	93	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	94	.pfn = PA_CS3(BAST_PA_ISAIO),
	95	.length = SZ_16M,
	96	.type = MT_DEVICE,
	97	},
1da177e4	98	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	99	{
	100	.virtual = (u32)BAST_VA_CTRL1,
	101	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	102	.length = SZ_1M,
	103	.type = MT_DEVICE,
	104	}, {
	105	.virtual = (u32)BAST_VA_CTRL2,
	106	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	107	.length = SZ_1M,
	108	.type = MT_DEVICE,
	109	}, {
	110	.virtual = (u32)BAST_VA_CTRL3,
	111	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	112	.length = SZ_1M,
	113	.type = MT_DEVICE,
	114	}, {
	115	.virtual = (u32)BAST_VA_CTRL4,
	116	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	117	.length = SZ_1M,
	118	.type = MT_DEVICE,
	119	},
1da177e4	120	/* PC104 IRQ mux */
1d23b65d BD	121	{
	122	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	123	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	124	.length = SZ_1M,
	125	.type = MT_DEVICE,
	126	}, {
	127	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	128	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	129	.length = SZ_1M,
	130	.type = MT_DEVICE,
	131	}, {
	132	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	133	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	134	.length = SZ_1M,
	135	.type = MT_DEVICE,
	136	},
1da177e4 LT	137
	138	/* peripheral space... one for each of fast/slow/byte/16bit */
	139	/* note, ide is only decoded in word space, even though some registers
	140	* are only 8bit */
	141
	142	/* slow, byte */
	143	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	144	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	145	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	146
	147	/* slow, word */
	148	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	149	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	150	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	151
	152	/* fast, byte */
	153	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	154	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	155	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	156
	157	/* fast, word */
	158	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	159	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	160	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	161	};
	162
	163	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	164	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	165	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	166
66a9b49a	167	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	168	[0] = {
	169	.hwport = 0,
	170	.flags = 0,
	171	.ucon = UCON,
	172	.ulcon = ULCON,
	173	.ufcon = UFCON,
1da177e4 LT	174	},
	175	[1] = {
	176	.hwport = 1,
	177	.flags = 0,
	178	.ucon = UCON,
	179	.ulcon = ULCON,
	180	.ufcon = UFCON,
1da177e4 LT	181	},
	182	/* port 2 is not actually used */
	183	[2] = {
	184	.hwport = 2,
	185	.flags = 0,
	186	.ucon = UCON,
	187	.ulcon = ULCON,
	188	.ufcon = UFCON,
1da177e4 LT	189	}
	190	};
	191
1da177e4 LT	192	/* NAND Flash on BAST board */
1da177e4 LT	193
6ddc4b07	194	#ifdef CONFIG_PM
bb072c3c	195	static int bast_pm_suspend(void)
6ddc4b07 BD	196	{
6ddc4b07 BD	197	/* ensure that an nRESET is not generated on resume. */
408c8b8c	198	gpio_direction_output(S3C2410_GPA(21), 1);
6ddc4b07 BD	199	return 0;
	200	}
	201
bb072c3c	202	static void bast_pm_resume(void)
6ddc4b07	203	{
40b956f0	204	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
6ddc4b07 BD	205	}
	206
	207	#else
	208	#define bast_pm_suspend NULL
	209	#define bast_pm_resume NULL
	210	#endif
	211
bb072c3c	212	static struct syscore_ops bast_pm_syscore_ops = {
6ddc4b07 BD	213	.suspend = bast_pm_suspend,
	214	.resume = bast_pm_resume,
	215	};
	216
1da177e4 LT	217	static int smartmedia_map[] = { 0 };
	218	static int chip0_map[] = { 1 };
	219	static int chip1_map[] = { 2 };
	220	static int chip2_map[] = { 3 };
	221
2a3a1804	222	static struct mtd_partition __initdata bast_default_nand_part[] = {
1da177e4 LT	223	[0] = {
	224	.name = "Boot Agent",
	225	.size = SZ_16K,
b526bf23	226	.offset = 0,
1da177e4 LT	227	},
	228	[1] = {
	229	.name = "/boot",
	230	.size = SZ_4M - SZ_16K,
	231	.offset = SZ_16K,
	232	},
	233	[2] = {
	234	.name = "user",
	235	.offset = SZ_4M,
	236	.size = MTDPART_SIZ_FULL,
	237	}
	238	};
	239
	240	/* the bast has 4 selectable slots for nand-flash, the three
	241	* on-board chip areas, as well as the external SmartMedia
	242	* slot.
	243	*
	244	* Note, there is no current hot-plug support for the SmartMedia
	245	* socket.
	246	*/
	247
2a3a1804	248	static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
1da177e4 LT	249	[0] = {
	250	.name = "SmartMedia",
	251	.nr_chips = 1,
	252	.nr_map = smartmedia_map,
d3ef7ee4	253	.options = NAND_SCAN_SILENT_NODEV,
1da177e4	254	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	255	.partitions = bast_default_nand_part,
1da177e4 LT	256	},
	257	[1] = {
	258	.name = "chip0",
	259	.nr_chips = 1,
	260	.nr_map = chip0_map,
	261	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	262	.partitions = bast_default_nand_part,
1da177e4 LT	263	},
	264	[2] = {
	265	.name = "chip1",
	266	.nr_chips = 1,
	267	.nr_map = chip1_map,
d3ef7ee4	268	.options = NAND_SCAN_SILENT_NODEV,
1da177e4	269	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	270	.partitions = bast_default_nand_part,
1da177e4 LT	271	},
	272	[3] = {
	273	.name = "chip2",
	274	.nr_chips = 1,
	275	.nr_map = chip2_map,
d3ef7ee4	276	.options = NAND_SCAN_SILENT_NODEV,
1da177e4	277	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	278	.partitions = bast_default_nand_part,
1da177e4 LT	279	}
	280	};
	281
	282	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	283	{
	284	unsigned int tmp;
	285
	286	slot = set->nr_map[slot] & 3;
	287
	288	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	289	slot, set, set->nr_map);
	290
	291	tmp = __raw_readb(BAST_VA_CTRL2);
	292	tmp &= BAST_CPLD_CTLR2_IDERST;
	293	tmp \|= slot;
	294	tmp \|= BAST_CPLD_CTRL2_WNAND;
	295
	296	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	297
	298	__raw_writeb(tmp, BAST_VA_CTRL2);
	299	}
	300
2a3a1804	301	static struct s3c2410_platform_nand __initdata bast_nand_info = {
b048dbf4 BD	302	.tacls = 30,
	303	.twrph0 = 60,
	304	.twrph1 = 60,
1da177e4 LT	305	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	306	.sets = bast_nand_sets,
	307	.select_chip = bast_nand_select,
	308	};
	309
d97a666f BD	310	/* DM9000 */
	311
	312	static struct resource bast_dm9k_resource[] = {
52df44d1 TB	313	[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
	314	[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
	315	[2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
	316	\| IORESOURCE_IRQ_HIGHLEVEL),
d97a666f BD	317	};
	318
	319	/* for the moment we limit ourselves to 16bit IO until some
	320	* better IO routines can be written and tested
	321	*/
	322
9f693d7b	323	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	324	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	325	};
	326
	327	static struct platform_device bast_device_dm9k = {
	328	.name = "dm9000",
	329	.id = 0,
	330	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	331	.resource = bast_dm9k_resource,
	332	.dev = {
	333	.platform_data = &bast_dm9k_platdata,
	334	}
	335	};
	336
65cc3370 BD	337	/* serial devices */
	338
	339	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	340	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	341	#define SERIAL_CLK (1843200)
	342
	343	static struct plat_serial8250_port bast_sio_data[] = {
	344	[0] = {
	345	.mapbase = SERIAL_BASE + 0x2f8,
	346	.irq = IRQ_PCSERIAL1,
	347	.flags = SERIAL_FLAGS,
	348	.iotype = UPIO_MEM,
	349	.regshift = 0,
	350	.uartclk = SERIAL_CLK,
	351	},
	352	[1] = {
	353	.mapbase = SERIAL_BASE + 0x3f8,
	354	.irq = IRQ_PCSERIAL2,
	355	.flags = SERIAL_FLAGS,
	356	.iotype = UPIO_MEM,
	357	.regshift = 0,
	358	.uartclk = SERIAL_CLK,
	359	},
	360	{ }
	361	};
	362
	363	static struct platform_device bast_sio = {
	364	.name = "serial8250",
6df29deb	365	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	366	.dev = {
	367	.platform_data = &bast_sio_data,
	368	},
	369	};
1da177e4	370
1fcf8448 BD	371	/* we have devices on the bus which cannot work much over the
	372	* standard 100KHz i2c bus frequency
	373	*/
	374
3e1b776c	375	static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
1fcf8448 BD	376	.flags = 0,
1fcf8448 BD	377	.slave_addr = 0x10,
c564e6ae	378	.frequency = 100*1000,
1fcf8448 BD	379	};
1fcf8448 BD	380
5ce4b1fe BD	381	/* Asix AX88796 10/100 ethernet controller */
	382
	383	static struct ax_plat_data bast_asix_platdata = {
	384	.flags = AXFLG_MAC_FROMDEV,
	385	.wordlength = 2,
	386	.dcr_val = 0x48,
	387	.rcr_val = 0x40,
	388	};
	389
	390	static struct resource bast_asix_resource[] = {
52df44d1 TB	391	[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
	392	[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
	393	[2] = DEFINE_RES_IRQ(IRQ_ASIX),
5ce4b1fe BD	394	};
	395
	396	static struct platform_device bast_device_asix = {
	397	.name = "ax88796",
	398	.id = 0,
	399	.num_resources = ARRAY_SIZE(bast_asix_resource),
	400	.resource = bast_asix_resource,
	401	.dev = {
	402	.platform_data = &bast_asix_platdata
	403	}
	404	};
	405
	406	/* Asix AX88796 10/100 ethernet controller parallel port */
	407
	408	static struct resource bast_asixpp_resource[] = {
52df44d1 TB	409	[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
52df44d1 TB	410	0x30 * 0x20),
5ce4b1fe BD	411	};
	412
	413	static struct platform_device bast_device_axpp = {
	414	.name = "ax88796-pp",
	415	.id = 0,
	416	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	417	.resource = bast_asixpp_resource,
	418	};
	419
	420	/* LCD/VGA controller */
58c8d570	421
09fe75f6 KH	422	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	423	{
1f411537	424	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	425	.width = 640,
09fe75f6 KH	426	.height = 480,
5f20f69b	427
69816699	428	.pixclock = 33333,
09fe75f6 KH	429	.xres = 640,
	430	.yres = 480,
	431	.bpp = 4,
1f411537 KH	432	.left_margin = 40,
1f411537 KH	433	.right_margin = 20,
93d11f5a	434	.hsync_len = 88,
5f20f69b KH	435	.upper_margin = 30,
5f20f69b KH	436	.lower_margin = 32,
93d11f5a	437	.vsync_len = 3,
09fe75f6	438
f28ef573	439	.lcdcon5 = 0x00014b02,
58c8d570	440	},
09fe75f6	441	{
1f411537	442	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	443	.width = 640,
	444	.height = 480,
	445
69816699	446	.pixclock = 33333,
09fe75f6 KH	447	.xres = 640,
	448	.yres = 480,
	449	.bpp = 8,
1f411537 KH	450	.left_margin = 40,
1f411537 KH	451	.right_margin = 20,
93d11f5a	452	.hsync_len = 88,
5f20f69b KH	453	.upper_margin = 30,
5f20f69b KH	454	.lower_margin = 32,
93d11f5a	455	.vsync_len = 3,
09fe75f6	456
f28ef573	457	.lcdcon5 = 0x00014b02,
09fe75f6 KH	458	},
09fe75f6 KH	459	{
1f411537	460	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	461	.width = 640,
	462	.height = 480,
	463
69816699	464	.pixclock = 33333,
09fe75f6 KH	465	.xres = 640,
	466	.yres = 480,
	467	.bpp = 16,
1f411537 KH	468	.left_margin = 40,
1f411537 KH	469	.right_margin = 20,
93d11f5a	470	.hsync_len = 88,
5f20f69b KH	471	.upper_margin = 30,
5f20f69b KH	472	.lower_margin = 32,
93d11f5a	473	.vsync_len = 3,
09fe75f6	474
f28ef573	475	.lcdcon5 = 0x00014b02,
09fe75f6 KH	476	},
09fe75f6 KH	477	};
58c8d570	478
09fe75f6 KH	479	/* LCD/VGA controller */
	480
	481	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	482
	483	.displays = bast_lcd_info,
	484	.num_displays = ARRAY_SIZE(bast_lcd_info),
9cbae12c	485	.default_display = 1,
58c8d570 BD	486	};
58c8d570 BD	487
042cf0f2 BD	488	/* I2C devices fitted. */
	489
	490	static struct i2c_board_info bast_i2c_devs[] __initdata = {
	491	{
	492	I2C_BOARD_INFO("tlv320aic23", 0x1a),
	493	}, {
	494	I2C_BOARD_INFO("simtec-pmu", 0x6b),
	495	}, {
	496	I2C_BOARD_INFO("ch7013", 0x75),
	497	},
	498	};
b7a12d19	499
885f9ebe BD	500	static struct s3c_hwmon_pdata bast_hwmon_info = {
	501	/* LCD contrast (0-6.6V) */
	502	.in[0] = &(struct s3c_hwmon_chcfg) {
	503	.name = "lcd-contrast",
	504	.mult = 3300,
	505	.div = 512,
	506	},
	507	/* LED current feedback */
	508	.in[1] = &(struct s3c_hwmon_chcfg) {
	509	.name = "led-feedback",
	510	.mult = 3300,
	511	.div = 1024,
	512	},
	513	/* LCD feedback (0-6.6V) */
	514	.in[2] = &(struct s3c_hwmon_chcfg) {
	515	.name = "lcd-feedback",
	516	.mult = 3300,
	517	.div = 512,
	518	},
	519	/* Vcore (1.8-2.0V), Vref 3.3V */
	520	.in[3] = &(struct s3c_hwmon_chcfg) {
	521	.name = "vcore",
	522	.mult = 3300,
	523	.div = 1024,
	524	},
	525	};
	526
1da177e4	527	/* Standard BAST devices */
885f9ebe	528	// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
1da177e4 LT	529
1da177e4 LT	530	static struct platform_device *bast_devices[] __initdata = {
b813248c	531	&s3c_device_ohci,
1da177e4 LT	532	&s3c_device_lcd,
1da177e4 LT	533	&s3c_device_wdt,
3e1b776c	534	&s3c_device_i2c0,
1da177e4 LT	535	&s3c_device_rtc,
1da177e4 LT	536	&s3c_device_nand,
885f9ebe BD	537	&s3c_device_adc,
885f9ebe BD	538	&s3c_device_hwmon,
d97a666f	539	&bast_device_dm9k,
5ce4b1fe BD	540	&bast_device_asix,
5ce4b1fe BD	541	&bast_device_axpp,
65cc3370	542	&bast_sio,
1da177e4 LT	543	};
1da177e4 LT	544
2bc7509f	545	static struct clk *bast_clocks[] __initdata = {
1da177e4 LT	546	&s3c24xx_dclk0,
	547	&s3c24xx_dclk1,
	548	&s3c24xx_clkout0,
	549	&s3c24xx_clkout1,
	550	&s3c24xx_uclk,
	551	};
	552
ca0b4901 BD	553	static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	554	.refresh = 7800, /* 7.8usec */
	555	.auto_io = 1,
	556	.need_io = 1,
	557	};
	558
4d3a3469 BD	559	static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
	560	.have_mic = 1,
	561	.have_lout = 1,
	562	};
	563
5fe10ab1	564	static void __init bast_map_io(void)
1da177e4 LT	565	{
	566	/* initialise the clocks */
	567
d96a9804	568	s3c24xx_dclk0.parent = &clk_upll;
1da177e4 LT	569	s3c24xx_dclk0.rate = 1210001000;
1da177e4 LT	570
d96a9804	571	s3c24xx_dclk1.parent = &clk_upll;
1da177e4 LT	572	s3c24xx_dclk1.rate = 2410001000;
	573
	574	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	575	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	576
	577	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	578
ce89c206 BD	579	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	580
6cd82ffe	581	s3c_hwmon_set_platdata(&bast_hwmon_info);
3e1b776c	582
1da177e4 LT	583	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	584	s3c24xx_init_clocks(0);
	585	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
1da177e4 LT	586	}
1da177e4 LT	587
58c8d570 BD	588	static void __init bast_init(void)
58c8d570 BD	589	{
bb072c3c	590	register_syscore_ops(&bast_pm_syscore_ops);
6ddc4b07	591
a8af6de0	592	s3c_i2c0_set_platdata(&bast_i2c_info);
2a3a1804	593	s3c_nand_set_platdata(&bast_nand_info);
09fe75f6	594	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	595	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
9d529c6e	596
042cf0f2 BD	597	i2c_register_board_info(0, bast_i2c_devs,
	598	ARRAY_SIZE(bast_i2c_devs));
	599
7a05a2cb	600	usb_simtec_init();
9d529c6e	601	nor_simtec_init();
4d3a3469	602	simtec_audio_add(NULL, true, &bast_audio);
ca0b4901	603
408c8b8c BD	604	WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
408c8b8c BD	605
ca0b4901	606	s3c_cpufreq_setboard(&bast_cpufreq);
58c8d570	607	}
1da177e4 LT	608
1da177e4 LT	609	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	610	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
69d50710	611	.atag_offset = 0x100,
f705b1ae BD	612	.map_io = bast_map_io,
f705b1ae BD	613	.init_irq = s3c24xx_init_irq,
58c8d570	614	.init_machine = bast_init,
6bb27d73	615	.init_time = s3c24xx_timer_init,
b27b0727	616	.restart = s3c2410_restart,
1da177e4	617	MACHINE_END