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ARM: S3C24XX: fix irq parent check
[linux-2.6-block.git] / arch / arm / mach-s3c24xx / irq.c
CommitLineData
1f629b7a
HS		 1/*
2 * S3C24XX IRQ handling
a21765a7 3 *
e02f8664 4 * Copyright (c) 2003-2004 Simtec Electronics
a21765a7 5 * Ben Dooks <ben@simtec.co.uk>
1f629b7a 6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
a21765a7
BD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
a21765a7
BD		 17*/
18
19#include <linux/init.h>
1f629b7a 20#include <linux/slab.h>
a21765a7 21#include <linux/module.h>
1f629b7a
HS		 22#include <linux/io.h>
23#include <linux/err.h>
a21765a7
BD		 24#include <linux/interrupt.h>
25#include <linux/ioport.h>
edbaa603 26#include <linux/device.h>
1f629b7a 27#include <linux/irqdomain.h>
a21765a7 28
a21765a7
BD		 29#include <asm/mach/irq.h>
30
1f629b7a
HS		 31#include <mach/regs-irq.h>
32#include <mach/regs-gpio.h>
a21765a7 33
a2b7ba9c 34#include <plat/cpu.h>
1f629b7a 35#include <plat/regs-irqtype.h>
a2b7ba9c 36#include <plat/pm.h>
a21765a7 37
1f629b7a
HS		 38#define S3C_IRQTYPE_NONE 0
39#define S3C_IRQTYPE_EINT 1
40#define S3C_IRQTYPE_EDGE 2
41#define S3C_IRQTYPE_LEVEL 3
a21765a7 42
1f629b7a
HS		 43struct s3c_irq_data {
44 unsigned int type;
45 unsigned long parent_irq;
a21765a7 46
1f629b7a
HS		 47 /* data gets filled during init */
48 struct s3c_irq_intc *intc;
49 unsigned long sub_bits;
50 struct s3c_irq_intc *sub_intc;
a21765a7
BD		 51};
52
1f629b7a
HS		 53/*
54 * Sructure holding the controller data
55 * @reg_pending register holding pending irqs
56 * @reg_intpnd special register intpnd in main intc
57 * @reg_mask mask register
58 * @domain irq_domain of the controller
59 * @parent parent controller for ext and sub irqs
60 * @irqs irq-data, always s3c_irq_data[32]
61 */
62struct s3c_irq_intc {
63 void __iomem *reg_pending;
64 void __iomem *reg_intpnd;
65 void __iomem *reg_mask;
66 struct irq_domain *domain;
67 struct s3c_irq_intc *parent;
68 struct s3c_irq_data *irqs;
a21765a7
BD		 69};
70
1f629b7a 71static void s3c_irq_mask(struct irq_data *data)
a21765a7 72{
1f629b7a
HS		 73 struct s3c_irq_intc *intc = data->domain->host_data;
74 struct s3c_irq_intc *parent_intc = intc->parent;
75 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
76 struct s3c_irq_data *parent_data;
a21765a7 77 unsigned long mask;
1f629b7a
HS		 78 unsigned int irqno;
79
80 mask = __raw_readl(intc->reg_mask);
81 mask |= (1UL << data->hwirq);
82 __raw_writel(mask, intc->reg_mask);
83
0fe3cb1e 84 if (parent_intc) {
1f629b7a 85 parent_data = &parent_intc->irqs[irq_data->parent_irq];
a21765a7 86
1f629b7a
HS		 87 /* check to see if we need to mask the parent IRQ */
88 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
89 irqno = irq_find_mapping(parent_intc->domain,
90 irq_data->parent_irq);
91 s3c_irq_mask(irq_get_irq_data(irqno));
92 }
93 }
a21765a7
BD		 94}
95
1f629b7a 96static void s3c_irq_unmask(struct irq_data *data)
a21765a7 97{
1f629b7a
HS		 98 struct s3c_irq_intc *intc = data->domain->host_data;
99 struct s3c_irq_intc *parent_intc = intc->parent;
100 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
a21765a7 101 unsigned long mask;
1f629b7a 102 unsigned int irqno;
a21765a7 103
1f629b7a
HS		 104 mask = __raw_readl(intc->reg_mask);
105 mask &= ~(1UL << data->hwirq);
106 __raw_writel(mask, intc->reg_mask);
a21765a7 107
0fe3cb1e 108 if (parent_intc) {
1f629b7a
HS		 109 irqno = irq_find_mapping(parent_intc->domain,
110 irq_data->parent_irq);
111 s3c_irq_unmask(irq_get_irq_data(irqno));
a21765a7
BD		 112 }
113}
114
1f629b7a 115static inline void s3c_irq_ack(struct irq_data *data)
a21765a7 116{
1f629b7a
HS		 117 struct s3c_irq_intc *intc = data->domain->host_data;
118 unsigned long bitval = 1UL << data->hwirq;
a21765a7 119
1f629b7a
HS		 120 __raw_writel(bitval, intc->reg_pending);
121 if (intc->reg_intpnd)
122 __raw_writel(bitval, intc->reg_intpnd);
a21765a7
BD		 123}
124
1f629b7a
HS		 125static int s3c_irqext_type_set(void __iomem *gpcon_reg,
126 void __iomem *extint_reg,
127 unsigned long gpcon_offset,
128 unsigned long extint_offset,
129 unsigned int type)
a21765a7 130{
a21765a7
BD		 131 unsigned long newvalue = 0, value;
132
a21765a7
BD		 133 /* Set the GPIO to external interrupt mode */
134 value = __raw_readl(gpcon_reg);
135 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
136 __raw_writel(value, gpcon_reg);
137
138 /* Set the external interrupt to pointed trigger type */
139 switch (type)
140 {
6cab4860 141 case IRQ_TYPE_NONE:
1f629b7a 142 pr_warn("No edge setting!\n");
a21765a7
BD		 143 break;
144
6cab4860 145 case IRQ_TYPE_EDGE_RISING:
a21765a7
BD		 146 newvalue = S3C2410_EXTINT_RISEEDGE;
147 break;
148
6cab4860 149 case IRQ_TYPE_EDGE_FALLING:
a21765a7
BD		 150 newvalue = S3C2410_EXTINT_FALLEDGE;
151 break;
152
6cab4860 153 case IRQ_TYPE_EDGE_BOTH:
a21765a7
BD		 154 newvalue = S3C2410_EXTINT_BOTHEDGE;
155 break;
156
6cab4860 157 case IRQ_TYPE_LEVEL_LOW:
a21765a7
BD		 158 newvalue = S3C2410_EXTINT_LOWLEV;
159 break;
160
6cab4860 161 case IRQ_TYPE_LEVEL_HIGH:
a21765a7
BD		 162 newvalue = S3C2410_EXTINT_HILEV;
163 break;
164
165 default:
1f629b7a
HS		 166 pr_err("No such irq type %d", type);
167 return -EINVAL;
a21765a7
BD		 168 }
169
170 value = __raw_readl(extint_reg);
171 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
172 __raw_writel(value, extint_reg);
173
174 return 0;
175}
176
dc1a3538 177static int s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 178{
1f629b7a
HS		 179 void __iomem *extint_reg;
180 void __iomem *gpcon_reg;
181 unsigned long gpcon_offset, extint_offset;
a21765a7 182
1f629b7a
HS		 183 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
184 gpcon_reg = S3C2410_GPFCON;
185 extint_reg = S3C24XX_EXTINT0;
186 gpcon_offset = (data->hwirq) * 2;
187 extint_offset = (data->hwirq) * 4;
188 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
189 gpcon_reg = S3C2410_GPGCON;
190 extint_reg = S3C24XX_EXTINT1;
191 gpcon_offset = (data->hwirq - 8) * 2;
192 extint_offset = (data->hwirq - 8) * 4;
193 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
194 gpcon_reg = S3C2410_GPGCON;
195 extint_reg = S3C24XX_EXTINT2;
196 gpcon_offset = (data->hwirq - 8) * 2;
197 extint_offset = (data->hwirq - 16) * 4;
198 } else {
199 return -EINVAL;
200 }
a21765a7 201
1f629b7a
HS		 202 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
203 extint_offset, type);
a21765a7
BD		 204}
205
1f629b7a 206static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
a21765a7 207{
1f629b7a
HS		 208 void __iomem *extint_reg;
209 void __iomem *gpcon_reg;
210 unsigned long gpcon_offset, extint_offset;
a21765a7 211
1f629b7a
HS		 212 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
213 gpcon_reg = S3C2410_GPFCON;
214 extint_reg = S3C24XX_EXTINT0;
215 gpcon_offset = (data->hwirq) * 2;
216 extint_offset = (data->hwirq) * 4;
217 } else {
218 return -EINVAL;
219 }
a21765a7 220
1f629b7a
HS		 221 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
222 extint_offset, type);
a21765a7
BD		 223}
224
dc1a3538 225static struct irq_chip s3c_irq_chip = {
1f629b7a
HS		 226 .name = "s3c",
227 .irq_ack = s3c_irq_ack,
228 .irq_mask = s3c_irq_mask,
229 .irq_unmask = s3c_irq_unmask,
230 .irq_set_wake = s3c_irq_wake
a21765a7
BD		 231};
232
dc1a3538 233static struct irq_chip s3c_irq_level_chip = {
1f629b7a
HS		 234 .name = "s3c-level",
235 .irq_mask = s3c_irq_mask,
236 .irq_unmask = s3c_irq_unmask,
237 .irq_ack = s3c_irq_ack,
a21765a7
BD		 238};
239
1f629b7a
HS		 240static struct irq_chip s3c_irqext_chip = {
241 .name = "s3c-ext",
242 .irq_mask = s3c_irq_mask,
243 .irq_unmask = s3c_irq_unmask,
244 .irq_ack = s3c_irq_ack,
245 .irq_set_type = s3c_irqext_type,
246 .irq_set_wake = s3c_irqext_wake
a21765a7
BD		 247};
248
1f629b7a
HS		 249static struct irq_chip s3c_irq_eint0t4 = {
250 .name = "s3c-ext0",
251 .irq_ack = s3c_irq_ack,
252 .irq_mask = s3c_irq_mask,
253 .irq_unmask = s3c_irq_unmask,
254 .irq_set_wake = s3c_irq_wake,
255 .irq_set_type = s3c_irqext0_type,
256};
a21765a7 257
1f629b7a 258static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
a21765a7 259{
1f629b7a
HS		 260 struct irq_chip *chip = irq_desc_get_chip(desc);
261 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
262 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
263 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
264 unsigned long src;
265 unsigned long msk;
266 unsigned int n;
267
268 chained_irq_enter(chip, desc);
269
270 src = __raw_readl(sub_intc->reg_pending);
271 msk = __raw_readl(sub_intc->reg_mask);
272
273 src &= ~msk;
274 src &= irq_data->sub_bits;
275
276 while (src) {
277 n = __ffs(src);
278 src &= ~(1 << n);
279 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
a21765a7
BD		 280 }
281
1f629b7a 282 chained_irq_exit(chip, desc);
a21765a7
BD		 283}
284
229fd8ff
BD		 285#ifdef CONFIG_FIQ
286/**
287 * s3c24xx_set_fiq - set the FIQ routing
288 * @irq: IRQ number to route to FIQ on processor.
289 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
290 *
291 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
292 * @on is true, the @irq is checked to see if it can be routed and the
293 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
294 * routing is cleared, regardless of which @irq is specified.
295 */
296int s3c24xx_set_fiq(unsigned int irq, bool on)
297{
298 u32 intmod;
299 unsigned offs;
300
301 if (on) {
302 offs = irq - FIQ_START;
303 if (offs > 31)
304 return -EINVAL;
305
306 intmod = 1 << offs;
307 } else {
308 intmod = 0;
309 }
310
311 __raw_writel(intmod, S3C2410_INTMOD);
312 return 0;
313}
0f13c824
BD		 314
315EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff
BD		 316#endif
317
1f629b7a
HS		 318static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
319 irq_hw_number_t hw)
a21765a7 320{
1f629b7a
HS		 321 struct s3c_irq_intc *intc = h->host_data;
322 struct s3c_irq_data *irq_data = &intc->irqs[hw];
323 struct s3c_irq_intc *parent_intc;
324 struct s3c_irq_data *parent_irq_data;
325 unsigned int irqno;
326
1f629b7a
HS		 327 /* attach controller pointer to irq_data */
328 irq_data->intc = intc;
a21765a7 329
0fe3cb1e
HS		 330 parent_intc = intc->parent;
331
1f629b7a
HS		 332 /* set handler and flags */
333 switch (irq_data->type) {
334 case S3C_IRQTYPE_NONE:
335 return 0;
336 case S3C_IRQTYPE_EINT:
1c8408e3
HS		 337 /* On the S3C2412, the EINT0to3 have a parent irq
338 * but need the s3c_irq_eint0t4 chip
339 */
0fe3cb1e 340 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
1f629b7a
HS		 341 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
342 handle_edge_irq);
343 else
344 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
345 handle_edge_irq);
346 break;
347 case S3C_IRQTYPE_EDGE:
0fe3cb1e 348 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
1f629b7a
HS		 349 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
350 handle_edge_irq);
351 else
352 irq_set_chip_and_handler(virq, &s3c_irq_chip,
353 handle_edge_irq);
354 break;
355 case S3C_IRQTYPE_LEVEL:
0fe3cb1e 356 if (parent_intc)
1f629b7a
HS		 357 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
358 handle_level_irq);
359 else
360 irq_set_chip_and_handler(virq, &s3c_irq_chip,
361 handle_level_irq);
362 break;
363 default:
364 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
365 return -EINVAL;
a21765a7 366 }
1f629b7a
HS		 367 set_irq_flags(virq, IRQF_VALID);
368
0fe3cb1e 369 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
502a2989
HS		 370 if (irq_data->parent_irq > 31) {
371 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
372 irq_data->parent_irq);
1f629b7a
HS		 373 goto err;
374 }
a21765a7 375
502a2989 376 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1f629b7a
HS		 377 parent_irq_data->sub_intc = intc;
378 parent_irq_data->sub_bits |= (1UL << hw);
a21765a7 379
1f629b7a
HS		 380 /* attach the demuxer to the parent irq */
381 irqno = irq_find_mapping(parent_intc->domain,
382 irq_data->parent_irq);
383 if (!irqno) {
384 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
385 irq_data->parent_irq);
386 goto err;
387 }
388 irq_set_chained_handler(irqno, s3c_irq_demux);
a21765a7
BD		 389 }
390
1f629b7a 391 return 0;
a21765a7 392
1f629b7a
HS		 393err:
394 set_irq_flags(virq, 0);
a21765a7 395
1f629b7a
HS		 396 /* the only error can result from bad mapping data*/
397 return -EINVAL;
398}
a21765a7 399
1f629b7a
HS		 400static struct irq_domain_ops s3c24xx_irq_ops = {
401 .map = s3c24xx_irq_map,
402 .xlate = irq_domain_xlate_twocell,
403};
a21765a7 404
1f629b7a
HS		 405static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
406{
407 void __iomem *reg_source;
408 unsigned long pend;
409 unsigned long last;
410 int i;
a21765a7 411
1f629b7a
HS		 412 /* if intpnd is set, read the next pending irq from there */
413 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
a21765a7 414
1f629b7a
HS		 415 last = 0;
416 for (i = 0; i < 4; i++) {
417 pend = __raw_readl(reg_source);
a21765a7 418
1f629b7a 419 if (pend == 0 || pend == last)
a21765a7
BD		 420 break;
421
1f629b7a
HS		 422 __raw_writel(pend, intc->reg_pending);
423 if (intc->reg_intpnd)
424 __raw_writel(pend, intc->reg_intpnd);
a21765a7 425
1f629b7a
HS		 426 pr_info("irq: clearing pending status %08x\n", (int)pend);
427 last = pend;
a21765a7 428 }
1f629b7a 429}
a21765a7 430
1f629b7a
HS		 431struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
432 struct s3c_irq_data *irq_data,
433 struct s3c_irq_intc *parent,
434 unsigned long address)
435{
436 struct s3c_irq_intc *intc;
437 void __iomem *base = (void *)0xf6000000; /* static mapping */
438 int irq_num;
439 int irq_start;
1f629b7a
HS		 440 int ret;
441
442 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
443 if (!intc)
444 return ERR_PTR(-ENOMEM);
445
446 intc->irqs = irq_data;
447
448 if (parent)
449 intc->parent = parent;
450
451 /* select the correct data for the controller.
452 * Need to hard code the irq num start and offset
453 * to preserve the static mapping for now
454 */
455 switch (address) {
456 case 0x4a000000:
457 pr_debug("irq: found main intc\n");
458 intc->reg_pending = base;
459 intc->reg_mask = base + 0x08;
460 intc->reg_intpnd = base + 0x10;
461 irq_num = 32;
462 irq_start = S3C2410_IRQ(0);
1f629b7a
HS		 463 break;
464 case 0x4a000018:
465 pr_debug("irq: found subintc\n");
466 intc->reg_pending = base + 0x18;
467 intc->reg_mask = base + 0x1c;
468 irq_num = 29;
469 irq_start = S3C2410_IRQSUB(0);
1f629b7a
HS		 470 break;
471 case 0x4a000040:
472 pr_debug("irq: found intc2\n");
473 intc->reg_pending = base + 0x40;
474 intc->reg_mask = base + 0x48;
475 intc->reg_intpnd = base + 0x50;
476 irq_num = 8;
477 irq_start = S3C2416_IRQ(0);
1f629b7a
HS		 478 break;
479 case 0x560000a4:
480 pr_debug("irq: found eintc\n");
481 base = (void *)0xfd000000;
482
483 intc->reg_mask = base + 0xa4;
484 intc->reg_pending = base + 0x08;
5424f218 485 irq_num = 24;
1f629b7a 486 irq_start = S3C2410_IRQ(32);
1f629b7a
HS		 487 break;
488 default:
489 pr_err("irq: unsupported controller address\n");
490 ret = -EINVAL;
491 goto err;
492 }
a21765a7 493
1f629b7a
HS		 494 /* now that all the data is complete, init the irq-domain */
495 s3c24xx_clear_intc(intc);
496 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
5424f218 497 0, &s3c24xx_irq_ops,
1f629b7a
HS		 498 intc);
499 if (!intc->domain) {
500 pr_err("irq: could not create irq-domain\n");
501 ret = -EINVAL;
502 goto err;
503 }
a21765a7 504
1f629b7a 505 return intc;
a21765a7 506
1f629b7a
HS		 507err:
508 kfree(intc);
509 return ERR_PTR(ret);
510}
a21765a7 511
1f629b7a
HS		 512/* s3c24xx_init_irq
513 *
514 * Initialise S3C2410 IRQ system
515*/
a21765a7 516
1f629b7a
HS		 517static struct s3c_irq_data init_base[32] = {
518 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
519 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
520 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
521 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
522 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
523 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
524 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
525 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
526 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
527 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
528 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
529 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
530 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
531 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
532 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
533 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
534 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
535 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
536 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
537 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
538 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
539 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
540 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
541 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
542 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
543 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
544 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
545 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
546 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
547 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
548 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
549 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
550};
a21765a7 551
1f629b7a
HS		 552static struct s3c_irq_data init_eint[32] = {
553 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
554 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
555 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
556 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
557 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
558 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
559 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
560 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
561 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
562 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
563 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
564 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
565 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
566 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
567 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
568 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
569 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
570 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
571 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
572 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
573 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
574 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
575 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
576 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
577};
a21765a7 578
1f629b7a
HS		 579static struct s3c_irq_data init_subint[32] = {
580 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
581 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
582 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
583 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
584 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
585 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
586 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
587 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
588 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
589 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
590 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
591};
a21765a7 592
1f629b7a
HS		 593void __init s3c24xx_init_irq(void)
594{
595 struct s3c_irq_intc *main_intc;
a21765a7 596
1f629b7a
HS		 597#ifdef CONFIG_FIQ
598 init_FIQ(FIQ_START);
599#endif
a21765a7 600
1f629b7a
HS		 601 main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
602 if (IS_ERR(main_intc)) {
603 pr_err("irq: could not create main interrupt controller\n");
604 return;
a21765a7
BD		 605 }
606
1f629b7a
HS		 607 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
608 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
a21765a7 609}
ef602eb5 610
d3d5a2c9 611#ifdef CONFIG_CPU_S3C2412
4245944c 612static struct s3c_irq_data init_s3c2412base[32] = {
1c8408e3
HS		 613 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
614 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
615 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
616 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
4245944c
HS		 617 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
618 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
619 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
620 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
621 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
622 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
623 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
624 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
625 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
626 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
627 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
628 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
629 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
630 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
631 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
632 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
633 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
634 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
635 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
636 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
637 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
638 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
639 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
640 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
641 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
642 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
643 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
644 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
645};
d3d5a2c9 646
1c8408e3
HS		 647static struct s3c_irq_data init_s3c2412eint[32] = {
648 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
649 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
650 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
651 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
652 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
653 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
654 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
655 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
656 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
657 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
658 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
659 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
660 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
661 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
662 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
663 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
664 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
665 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
666 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
667 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
668 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
669 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
670 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
671 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
672};
673
4245944c
HS		 674static struct s3c_irq_data init_s3c2412subint[32] = {
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
680 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
681 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
682 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
683 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
684 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
685 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
686 { .type = S3C_IRQTYPE_NONE, },
687 { .type = S3C_IRQTYPE_NONE, },
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
690};
d3d5a2c9 691
4245944c 692void s3c2412_init_irq(void)
d3d5a2c9 693{
4245944c 694 struct s3c_irq_intc *main_intc;
d3d5a2c9 695
4245944c 696 pr_info("S3C2412: IRQ Support\n");
d3d5a2c9 697
4245944c
HS		 698#ifdef CONFIG_FIQ
699 init_FIQ(FIQ_START);
700#endif
d3d5a2c9 701
4245944c
HS		 702 main_intc = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, 0x4a000000);
703 if (IS_ERR(main_intc)) {
704 pr_err("irq: could not create main interrupt controller\n");
705 return;
706 }
d3d5a2c9 707
1c8408e3 708 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], main_intc, 0x560000a4);
4245944c 709 s3c24xx_init_intc(NULL, &init_s3c2412subint[0], main_intc, 0x4a000018);
d3d5a2c9 710}
d3d5a2c9
HS		 711#endif
712
ef602eb5 713#ifdef CONFIG_CPU_S3C2416
20f6c781
HS		 714static struct s3c_irq_data init_s3c2416base[32] = {
715 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
716 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
717 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
718 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
719 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
721 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
722 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
723 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
724 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
725 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
726 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
727 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
728 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
729 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
730 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
731 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
732 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
733 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
734 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
735 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
736 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
737 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
738 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
739 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
740 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
741 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
742 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
743 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
744 { .type = S3C_IRQTYPE_NONE, },
745 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
746 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
ef602eb5
HS		 747};
748
20f6c781
HS		 749static struct s3c_irq_data init_s3c2416subint[32] = {
750 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
751 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
752 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
753 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
754 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
755 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
756 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
757 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
758 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
759 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
760 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
761 { .type = S3C_IRQTYPE_NONE }, /* reserved */
762 { .type = S3C_IRQTYPE_NONE }, /* reserved */
763 { .type = S3C_IRQTYPE_NONE }, /* reserved */
764 { .type = S3C_IRQTYPE_NONE }, /* reserved */
765 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
766 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
777 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
778 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
ef602eb5
HS		 779};
780
20f6c781
HS		 781static struct s3c_irq_data init_s3c2416_second[32] = {
782 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
783 { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
784 { .type = S3C_IRQTYPE_NONE }, /* reserved */
785 { .type = S3C_IRQTYPE_NONE }, /* reserved */
786 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
787 { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
788 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
789 { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
ef602eb5
HS		 790};
791
4a282dd3 792void __init s3c2416_init_irq(void)
ef602eb5 793{
20f6c781 794 struct s3c_irq_intc *main_intc;
ef602eb5 795
20f6c781 796 pr_info("S3C2416: IRQ Support\n");
ef602eb5 797
20f6c781
HS		 798#ifdef CONFIG_FIQ
799 init_FIQ(FIQ_START);
800#endif
ef602eb5 801
20f6c781
HS		 802 main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
803 if (IS_ERR(main_intc)) {
804 pr_err("irq: could not create main interrupt controller\n");
805 return;
806 }
ef602eb5 807
20f6c781
HS		 808 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
809 s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
ef602eb5 810
20f6c781 811 s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
ef602eb5
HS		 812}
813
ef602eb5 814#endif
6b628917 815
ce6c164b 816#ifdef CONFIG_CPU_S3C2440
f0301673
HS		 817static struct s3c_irq_data init_s3c2440base[32] = {
818 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
819 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
820 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
821 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
823 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
824 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
825 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
826 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
827 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
828 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
829 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
830 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
831 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
832 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
833 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
834 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
835 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
836 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
837 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
838 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
839 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
840 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
841 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
842 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
843 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
844 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
845 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
846 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
847 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
848 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
849 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
850};
2286cf46 851
f0301673
HS		 852static struct s3c_irq_data init_s3c2440subint[32] = {
853 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
862 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
863 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
2286cf46
HS		 868};
869
7cefed5e 870void __init s3c2440_init_irq(void)
2286cf46 871{
f0301673 872 struct s3c_irq_intc *main_intc;
6f8d7ea2 873
f0301673 874 pr_info("S3C2440: IRQ Support\n");
6f8d7ea2 875
f0301673
HS		 876#ifdef CONFIG_FIQ
877 init_FIQ(FIQ_START);
878#endif
6f8d7ea2 879
f0301673
HS		 880 main_intc = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000);
881 if (IS_ERR(main_intc)) {
882 pr_err("irq: could not create main interrupt controller\n");
883 return;
6f8d7ea2 884 }
7cefed5e 885
f0301673
HS		 886 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
887 s3c24xx_init_intc(NULL, &init_s3c2440subint[0], main_intc, 0x4a000018);
6f8d7ea2 888}
ce6c164b 889#endif
6f8d7ea2 890
ce6c164b 891#ifdef CONFIG_CPU_S3C2442
70644ade
HS		 892static struct s3c_irq_data init_s3c2442base[32] = {
893 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
894 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
895 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
896 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
897 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
898 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
899 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
900 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
901 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
902 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
903 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
904 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
905 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
906 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
907 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
908 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
909 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
910 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
911 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
912 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
913 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
914 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
915 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
916 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
917 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
918 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
919 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
920 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
921 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
923 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
924 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
925};
6f8d7ea2 926
70644ade
HS		 927static struct s3c_irq_data init_s3c2442subint[32] = {
928 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
929 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
930 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
931 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
932 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
933 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
934 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
935 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
936 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
937 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
938 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
939 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */
940 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */
941};
6f8d7ea2 942
70644ade
HS		 943void __init s3c2442_init_irq(void)
944{
945 struct s3c_irq_intc *main_intc;
6f8d7ea2 946
70644ade 947 pr_info("S3C2442: IRQ Support\n");
6f8d7ea2 948
70644ade
HS		 949#ifdef CONFIG_FIQ
950 init_FIQ(FIQ_START);
951#endif
ce6c164b 952
70644ade
HS		 953 main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000);
954 if (IS_ERR(main_intc)) {
955 pr_err("irq: could not create main interrupt controller\n");
956 return;
ce6c164b 957 }
70644ade
HS		 958
959 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
960 s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018);
6f8d7ea2 961}
ce6c164b 962#endif
6f8d7ea2 963
6b628917 964#ifdef CONFIG_CPU_S3C2443
f44ddba3
HS		 965static struct s3c_irq_data init_s3c2443base[32] = {
966 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
967 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
968 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
969 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
970 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
971 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
972 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
973 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
974 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
975 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
976 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
977 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
978 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
979 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
980 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
981 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
982 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
983 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
984 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
985 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
986 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
987 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
988 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
989 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
990 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
991 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
992 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
993 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
994 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
995 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
996 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
997 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
6b628917
HS		 998};
999
6b628917 1000
f44ddba3
HS		 1001static struct s3c_irq_data init_s3c2443subint[32] = {
1002 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1003 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1004 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1005 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1006 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1007 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1008 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1009 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1010 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1011 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1012 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1013 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1014 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1015 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1016 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1017 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1018 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1019 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1020 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1029 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1030 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
6b628917
HS		 1031};
1032
b499b7a8 1033void __init s3c2443_init_irq(void)
6b628917 1034{
f44ddba3 1035 struct s3c_irq_intc *main_intc;
6b628917 1036
f44ddba3 1037 pr_info("S3C2443: IRQ Support\n");
6b628917 1038
f44ddba3
HS		 1039#ifdef CONFIG_FIQ
1040 init_FIQ(FIQ_START);
1041#endif
6b628917 1042
f44ddba3
HS		 1043 main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
1044 if (IS_ERR(main_intc)) {
1045 pr_err("irq: could not create main interrupt controller\n");
1046 return;
1047 }
6b628917 1048
f44ddba3
HS		 1049 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
1050 s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
6b628917 1051}
6b628917 1052#endif
Linux 6.x block layer and io_uring tree(s)