[linux-2.6-block.git] / arch / arm / mach-s3c24xx / common.c

/* linux/arch/arm/plat-s3c24xx/cpu.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://www.simtec.co.uk/products/SWLINUX/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * Common code for S3C24XX machines
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/


#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <asm/irq.h>
#include <asm/cacheflush.h>
#include <asm/system_info.h>
#include <asm/system_misc.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/cpu-freq.h>
#include <plat/pll.h>

#include "common.h"

/* table of supported CPUs */

static const char name_s3c2410[]  = "S3C2410";
static const char name_s3c2412[]  = "S3C2412";
static const char name_s3c2416[]  = "S3C2416/S3C2450";
static const char name_s3c2440[]  = "S3C2440";
static const char name_s3c2442[]  = "S3C2442";
static const char name_s3c2442b[]  = "S3C2442B";
static const char name_s3c2443[]  = "S3C2443";
static const char name_s3c2410a[] = "S3C2410A";
static const char name_s3c2440a[] = "S3C2440A";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= 0x32410000,
		.idmask		= 0xffffffff,
		.map_io		= s3c2410_map_io,
		.init_clocks	= s3c2410_init_clocks,
		.init_uarts	= s3c2410_init_uarts,
		.init		= s3c2410_init,
		.name		= name_s3c2410
	},
	{
		.idcode		= 0x32410002,
		.idmask		= 0xffffffff,
		.map_io		= s3c2410_map_io,
		.init_clocks	= s3c2410_init_clocks,
		.init_uarts	= s3c2410_init_uarts,
		.init		= s3c2410a_init,
		.name		= name_s3c2410a
	},
	{
		.idcode		= 0x32440000,
		.idmask		= 0xffffffff,
		.map_io		= s3c2440_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2440_init,
		.name		= name_s3c2440
	},
	{
		.idcode		= 0x32440001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2440_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2440_init,
		.name		= name_s3c2440a
	},
	{
		.idcode		= 0x32440aaa,
		.idmask		= 0xffffffff,
		.map_io		= s3c2442_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2442_init,
		.name		= name_s3c2442
	},
	{
		.idcode		= 0x32440aab,
		.idmask		= 0xffffffff,
		.map_io		= s3c2442_map_io,
		.init_clocks	= s3c244x_init_clocks,
		.init_uarts	= s3c244x_init_uarts,
		.init		= s3c2442_init,
		.name		= name_s3c2442b
	},
	{
		.idcode		= 0x32412001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2412_map_io,
		.init_clocks	= s3c2412_init_clocks,
		.init_uarts	= s3c2412_init_uarts,
		.init		= s3c2412_init,
		.name		= name_s3c2412,
	},
	{			/* a newer version of the s3c2412 */
		.idcode		= 0x32412003,
		.idmask		= 0xffffffff,
		.map_io		= s3c2412_map_io,
		.init_clocks	= s3c2412_init_clocks,
		.init_uarts	= s3c2412_init_uarts,
		.init		= s3c2412_init,
		.name		= name_s3c2412,
	},
	{			/* a strange version of the s3c2416 */
		.idcode		= 0x32450003,
		.idmask		= 0xffffffff,
		.map_io		= s3c2416_map_io,
		.init_clocks	= s3c2416_init_clocks,
		.init_uarts	= s3c2416_init_uarts,
		.init		= s3c2416_init,
		.name		= name_s3c2416,
	},
	{
		.idcode		= 0x32443001,
		.idmask		= 0xffffffff,
		.map_io		= s3c2443_map_io,
		.init_clocks	= s3c2443_init_clocks,
		.init_uarts	= s3c2443_init_uarts,
		.init		= s3c2443_init,
		.name		= name_s3c2443,
	},
};

/* minimal IO mapping */

static struct map_desc s3c_iodesc[] __initdata = {
	IODESC_ENT(GPIO),
	IODESC_ENT(IRQ),
	IODESC_ENT(MEMCTRL),
	IODESC_ENT(UART)
};

/* read cpu identificaiton code */

static unsigned long s3c24xx_read_idcode_v5(void)
{
#if defined(CONFIG_CPU_S3C2416)
	/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */

	u32 gs = __raw_readl(S3C24XX_GSTATUS1);

	/* test for s3c2416 or similar device */
	if ((gs >> 16) == 0x3245)
		return gs;
#endif

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
	return __raw_readl(S3C2412_GSTATUS1);
#else
	return 1UL;	/* don't look like an 2400 */
#endif
}

static unsigned long s3c24xx_read_idcode_v4(void)
{
	return __raw_readl(S3C2410_GSTATUS1);
}

static void s3c24xx_default_idle(void)
{
	unsigned long tmp = 0;
	int i;

	/* idle the system by using the idle mode which will wait for an
	 * interrupt to happen before restarting the system.
	 */

	/* Warning: going into idle state upsets jtag scanning */

	__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
		     S3C2410_CLKCON);

	/* the samsung port seems to do a loop and then unset idle.. */
	for (i = 0; i < 50; i++)
		tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */

	/* this bit is not cleared on re-start... */

	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
		     S3C2410_CLKCON);
}

void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
{
	arm_pm_idle = s3c24xx_default_idle;

	/* initialise the io descriptors we need for initialisation */
	iotable_init(mach_desc, size);
	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));

	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
		samsung_cpu_id = s3c24xx_read_idcode_v5();
	} else {
		samsung_cpu_id = s3c24xx_read_idcode_v4();
	}
	s3c24xx_init_cpu();

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}

/* Serial port registrations */

#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )

static struct resource s3c2410_uart0_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
			IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
			NULL, IORESOURCE_IRQ)
};

static struct resource s3c2410_uart1_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
			IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
			NULL, IORESOURCE_IRQ)
};

static struct resource s3c2410_uart2_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
			IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
			NULL, IORESOURCE_IRQ)
};

static struct resource s3c2410_uart3_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
			IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
			NULL, IORESOURCE_IRQ)
};

struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
	[0] = {
		.resources	= s3c2410_uart0_resource,
		.nr_resources	= ARRAY_SIZE(s3c2410_uart0_resource),
	},
	[1] = {
		.resources	= s3c2410_uart1_resource,
		.nr_resources	= ARRAY_SIZE(s3c2410_uart1_resource),
	},
	[2] = {
		.resources	= s3c2410_uart2_resource,
		.nr_resources	= ARRAY_SIZE(s3c2410_uart2_resource),
	},
	[3] = {
		.resources	= s3c2410_uart3_resource,
		.nr_resources	= ARRAY_SIZE(s3c2410_uart3_resource),
	},
};

/* initialise all the clocks */

void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
					   unsigned long hclk,
					   unsigned long pclk)
{
	clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
					clk_xtal.rate);

	clk_mpll.rate = fclk;
	clk_h.rate = hclk;
	clk_p.rate = pclk;
	clk_f.rate = fclk;
}
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/plat-s3c24xx/cpu.c
1da177e4 LT	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://www.simtec.co.uk/products/SWLINUX/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
4a9f52fd	7	* Common code for S3C24XX machines
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/ioport.h>
b6d1f542	29	#include <linux/serial_core.h>
d052d1be	30	#include <linux/platform_device.h>
3c7d9c81	31	#include <linux/delay.h>
fced80c7	32	#include <linux/io.h>
1da177e4	33
a09e64fb	34	#include <mach/hardware.h>
92311272	35	#include <mach/regs-clock.h>
1da177e4	36	#include <asm/irq.h>
3c7d9c81	37	#include <asm/cacheflush.h>
9f97da78	38	#include <asm/system_info.h>
86dfe446	39	#include <asm/system_misc.h>
1da177e4 LT	40
	41	#include <asm/mach/arch.h>
	42	#include <asm/mach/map.h>
	43
a09e64fb	44	#include <mach/regs-gpio.h>
a2b7ba9c	45	#include <plat/regs-serial.h>
1da177e4	46
a2b7ba9c BD	47	#include <plat/cpu.h>
a2b7ba9c BD	48	#include <plat/devs.h>
d5120ae7	49	#include <plat/clock.h>
2473f713 HS	50	#include <plat/cpu-freq.h>
2473f713 HS	51	#include <plat/pll.h>
1da177e4	52
e1a621da HS	53	#include "common.h"
e1a621da HS	54
1da177e4 LT	55	/* table of supported CPUs */
	56
	57	static const char name_s3c2410[] = "S3C2410";
68d9ab39	58	static const char name_s3c2412[] = "S3C2412";
63b1f51b	59	static const char name_s3c2416[] = "S3C2416/S3C2450";
1da177e4	60	static const char name_s3c2440[] = "S3C2440";
96ce2385	61	static const char name_s3c2442[] = "S3C2442";
f5fb9b1a	62	static const char name_s3c2442b[] = "S3C2442B";
e4d06e39	63	static const char name_s3c2443[] = "S3C2443";
1da177e4 LT	64	static const char name_s3c2410a[] = "S3C2410A";
	65	static const char name_s3c2440a[] = "S3C2440A";
	66
	67	static struct cpu_table cpu_ids[] __initdata = {
	68	{
	69	.idcode = 0x32410000,
	70	.idmask = 0xffffffff,
	71	.map_io = s3c2410_map_io,
	72	.init_clocks = s3c2410_init_clocks,
	73	.init_uarts = s3c2410_init_uarts,
	74	.init = s3c2410_init,
	75	.name = name_s3c2410
	76	},
	77	{
	78	.idcode = 0x32410002,
	79	.idmask = 0xffffffff,
	80	.map_io = s3c2410_map_io,
	81	.init_clocks = s3c2410_init_clocks,
	82	.init_uarts = s3c2410_init_uarts,
f0176794	83	.init = s3c2410a_init,
1da177e4 LT	84	.name = name_s3c2410a
	85	},
	86	{
	87	.idcode = 0x32440000,
	88	.idmask = 0xffffffff,
812c4e40	89	.map_io = s3c2440_map_io,
96ce2385 BD	90	.init_clocks = s3c244x_init_clocks,
96ce2385 BD	91	.init_uarts = s3c244x_init_uarts,
1da177e4 LT	92	.init = s3c2440_init,
	93	.name = name_s3c2440
	94	},
	95	{
	96	.idcode = 0x32440001,
	97	.idmask = 0xffffffff,
812c4e40	98	.map_io = s3c2440_map_io,
96ce2385 BD	99	.init_clocks = s3c244x_init_clocks,
96ce2385 BD	100	.init_uarts = s3c244x_init_uarts,
1da177e4 LT	101	.init = s3c2440_init,
1da177e4 LT	102	.name = name_s3c2440a
83f755f5	103	},
96ce2385 BD	104	{
	105	.idcode = 0x32440aaa,
	106	.idmask = 0xffffffff,
812c4e40	107	.map_io = s3c2442_map_io,
96ce2385 BD	108	.init_clocks = s3c244x_init_clocks,
	109	.init_uarts = s3c244x_init_uarts,
	110	.init = s3c2442_init,
	111	.name = name_s3c2442
	112	},
f5fb9b1a HW	113	{
	114	.idcode = 0x32440aab,
	115	.idmask = 0xffffffff,
812c4e40	116	.map_io = s3c2442_map_io,
f5fb9b1a HW	117	.init_clocks = s3c244x_init_clocks,
	118	.init_uarts = s3c244x_init_uarts,
	119	.init = s3c2442_init,
	120	.name = name_s3c2442b
	121	},
68d9ab39 BD	122	{
	123	.idcode = 0x32412001,
	124	.idmask = 0xffffffff,
	125	.map_io = s3c2412_map_io,
	126	.init_clocks = s3c2412_init_clocks,
	127	.init_uarts = s3c2412_init_uarts,
	128	.init = s3c2412_init,
	129	.name = name_s3c2412,
	130	},
d9bc55fa BD	131	{ /* a newer version of the s3c2412 */
	132	.idcode = 0x32412003,
	133	.idmask = 0xffffffff,
	134	.map_io = s3c2412_map_io,
	135	.init_clocks = s3c2412_init_clocks,
	136	.init_uarts = s3c2412_init_uarts,
	137	.init = s3c2412_init,
	138	.name = name_s3c2412,
	139	},
f1290a49 YK	140	{ /* a strange version of the s3c2416 */
	141	.idcode = 0x32450003,
	142	.idmask = 0xffffffff,
	143	.map_io = s3c2416_map_io,
	144	.init_clocks = s3c2416_init_clocks,
	145	.init_uarts = s3c2416_init_uarts,
	146	.init = s3c2416_init,
	147	.name = name_s3c2416,
	148	},
e4d06e39 BD	149	{
	150	.idcode = 0x32443001,
	151	.idmask = 0xffffffff,
	152	.map_io = s3c2443_map_io,
	153	.init_clocks = s3c2443_init_clocks,
	154	.init_uarts = s3c2443_init_uarts,
	155	.init = s3c2443_init,
	156	.name = name_s3c2443,
	157	},
1da177e4 LT	158	};
	159
	160	/* minimal IO mapping */
	161
	162	static struct map_desc s3c_iodesc[] __initdata = {
	163	IODESC_ENT(GPIO),
	164	IODESC_ENT(IRQ),
	165	IODESC_ENT(MEMCTRL),
	166	IODESC_ENT(UART)
	167	};
	168
74b265d4	169	/* read cpu identificaiton code */
1da177e4	170
68d9ab39 BD	171	static unsigned long s3c24xx_read_idcode_v5(void)
68d9ab39 BD	172	{
d11a7d71 BD	173	#if defined(CONFIG_CPU_S3C2416)
	174	/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
	175
	176	u32 gs = __raw_readl(S3C24XX_GSTATUS1);
	177
	178	/* test for s3c2416 or similar device */
	179	if ((gs >> 16) == 0x3245)
	180	return gs;
	181	#endif
	182
68d9ab39 BD	183	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413)
	184	return __raw_readl(S3C2412_GSTATUS1);
	185	#else
	186	return 1UL; /* don't look like an 2400 */
	187	#endif
	188	}
	189
	190	static unsigned long s3c24xx_read_idcode_v4(void)
	191	{
68d9ab39	192	return __raw_readl(S3C2410_GSTATUS1);
68d9ab39 BD	193	}
68d9ab39 BD	194
92311272 NP	195	static void s3c24xx_default_idle(void)
92311272 NP	196	{
813f13e7	197	unsigned long tmp = 0;
92311272 NP	198	int i;
	199
	200	/* idle the system by using the idle mode which will wait for an
	201	* interrupt to happen before restarting the system.
	202	*/
	203
	204	/* Warning: going into idle state upsets jtag scanning */
	205
	206	__raw_writel(__raw_readl(S3C2410_CLKCON) \| S3C2410_CLKCON_IDLE,
	207	S3C2410_CLKCON);
	208
	209	/* the samsung port seems to do a loop and then unset idle.. */
	210	for (i = 0; i < 50; i++)
	211	tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
	212
	213	/* this bit is not cleared on re-start... */
	214
	215	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
	216	S3C2410_CLKCON);
	217	}
	218
1da177e4 LT	219	void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
1da177e4 LT	220	{
92311272 NP	221	arm_pm_idle = s3c24xx_default_idle;
92311272 NP	222
1da177e4	223	/* initialise the io descriptors we need for initialisation */
74b265d4	224	iotable_init(mach_desc, size);
1da177e4 LT	225	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
1da177e4 LT	226
68d9ab39	227	if (cpu_architecture() >= CPU_ARCH_ARMv5) {
c06af3cc	228	samsung_cpu_id = s3c24xx_read_idcode_v5();
68d9ab39	229	} else {
c06af3cc	230	samsung_cpu_id = s3c24xx_read_idcode_v4();
68d9ab39	231	}
e6d1cb9f	232	s3c24xx_init_cpu();
83f755f5	233
c06af3cc	234	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
66a9b49a	235	}
618ae08a HS	236
	237	/* Serial port registrations */
	238
9ee51f01 AB	239	#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
	240	#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
	241	#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
	242	#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
	243
618ae08a	244	static struct resource s3c2410_uart0_resource[] = {
99dbdd98 TB	245	[0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
	246	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
	247	IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
	248	NULL, IORESOURCE_IRQ)
618ae08a HS	249	};
	250
	251	static struct resource s3c2410_uart1_resource[] = {
99dbdd98 TB	252	[0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
	253	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
	254	IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
	255	NULL, IORESOURCE_IRQ)
618ae08a HS	256	};
	257
	258	static struct resource s3c2410_uart2_resource[] = {
99dbdd98 TB	259	[0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
	260	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
	261	IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
	262	NULL, IORESOURCE_IRQ)
618ae08a HS	263	};
	264
	265	static struct resource s3c2410_uart3_resource[] = {
99dbdd98 TB	266	[0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
	267	[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
	268	IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
	269	NULL, IORESOURCE_IRQ)
618ae08a HS	270	};
	271
	272	struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
	273	[0] = {
	274	.resources = s3c2410_uart0_resource,
	275	.nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
	276	},
	277	[1] = {
	278	.resources = s3c2410_uart1_resource,
	279	.nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
	280	},
	281	[2] = {
	282	.resources = s3c2410_uart2_resource,
	283	.nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
	284	},
	285	[3] = {
	286	.resources = s3c2410_uart3_resource,
	287	.nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
	288	},
	289	};
2473f713 HS	290
	291	/* initialise all the clocks */
	292
	293	void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
	294	unsigned long hclk,
	295	unsigned long pclk)
	296	{
	297	clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
	298	clk_xtal.rate);
	299
	300	clk_mpll.rate = fclk;
	301	clk_h.rate = hclk;
	302	clk_p.rate = pclk;
	303	clk_f.rate = fclk;
	304	}