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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / arm / mach-s3c24xx / common.c
CommitLineData
a21765a7 1/* linux/arch/arm/plat-s3c24xx/cpu.c
1da177e4
LT		 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
4a9f52fd 7 * Common code for S3C24XX machines
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
b6d1f542 29#include <linux/serial_core.h>
1c161fd0 30#include <clocksource/samsung_pwm.h>
d052d1be 31#include <linux/platform_device.h>
3c7d9c81 32#include <linux/delay.h>
fced80c7 33#include <linux/io.h>
f2dda07d 34#include <linux/platform_data/dma-s3c24xx.h>
1da177e4 35
a09e64fb 36#include <mach/hardware.h>
92311272 37#include <mach/regs-clock.h>
1da177e4 38#include <asm/irq.h>
3c7d9c81 39#include <asm/cacheflush.h>
9f97da78 40#include <asm/system_info.h>
86dfe446 41#include <asm/system_misc.h>
1da177e4
LT		 42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45
a09e64fb 46#include <mach/regs-gpio.h>
a2b7ba9c 47#include <plat/regs-serial.h>
f2dda07d 48#include <mach/dma.h>
1da177e4 49
a2b7ba9c
BD		 50#include <plat/cpu.h>
51#include <plat/devs.h>
d5120ae7 52#include <plat/clock.h>
2473f713
HS		 53#include <plat/cpu-freq.h>
54#include <plat/pll.h>
1c161fd0 55#include <plat/pwm-core.h>
1da177e4 56
e1a621da
HS		 57#include "common.h"
58
1da177e4
LT		 59/* table of supported CPUs */
60
61static const char name_s3c2410[] = "S3C2410";
68d9ab39 62static const char name_s3c2412[] = "S3C2412";
63b1f51b 63static const char name_s3c2416[] = "S3C2416/S3C2450";
1da177e4 64static const char name_s3c2440[] = "S3C2440";
96ce2385 65static const char name_s3c2442[] = "S3C2442";
f5fb9b1a 66static const char name_s3c2442b[] = "S3C2442B";
e4d06e39 67static const char name_s3c2443[] = "S3C2443";
1da177e4
LT		 68static const char name_s3c2410a[] = "S3C2410A";
69static const char name_s3c2440a[] = "S3C2440A";
70
71static struct cpu_table cpu_ids[] __initdata = {
72 {
73 .idcode = 0x32410000,
74 .idmask = 0xffffffff,
75 .map_io = s3c2410_map_io,
76 .init_clocks = s3c2410_init_clocks,
77 .init_uarts = s3c2410_init_uarts,
78 .init = s3c2410_init,
79 .name = name_s3c2410
80 },
81 {
82 .idcode = 0x32410002,
83 .idmask = 0xffffffff,
84 .map_io = s3c2410_map_io,
85 .init_clocks = s3c2410_init_clocks,
86 .init_uarts = s3c2410_init_uarts,
f0176794 87 .init = s3c2410a_init,
1da177e4
LT		 88 .name = name_s3c2410a
89 },
90 {
91 .idcode = 0x32440000,
92 .idmask = 0xffffffff,
812c4e40 93 .map_io = s3c2440_map_io,
96ce2385
BD		 94 .init_clocks = s3c244x_init_clocks,
95 .init_uarts = s3c244x_init_uarts,
1da177e4
LT		 96 .init = s3c2440_init,
97 .name = name_s3c2440
98 },
99 {
100 .idcode = 0x32440001,
101 .idmask = 0xffffffff,
812c4e40 102 .map_io = s3c2440_map_io,
96ce2385
BD		 103 .init_clocks = s3c244x_init_clocks,
104 .init_uarts = s3c244x_init_uarts,
1da177e4
LT		 105 .init = s3c2440_init,
106 .name = name_s3c2440a
83f755f5 107 },
96ce2385
BD		 108 {
109 .idcode = 0x32440aaa,
110 .idmask = 0xffffffff,
812c4e40 111 .map_io = s3c2442_map_io,
96ce2385
BD		 112 .init_clocks = s3c244x_init_clocks,
113 .init_uarts = s3c244x_init_uarts,
114 .init = s3c2442_init,
115 .name = name_s3c2442
116 },
f5fb9b1a
HW		 117 {
118 .idcode = 0x32440aab,
119 .idmask = 0xffffffff,
812c4e40 120 .map_io = s3c2442_map_io,
f5fb9b1a
HW		 121 .init_clocks = s3c244x_init_clocks,
122 .init_uarts = s3c244x_init_uarts,
123 .init = s3c2442_init,
124 .name = name_s3c2442b
125 },
68d9ab39
BD		 126 {
127 .idcode = 0x32412001,
128 .idmask = 0xffffffff,
129 .map_io = s3c2412_map_io,
130 .init_clocks = s3c2412_init_clocks,
131 .init_uarts = s3c2412_init_uarts,
132 .init = s3c2412_init,
133 .name = name_s3c2412,
134 },
d9bc55fa
BD		 135 { /* a newer version of the s3c2412 */
136 .idcode = 0x32412003,
137 .idmask = 0xffffffff,
138 .map_io = s3c2412_map_io,
139 .init_clocks = s3c2412_init_clocks,
140 .init_uarts = s3c2412_init_uarts,
141 .init = s3c2412_init,
142 .name = name_s3c2412,
143 },
f1290a49
YK		 144 { /* a strange version of the s3c2416 */
145 .idcode = 0x32450003,
146 .idmask = 0xffffffff,
147 .map_io = s3c2416_map_io,
148 .init_clocks = s3c2416_init_clocks,
149 .init_uarts = s3c2416_init_uarts,
150 .init = s3c2416_init,
151 .name = name_s3c2416,
152 },
e4d06e39
BD		 153 {
154 .idcode = 0x32443001,
155 .idmask = 0xffffffff,
156 .map_io = s3c2443_map_io,
157 .init_clocks = s3c2443_init_clocks,
158 .init_uarts = s3c2443_init_uarts,
159 .init = s3c2443_init,
160 .name = name_s3c2443,
161 },
1da177e4
LT		 162};
163
164/* minimal IO mapping */
165
166static struct map_desc s3c_iodesc[] __initdata = {
167 IODESC_ENT(GPIO),
168 IODESC_ENT(IRQ),
169 IODESC_ENT(MEMCTRL),
170 IODESC_ENT(UART)
171};
172
74b265d4 173/* read cpu identificaiton code */
1da177e4 174
68d9ab39
BD		 175static unsigned long s3c24xx_read_idcode_v5(void)
176{
d11a7d71
BD		 177#if defined(CONFIG_CPU_S3C2416)
178 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
179
180 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
181
182 /* test for s3c2416 or similar device */
183 if ((gs >> 16) == 0x3245)
184 return gs;
185#endif
186
68d9ab39
BD		 187#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
188 return __raw_readl(S3C2412_GSTATUS1);
189#else
190 return 1UL; /* don't look like an 2400 */
191#endif
192}
193
194static unsigned long s3c24xx_read_idcode_v4(void)
195{
68d9ab39 196 return __raw_readl(S3C2410_GSTATUS1);
68d9ab39
BD		 197}
198
92311272
NP		 199static void s3c24xx_default_idle(void)
200{
813f13e7 201 unsigned long tmp = 0;
92311272
NP		 202 int i;
203
204 /* idle the system by using the idle mode which will wait for an
205 * interrupt to happen before restarting the system.
206 */
207
208 /* Warning: going into idle state upsets jtag scanning */
209
210 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
211 S3C2410_CLKCON);
212
213 /* the samsung port seems to do a loop and then unset idle.. */
214 for (i = 0; i < 50; i++)
215 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
216
217 /* this bit is not cleared on re-start... */
218
219 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
220 S3C2410_CLKCON);
221}
222
1c161fd0
TF		 223static struct samsung_pwm_variant s3c24xx_pwm_variant = {
224 .bits = 16,
225 .div_base = 1,
226 .has_tint_cstat = false,
227 .tclk_mask = (1 << 4),
228};
229
1da177e4
LT		 230void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
231{
92311272
NP		 232 arm_pm_idle = s3c24xx_default_idle;
233
1da177e4 234 /* initialise the io descriptors we need for initialisation */
74b265d4 235 iotable_init(mach_desc, size);
1da177e4
LT		 236 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
237
68d9ab39 238 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
c06af3cc 239 samsung_cpu_id = s3c24xx_read_idcode_v5();
68d9ab39 240 } else {
c06af3cc 241 samsung_cpu_id = s3c24xx_read_idcode_v4();
68d9ab39 242 }
e6d1cb9f 243 s3c24xx_init_cpu();
83f755f5 244
c06af3cc 245 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
1c161fd0
TF		 246
247 samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
66a9b49a 248}
618ae08a 249
4280506a
TF		 250void __init samsung_set_timer_source(unsigned int event, unsigned int source)
251{
252 s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
253 s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
254}
255
256void __init samsung_timer_init(void)
257{
258 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
259 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
260 };
261
262 samsung_pwm_clocksource_init(S3C_VA_TIMER,
263 timer_irqs, &s3c24xx_pwm_variant);
264}
265
618ae08a
HS		 266/* Serial port registrations */
267
9ee51f01
AB		 268#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
269#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
270#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
271#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
272
618ae08a 273static struct resource s3c2410_uart0_resource[] = {
99dbdd98
TB		 274 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
275 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
276 IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
277 NULL, IORESOURCE_IRQ)
618ae08a
HS		 278};
279
280static struct resource s3c2410_uart1_resource[] = {
99dbdd98
TB		 281 [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
282 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
283 IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
284 NULL, IORESOURCE_IRQ)
618ae08a
HS		 285};
286
287static struct resource s3c2410_uart2_resource[] = {
99dbdd98
TB		 288 [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
289 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
290 IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
291 NULL, IORESOURCE_IRQ)
618ae08a
HS		 292};
293
294static struct resource s3c2410_uart3_resource[] = {
99dbdd98
TB		 295 [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
296 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
297 IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
298 NULL, IORESOURCE_IRQ)
618ae08a
HS		 299};
300
301struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
302 [0] = {
303 .resources = s3c2410_uart0_resource,
304 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
305 },
306 [1] = {
307 .resources = s3c2410_uart1_resource,
308 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
309 },
310 [2] = {
311 .resources = s3c2410_uart2_resource,
312 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
313 },
314 [3] = {
315 .resources = s3c2410_uart3_resource,
316 .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
317 },
318};
2473f713
HS		 319
320/* initialise all the clocks */
321
322void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
323 unsigned long hclk,
324 unsigned long pclk)
325{
326 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
327 clk_xtal.rate);
328
329 clk_mpll.rate = fclk;
330 clk_h.rate = hclk;
331 clk_p.rate = pclk;
332 clk_f.rate = fclk;
333}
f2dda07d
HS		 334
335#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
336 defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
337static struct resource s3c2410_dma_resource[] = {
338 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
339 [1] = DEFINE_RES_IRQ(IRQ_DMA0),
340 [2] = DEFINE_RES_IRQ(IRQ_DMA1),
341 [3] = DEFINE_RES_IRQ(IRQ_DMA2),
342 [4] = DEFINE_RES_IRQ(IRQ_DMA3),
343};
344#endif
345
1fecf895
HS		 346#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
347static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
348 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
349 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
350 [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
351 S3C24XX_DMA_CHANREQ(2, 2) |
352 S3C24XX_DMA_CHANREQ(1, 3),
353 },
354 [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
355 [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
356 [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
357 [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
358 [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
359 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
360 S3C24XX_DMA_CHANREQ(3, 2) |
361 S3C24XX_DMA_CHANREQ(3, 3),
362 },
363 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
364 S3C24XX_DMA_CHANREQ(1, 2),
365 },
366 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
367 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
368 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
369 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
370 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
371};
372
373static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
374 .num_phy_channels = 4,
375 .channels = s3c2410_dma_channels,
376 .num_channels = DMACH_MAX,
377};
378
379struct platform_device s3c2410_device_dma = {
380 .name = "s3c2410-dma",
381 .id = 0,
382 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
383 .resource = s3c2410_dma_resource,
384 .dev = {
385 .platform_data = &s3c2410_dma_platdata,
386 },
387};
388#endif
389
f2dda07d
HS		 390#ifdef CONFIG_CPU_S3C2412
391static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
392 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
393 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
394 [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
395 [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
396 [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
397 [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
398 [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
399 [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
400 [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
401 [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
402 [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
403 [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
404 [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
405 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
406 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
407 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
408 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
409 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
410 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
411 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
412};
413
414static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
415 .num_phy_channels = 4,
416 .channels = s3c2412_dma_channels,
417 .num_channels = DMACH_MAX,
418};
419
420struct platform_device s3c2412_device_dma = {
421 .name = "s3c2412-dma",
422 .id = 0,
423 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
424 .resource = s3c2410_dma_resource,
425 .dev = {
426 .platform_data = &s3c2412_dma_platdata,
427 },
428};
429#endif
430
1fecf895
HS		 431#if defined(CONFIG_CPU_S3C2440)
432static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
433 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
434 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
435 [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
436 S3C24XX_DMA_CHANREQ(6, 1) |
437 S3C24XX_DMA_CHANREQ(2, 2) |
438 S3C24XX_DMA_CHANREQ(1, 3),
439 },
440 [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
441 [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
442 [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
443 [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
444 [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
445 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
446 S3C24XX_DMA_CHANREQ(3, 2) |
447 S3C24XX_DMA_CHANREQ(3, 3),
448 },
449 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
450 S3C24XX_DMA_CHANREQ(1, 2),
451 },
452 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
453 S3C24XX_DMA_CHANREQ(0, 2),
454 },
455 [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
456 S3C24XX_DMA_CHANREQ(5, 2),
457 },
458 [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
459 S3C24XX_DMA_CHANREQ(6, 3),
460 },
461 [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
462 S3C24XX_DMA_CHANREQ(5, 3),
463 },
464 [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
465 [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
466 [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
467 [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
468};
469
470static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
471 .num_phy_channels = 4,
472 .channels = s3c2440_dma_channels,
473 .num_channels = DMACH_MAX,
474};
475
476struct platform_device s3c2440_device_dma = {
477 .name = "s3c2410-dma",
478 .id = 0,
479 .num_resources = ARRAY_SIZE(s3c2410_dma_resource),
480 .resource = s3c2410_dma_resource,
481 .dev = {
482 .platform_data = &s3c2440_dma_platdata,
483 },
484};
485#endif
486
f2dda07d
HS		 487#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416)
488static struct resource s3c2443_dma_resource[] = {
489 [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
490 [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
491 [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
492 [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
493 [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
494 [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
495 [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
496};
497
498static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
499 [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
500 [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
501 [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
502 [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
503 [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
504 [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
505 [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
506 [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
507 [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
508 [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
509 [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
510 [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
511 [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
512 [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
513 [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
514 [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
515 [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
516 [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
517 [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
518 [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
519 [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
520};
521
522static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
523 .num_phy_channels = 6,
524 .channels = s3c2443_dma_channels,
525 .num_channels = DMACH_MAX,
526};
527
528struct platform_device s3c2443_device_dma = {
529 .name = "s3c2443-dma",
530 .id = 0,
531 .num_resources = ARRAY_SIZE(s3c2443_dma_resource),
532 .resource = s3c2443_dma_resource,
533 .dev = {
534 .platform_data = &s3c2443_dma_platdata,
535 },
536};
537#endif
Linux 6.x block layer and io_uring tree(s)