Commit | Line | Data |
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a21765a7 | 1 | /* linux/arch/arm/mach-s3c2440/mach-rx3715.c |
1da177e4 | 2 | * |
e02f8664 | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * http://www.handhelds.org/projects/rx3715.html | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
8d717a52 | 18 | #include <linux/memblock.h> |
1da177e4 LT |
19 | #include <linux/timer.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/console.h> | |
333a42e1 | 23 | #include <linux/sysdev.h> |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/serial_core.h> |
26 | #include <linux/serial.h> | |
fced80c7 | 27 | #include <linux/io.h> |
272eb575 BD |
28 | #include <linux/mtd/mtd.h> |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/mtd/nand_ecc.h> | |
31 | #include <linux/mtd/partitions.h> | |
32 | ||
1da177e4 LT |
33 | #include <asm/mach/arch.h> |
34 | #include <asm/mach/map.h> | |
35 | #include <asm/mach/irq.h> | |
36 | ||
a09e64fb | 37 | #include <mach/hardware.h> |
1da177e4 LT |
38 | #include <asm/irq.h> |
39 | #include <asm/mach-types.h> | |
40 | ||
a2b7ba9c | 41 | #include <plat/regs-serial.h> |
a09e64fb RK |
42 | #include <mach/regs-gpio.h> |
43 | #include <mach/regs-lcd.h> | |
e838ffc2 | 44 | |
a09e64fb | 45 | #include <mach/h1940.h> |
7926b5a3 | 46 | #include <plat/nand.h> |
a09e64fb | 47 | #include <mach/fb.h> |
1da177e4 | 48 | |
d5120ae7 | 49 | #include <plat/clock.h> |
a2b7ba9c BD |
50 | #include <plat/devs.h> |
51 | #include <plat/cpu.h> | |
52 | #include <plat/pm.h> | |
1da177e4 LT |
53 | |
54 | static struct map_desc rx3715_iodesc[] __initdata = { | |
55 | /* dump ISA space somewhere unused */ | |
56 | ||
ff6ffa82 BD |
57 | { |
58 | .virtual = (u32)S3C24XX_VA_ISA_WORD, | |
59 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
60 | .length = SZ_1M, | |
61 | .type = MT_DEVICE, | |
62 | }, { | |
63 | .virtual = (u32)S3C24XX_VA_ISA_BYTE, | |
64 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
65 | .length = SZ_1M, | |
66 | .type = MT_DEVICE, | |
67 | }, | |
1da177e4 LT |
68 | }; |
69 | ||
1da177e4 LT |
70 | static struct s3c2410_uartcfg rx3715_uartcfgs[] = { |
71 | [0] = { | |
72 | .hwport = 0, | |
73 | .flags = 0, | |
74 | .ucon = 0x3c5, | |
75 | .ulcon = 0x03, | |
76 | .ufcon = 0x51, | |
afba7f91 | 77 | .clk_sel = S3C2410_UCON_CLKSEL3, |
1da177e4 LT |
78 | }, |
79 | [1] = { | |
80 | .hwport = 1, | |
81 | .flags = 0, | |
82 | .ucon = 0x3c5, | |
83 | .ulcon = 0x03, | |
84 | .ufcon = 0x00, | |
afba7f91 | 85 | .clk_sel = S3C2410_UCON_CLKSEL3, |
1da177e4 LT |
86 | }, |
87 | /* IR port */ | |
88 | [2] = { | |
89 | .hwport = 2, | |
90 | .uart_flags = UPF_CONS_FLOW, | |
91 | .ucon = 0x3c5, | |
92 | .ulcon = 0x43, | |
93 | .ufcon = 0x51, | |
afba7f91 | 94 | .clk_sel = S3C2410_UCON_CLKSEL3, |
1da177e4 LT |
95 | } |
96 | }; | |
97 | ||
e838ffc2 BD |
98 | /* framebuffer lcd controller information */ |
99 | ||
09fe75f6 | 100 | static struct s3c2410fb_display rx3715_lcdcfg __initdata = { |
f28ef573 KH |
101 | .lcdcon5 = S3C2410_LCDCON5_INVVLINE | |
102 | S3C2410_LCDCON5_FRM565 | | |
103 | S3C2410_LCDCON5_HWSWP, | |
e838ffc2 | 104 | |
1f411537 KH |
105 | .type = S3C2410_LCDCON1_TFT, |
106 | .width = 240, | |
107 | .height = 320, | |
108 | ||
69816699 | 109 | .pixclock = 260000, |
1f411537 KH |
110 | .xres = 240, |
111 | .yres = 320, | |
112 | .bpp = 16, | |
113 | .left_margin = 36, | |
114 | .right_margin = 36, | |
93d11f5a | 115 | .hsync_len = 8, |
5f20f69b KH |
116 | .upper_margin = 6, |
117 | .lower_margin = 7, | |
93d11f5a | 118 | .vsync_len = 3, |
09fe75f6 KH |
119 | }; |
120 | ||
121 | static struct s3c2410fb_mach_info rx3715_fb_info __initdata = { | |
122 | ||
123 | .displays = &rx3715_lcdcfg, | |
124 | .num_displays = 1, | |
125 | .default_display = 0, | |
126 | ||
e838ffc2 BD |
127 | .lpcsel = 0xf82, |
128 | ||
129 | .gpccon = 0xaa955699, | |
130 | .gpccon_mask = 0xffc003cc, | |
131 | .gpcup = 0x0000ffff, | |
132 | .gpcup_mask = 0xffffffff, | |
133 | ||
134 | .gpdcon = 0xaa95aaa1, | |
135 | .gpdcon_mask = 0xffc0fff0, | |
136 | .gpdup = 0x0000faff, | |
137 | .gpdup_mask = 0xffffffff, | |
e838ffc2 BD |
138 | }; |
139 | ||
2a3a1804 | 140 | static struct mtd_partition __initdata rx3715_nand_part[] = { |
272eb575 BD |
141 | [0] = { |
142 | .name = "Whole Flash", | |
143 | .offset = 0, | |
144 | .size = MTDPART_SIZ_FULL, | |
145 | .mask_flags = MTD_WRITEABLE, | |
146 | } | |
147 | }; | |
148 | ||
2a3a1804 | 149 | static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = { |
272eb575 BD |
150 | [0] = { |
151 | .name = "Internal", | |
152 | .nr_chips = 1, | |
153 | .nr_partitions = ARRAY_SIZE(rx3715_nand_part), | |
154 | .partitions = rx3715_nand_part, | |
155 | }, | |
156 | }; | |
157 | ||
2a3a1804 | 158 | static struct s3c2410_platform_nand __initdata rx3715_nand_info = { |
272eb575 BD |
159 | .tacls = 25, |
160 | .twrph0 = 50, | |
161 | .twrph1 = 15, | |
162 | .nr_sets = ARRAY_SIZE(rx3715_nand_sets), | |
163 | .sets = rx3715_nand_sets, | |
164 | }; | |
165 | ||
1da177e4 | 166 | static struct platform_device *rx3715_devices[] __initdata = { |
b813248c | 167 | &s3c_device_ohci, |
1da177e4 LT |
168 | &s3c_device_lcd, |
169 | &s3c_device_wdt, | |
3e1b776c | 170 | &s3c_device_i2c0, |
1da177e4 | 171 | &s3c_device_iis, |
272eb575 | 172 | &s3c_device_nand, |
1da177e4 LT |
173 | }; |
174 | ||
5fe10ab1 | 175 | static void __init rx3715_map_io(void) |
1da177e4 LT |
176 | { |
177 | s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); | |
178 | s3c24xx_init_clocks(16934000); | |
179 | s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); | |
1da177e4 LT |
180 | } |
181 | ||
98c672cf RK |
182 | /* H1940 and RX3715 need to reserve this for suspend */ |
183 | static void __init rx3715_reserve(void) | |
184 | { | |
8d717a52 RK |
185 | memblock_reserve(0x30003000, 0x1000); |
186 | memblock_reserve(0x30081000, 0x1000); | |
98c672cf RK |
187 | } |
188 | ||
5fe10ab1 | 189 | static void __init rx3715_init_irq(void) |
1da177e4 LT |
190 | { |
191 | s3c24xx_init_irq(); | |
192 | } | |
193 | ||
1da177e4 LT |
194 | static void __init rx3715_init_machine(void) |
195 | { | |
b1dfe1f1 | 196 | #ifdef CONFIG_PM_H1940 |
bbf6f280 | 197 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
b1dfe1f1 | 198 | #endif |
4e59c25d | 199 | s3c_pm_init(); |
bbf6f280 | 200 | |
2a3a1804 | 201 | s3c_nand_set_platdata(&rx3715_nand_info); |
09fe75f6 | 202 | s3c24xx_fb_set_platdata(&rx3715_fb_info); |
57e5171c | 203 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); |
1da177e4 | 204 | } |
e838ffc2 | 205 | |
1da177e4 | 206 | MACHINE_START(RX3715, "IPAQ-RX3715") |
afdd225d | 207 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
69d50710 | 208 | .atag_offset = 0x100, |
e9dea0c6 | 209 | .map_io = rx3715_map_io, |
98c672cf | 210 | .reserve = rx3715_reserve, |
e9dea0c6 RK |
211 | .init_irq = rx3715_init_irq, |
212 | .init_machine = rx3715_init_machine, | |
1da177e4 LT |
213 | .timer = &s3c24xx_timer, |
214 | MACHINE_END |