[linux-2.6-block.git] / arch / arm / mach-s3c2440 / mach-rx3715.c

/* linux/arch/arm/mach-s3c2440/mach-rx3715.c
 *
 * Copyright (c) 2003,2004 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.handhelds.org/projects/rx3715.html
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/tty.h>
#include <linux/console.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/serial.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <asm/plat-s3c/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-lcd.h>

#include <asm/arch/h1940.h>
#include <asm/plat-s3c/nand.h>
#include <asm/arch/fb.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>
#include <asm/plat-s3c24xx/pm.h>

static struct map_desc rx3715_iodesc[] __initdata = {
	/* dump ISA space somewhere unused */

	{
		.virtual	= (u32)S3C24XX_VA_ISA_WORD,
		.pfn		= __phys_to_pfn(S3C2410_CS3),
		.length		= SZ_1M,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
		.pfn		= __phys_to_pfn(S3C2410_CS3),
		.length		= SZ_1M,
		.type		= MT_DEVICE,
	},
};


static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
	[0] = {
		.name		= "fclk",
		.divisor	= 0,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};

static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = 0x3c5,
		.ulcon	     = 0x03,
		.ufcon	     = 0x51,
		.clocks	     = rx3715_serial_clocks,
		.clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = 0x3c5,
		.ulcon	     = 0x03,
		.ufcon	     = 0x00,
		.clocks	     = rx3715_serial_clocks,
		.clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
	},
	/* IR port */
	[2] = {
		.hwport	     = 2,
		.uart_flags  = UPF_CONS_FLOW,
		.ucon	     = 0x3c5,
		.ulcon	     = 0x43,
		.ufcon	     = 0x51,
		.clocks	     = rx3715_serial_clocks,
		.clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
	}
};

/* framebuffer lcd controller information */

static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
	.regs	= {
		.lcdcon1 =	S3C2410_LCDCON1_TFT16BPP | \
				S3C2410_LCDCON1_TFT | \
				S3C2410_LCDCON1_CLKVAL(0x0C),

		.lcdcon2 =	S3C2410_LCDCON2_VBPD(5) | \
				S3C2410_LCDCON2_LINEVAL(319) | \
				S3C2410_LCDCON2_VFPD(6) | \
				S3C2410_LCDCON2_VSPW(2),

		.lcdcon3 =	S3C2410_LCDCON3_HBPD(35) | \
				S3C2410_LCDCON3_HOZVAL(239) | \
				S3C2410_LCDCON3_HFPD(35),

		.lcdcon4 =	S3C2410_LCDCON4_MVAL(0) | \
				S3C2410_LCDCON4_HSPW(7),

		.lcdcon5 =	S3C2410_LCDCON5_INVVLINE |
				S3C2410_LCDCON5_FRM565 |
				S3C2410_LCDCON5_HWSWP,
	},

	.lpcsel =	0xf82,

	.gpccon =	0xaa955699,
	.gpccon_mask =	0xffc003cc,
	.gpcup =	0x0000ffff,
	.gpcup_mask =	0xffffffff,

	.gpdcon =	0xaa95aaa1,
	.gpdcon_mask =	0xffc0fff0,
	.gpdup =	0x0000faff,
	.gpdup_mask =	0xffffffff,

	.fixed_syncs =	1,
	.width  =	240,
	.height =	320,

	.xres	= {
		.min =		240,
		.max =		240,
		.defval =	240,
	},

	.yres	= {
		.max =		320,
		.min =		320,
		.defval	=	320,
	},

	.bpp	= {
		.min =		16,
		.max =		16,
		.defval =	16,
	},
};

static struct mtd_partition rx3715_nand_part[] = {
	[0] = {
		.name		= "Whole Flash",
		.offset		= 0,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= MTD_WRITEABLE,
	}
};

static struct s3c2410_nand_set rx3715_nand_sets[] = {
	[0] = {
		.name		= "Internal",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(rx3715_nand_part),
		.partitions	= rx3715_nand_part,
	},
};

static struct s3c2410_platform_nand rx3715_nand_info = {
	.tacls		= 25,
	.twrph0		= 50,
	.twrph1		= 15,
	.nr_sets	= ARRAY_SIZE(rx3715_nand_sets),
	.sets		= rx3715_nand_sets,
};

static struct platform_device *rx3715_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c,
	&s3c_device_iis,
	&s3c_device_nand,
};

static void __init rx3715_map_io(void)
{
	s3c_device_nand.dev.platform_data = &rx3715_nand_info;

	s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
	s3c24xx_init_clocks(16934000);
	s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
}

static void __init rx3715_init_irq(void)
{
	s3c24xx_init_irq();
}

static void __init rx3715_init_machine(void)
{
#ifdef CONFIG_PM_H1940
	memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
	s3c2410_pm_init();

	s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
	platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
}

MACHINE_START(RX3715, "IPAQ-RX3715")
	/* Maintainer: Ben Dooks <ben@fluff.org> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= rx3715_map_io,
	.init_irq	= rx3715_init_irq,
	.init_machine	= rx3715_init_machine,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-rx3715.c
1da177e4 LT	2	*
	3	* Copyright (c) 2003,2004 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.handhelds.org/projects/rx3715.html
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
1da177e4 LT	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/types.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/list.h>
	18	#include <linux/timer.h>
	19	#include <linux/init.h>
	20	#include <linux/tty.h>
	21	#include <linux/console.h>
333a42e1	22	#include <linux/sysdev.h>
d052d1be	23	#include <linux/platform_device.h>
1da177e4 LT	24	#include <linux/serial_core.h>
	25	#include <linux/serial.h>
	26
272eb575 BD	27	#include <linux/mtd/mtd.h>
	28	#include <linux/mtd/nand.h>
	29	#include <linux/mtd/nand_ecc.h>
	30	#include <linux/mtd/partitions.h>
	31
1da177e4 LT	32	#include <asm/mach/arch.h>
	33	#include <asm/mach/map.h>
	34	#include <asm/mach/irq.h>
	35
	36	#include <asm/hardware.h>
1da177e4 LT	37	#include <asm/io.h>
	38	#include <asm/irq.h>
	39	#include <asm/mach-types.h>
	40
531b617c	41	#include <asm/plat-s3c/regs-serial.h>
1da177e4	42	#include <asm/arch/regs-gpio.h>
e838ffc2 BD	43	#include <asm/arch/regs-lcd.h>
e838ffc2 BD	44
bbf6f280	45	#include <asm/arch/h1940.h>
531b617c	46	#include <asm/plat-s3c/nand.h>
e838ffc2	47	#include <asm/arch/fb.h>
1da177e4	48
a21765a7 BD	49	#include <asm/plat-s3c24xx/clock.h>
	50	#include <asm/plat-s3c24xx/devs.h>
	51	#include <asm/plat-s3c24xx/cpu.h>
	52	#include <asm/plat-s3c24xx/pm.h>
1da177e4 LT	53
	54	static struct map_desc rx3715_iodesc[] __initdata = {
	55	/* dump ISA space somewhere unused */
	56
ff6ffa82 BD	57	{
	58	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	59	.pfn = __phys_to_pfn(S3C2410_CS3),
	60	.length = SZ_1M,
	61	.type = MT_DEVICE,
	62	}, {
	63	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	64	.pfn = __phys_to_pfn(S3C2410_CS3),
	65	.length = SZ_1M,
	66	.type = MT_DEVICE,
	67	},
1da177e4 LT	68	};
	69
	70
	71	static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
	72	[0] = {
	73	.name = "fclk",
	74	.divisor = 0,
	75	.min_baud = 0,
	76	.max_baud = 0,
	77	}
	78	};
	79
	80	static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
	81	[0] = {
	82	.hwport = 0,
	83	.flags = 0,
	84	.ucon = 0x3c5,
	85	.ulcon = 0x03,
	86	.ufcon = 0x51,
	87	.clocks = rx3715_serial_clocks,
	88	.clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
	89	},
	90	[1] = {
	91	.hwport = 1,
	92	.flags = 0,
	93	.ucon = 0x3c5,
	94	.ulcon = 0x03,
	95	.ufcon = 0x00,
	96	.clocks = rx3715_serial_clocks,
	97	.clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
	98	},
	99	/* IR port */
	100	[2] = {
	101	.hwport = 2,
	102	.uart_flags = UPF_CONS_FLOW,
	103	.ucon = 0x3c5,
	104	.ulcon = 0x43,
	105	.ufcon = 0x51,
	106	.clocks = rx3715_serial_clocks,
	107	.clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
	108	}
	109	};
	110
e838ffc2 BD	111	/* framebuffer lcd controller information */
	112
	113	static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
	114	.regs = {
	115	.lcdcon1 = S3C2410_LCDCON1_TFT16BPP \| \
	116	S3C2410_LCDCON1_TFT \| \
	117	S3C2410_LCDCON1_CLKVAL(0x0C),
	118
	119	.lcdcon2 = S3C2410_LCDCON2_VBPD(5) \| \
	120	S3C2410_LCDCON2_LINEVAL(319) \| \
	121	S3C2410_LCDCON2_VFPD(6) \| \
	122	S3C2410_LCDCON2_VSPW(2),
	123
	124	.lcdcon3 = S3C2410_LCDCON3_HBPD(35) \| \
	125	S3C2410_LCDCON3_HOZVAL(239) \| \
	126	S3C2410_LCDCON3_HFPD(35),
	127
	128	.lcdcon4 = S3C2410_LCDCON4_MVAL(0) \| \
	129	S3C2410_LCDCON4_HSPW(7),
	130
	131	.lcdcon5 = S3C2410_LCDCON5_INVVLINE \|
	132	S3C2410_LCDCON5_FRM565 \|
	133	S3C2410_LCDCON5_HWSWP,
	134	},
	135
	136	.lpcsel = 0xf82,
	137
	138	.gpccon = 0xaa955699,
	139	.gpccon_mask = 0xffc003cc,
	140	.gpcup = 0x0000ffff,
	141	.gpcup_mask = 0xffffffff,
	142
	143	.gpdcon = 0xaa95aaa1,
	144	.gpdcon_mask = 0xffc0fff0,
	145	.gpdup = 0x0000faff,
	146	.gpdup_mask = 0xffffffff,
	147
	148	.fixed_syncs = 1,
	149	.width = 240,
	150	.height = 320,
	151
	152	.xres = {
	153	.min = 240,
	154	.max = 240,
	155	.defval = 240,
	156	},
	157
	158	.yres = {
	159	.max = 320,
	160	.min = 320,
	161	.defval = 320,
	162	},
	163
	164	.bpp = {
	165	.min = 16,
	166	.max = 16,
	167	.defval = 16,
	168	},
	169	};
	170
272eb575 BD	171	static struct mtd_partition rx3715_nand_part[] = {
	172	[0] = {
	173	.name = "Whole Flash",
	174	.offset = 0,
	175	.size = MTDPART_SIZ_FULL,
	176	.mask_flags = MTD_WRITEABLE,
	177	}
	178	};
	179
	180	static struct s3c2410_nand_set rx3715_nand_sets[] = {
	181	[0] = {
	182	.name = "Internal",
	183	.nr_chips = 1,
	184	.nr_partitions = ARRAY_SIZE(rx3715_nand_part),
	185	.partitions = rx3715_nand_part,
	186	},
	187	};
	188
	189	static struct s3c2410_platform_nand rx3715_nand_info = {
	190	.tacls = 25,
	191	.twrph0 = 50,
	192	.twrph1 = 15,
	193	.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
	194	.sets = rx3715_nand_sets,
	195	};
	196
1da177e4 LT	197	static struct platform_device *rx3715_devices[] __initdata = {
	198	&s3c_device_usb,
	199	&s3c_device_lcd,
	200	&s3c_device_wdt,
	201	&s3c_device_i2c,
	202	&s3c_device_iis,
272eb575	203	&s3c_device_nand,
1da177e4 LT	204	};
1da177e4 LT	205
5fe10ab1	206	static void __init rx3715_map_io(void)
1da177e4	207	{
272eb575 BD	208	s3c_device_nand.dev.platform_data = &rx3715_nand_info;
272eb575 BD	209
1da177e4 LT	210	s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
	211	s3c24xx_init_clocks(16934000);
	212	s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
1da177e4 LT	213	}
1da177e4 LT	214
5fe10ab1	215	static void __init rx3715_init_irq(void)
1da177e4 LT	216	{
	217	s3c24xx_init_irq();
	218	}
	219
1da177e4 LT	220	static void __init rx3715_init_machine(void)
1da177e4 LT	221	{
b1dfe1f1	222	#ifdef CONFIG_PM_H1940
bbf6f280	223	memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
b1dfe1f1	224	#endif
1da177e4	225	s3c2410_pm_init();
bbf6f280	226
e838ffc2	227	s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
57e5171c	228	platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
1da177e4	229	}
e838ffc2	230
1da177e4	231	MACHINE_START(RX3715, "IPAQ-RX3715")
e9dea0c6	232	/* Maintainer: Ben Dooks <ben@fluff.org> */
e9dea0c6 RK	233	.phys_io = S3C2410_PA_UART,
	234	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	235	.boot_params = S3C2410_SDRAM_PA + 0x100,
	236	.map_io = rx3715_map_io,
	237	.init_irq = rx3715_init_irq,
	238	.init_machine = rx3715_init_machine,
1da177e4 LT	239	.timer = &s3c24xx_timer,
1da177e4 LT	240	MACHINE_END