[linux-2.6-block.git] / arch / arm / mach-s3c2440 / mach-osiris.c

/* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
 * Copyright (c) 2005-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <linux/i2c/tps65010.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/osiris-map.h>
#include <mach/osiris-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

/* onboard perihperal map */

static struct map_desc osiris_iodesc[] __initdata = {
  /* ISA IO areas (may be over-written later) */

  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },

  /* CPLD control registers */

  {
	  .virtual	= (u32)OSIRIS_VA_CTRL0,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL1,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL2,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_IDREG,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	}
};

/* NAND Flash on Osiris board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition __initdata osiris_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Osiris has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.options	= NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.options	= NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
};

static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(OSIRIS_VA_CTRL0);
	tmp &= ~OSIRIS_CTRL0_NANDSEL;
	tmp |= slot;

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}

static struct s3c2410_platform_nand __initdata osiris_nand_info = {
	.tacls		= 25,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(osiris_nand_sets),
	.sets		= osiris_nand_sets,
	.select_chip	= osiris_nand_select,
};

/* PCMCIA control and configuration */

static struct resource osiris_pcmcia_resource[] = {
	[0] = {
		.start	= 0x0f000000,
		.end	= 0x0f100000,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 0x0c000000,
		.end	= 0x0c100000,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device osiris_pcmcia = {
	.name		= "osiris-pcmcia",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(osiris_pcmcia_resource),
	.resource	= osiris_pcmcia_resource,
};

/* Osiris power management device */

#ifdef CONFIG_PM
static unsigned char pm_osiris_ctrl0;

static int osiris_pm_suspend(void)
{
	unsigned int tmp;

	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;

	/* ensure correct NAND slot is selected on resume */
	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	        tmp |= 2;

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static void osiris_pm_resume(void)
{
	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
		__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);

	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);

	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
}

#else
#define osiris_pm_suspend NULL
#define osiris_pm_resume NULL
#endif

static struct syscore_ops osiris_pm_syscore_ops = {
	.suspend	= osiris_pm_suspend,
	.resume		= osiris_pm_resume,
};

/* Link for DVS driver to TPS65011 */

static void osiris_tps_release(struct device *dev)
{
	/* static device, do not need to release anything */
}

static struct platform_device osiris_tps_device = {
	.name	= "osiris-dvs",
	.id	= -1,
	.dev.release = osiris_tps_release,
};

static int osiris_tps_setup(struct i2c_client *client, void *context)
{
	osiris_tps_device.dev.parent = &client->dev;
	return platform_device_register(&osiris_tps_device);
}

static int osiris_tps_remove(struct i2c_client *client, void *context)
{
	platform_device_unregister(&osiris_tps_device);
	return 0;
}

static struct tps65010_board osiris_tps_board = {
	.base		= -1,	/* GPIO can go anywhere at the moment */
	.setup		= osiris_tps_setup,
	.teardown	= osiris_tps_remove,
};

/* I2C devices fitted. */

static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
		.platform_data = &osiris_tps_board,
	},
};

/* Standard Osiris devices */

static struct platform_device *osiris_devices[] __initdata = {
	&s3c_device_i2c0,
	&s3c_device_wdt,
	&s3c_device_nand,
	&osiris_pcmcia,
};

static struct clk *osiris_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	.refresh	= 7800, /* refresh period is 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static void __init osiris_map_io(void)
{
	unsigned long flags;

	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));

	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
		printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
		       __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
		osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	} else {
		/* write-protect line to the NAND */
		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
	}

	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */

	local_irq_save(flags);
	__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
	local_irq_restore(flags);
}

static void __init osiris_init(void)
{
	register_syscore_ops(&osiris_pm_syscore_ops);

	s3c_i2c0_set_platdata(NULL);
	s3c_nand_set_platdata(&osiris_nand_info);

	s3c_cpufreq_setboard(&osiris_cpufreq);

	i2c_register_board_info(0, osiris_i2c_devs,
				ARRAY_SIZE(osiris_i2c_devs));

	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
};

MACHINE_START(OSIRIS, "Simtec-OSIRIS")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.atag_offset	= 0x100,
	.map_io		= osiris_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= osiris_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-osiris.c
110d322b	2	*
ccae941e	3	* Copyright (c) 2005-2008 Simtec Electronics
110d322b BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
110d322b	19	#include <linux/device.h>
bb072c3c	20	#include <linux/syscore_ops.h>
b6d1f542	21	#include <linux/serial_core.h>
d96a9804	22	#include <linux/clk.h>
f3374221	23	#include <linux/i2c.h>
fced80c7	24	#include <linux/io.h>
110d322b	25
4fa084af BD	26	#include <linux/i2c/tps65010.h>
4fa084af BD	27
110d322b BD	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/irq.h>
	31
a09e64fb RK	32	#include <mach/osiris-map.h>
a09e64fb RK	33	#include <mach/osiris-cpld.h>
110d322b	34
a09e64fb	35	#include <mach/hardware.h>
110d322b BD	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
baf6b281	39	#include <plat/cpu-freq.h>
a2b7ba9c	40	#include <plat/regs-serial.h>
a09e64fb RK	41	#include <mach/regs-gpio.h>
	42	#include <mach/regs-mem.h>
	43	#include <mach/regs-lcd.h>
7926b5a3	44	#include <plat/nand.h>
3e1b776c	45	#include <plat/iic.h>
110d322b BD	46
	47	#include <linux/mtd/mtd.h>
	48	#include <linux/mtd/nand.h>
	49	#include <linux/mtd/nand_ecc.h>
	50	#include <linux/mtd/partitions.h>
	51
40b956f0	52	#include <plat/gpio-cfg.h>
d5120ae7	53	#include <plat/clock.h>
a2b7ba9c BD	54	#include <plat/devs.h>
a2b7ba9c BD	55	#include <plat/cpu.h>
110d322b	56
6cbdc8c5	57	/* onboard perihperal map */
110d322b BD	58
	59	static struct map_desc osiris_iodesc[] __initdata = {
	60	/* ISA IO areas (may be over-written later) */
	61
	62	{
	63	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	64	.pfn = __phys_to_pfn(S3C2410_CS5),
	65	.length = SZ_16M,
	66	.type = MT_DEVICE,
	67	}, {
	68	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	69	.pfn = __phys_to_pfn(S3C2410_CS5),
	70	.length = SZ_16M,
	71	.type = MT_DEVICE,
	72	},
	73
	74	/* CPLD control registers */
	75
	76	{
c362aecd BD	77	.virtual = (u32)OSIRIS_VA_CTRL0,
	78	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
	79	.length = SZ_16K,
	80	.type = MT_DEVICE,
	81	}, {
110d322b BD	82	.virtual = (u32)OSIRIS_VA_CTRL1,
	83	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
	84	.length = SZ_16K,
705630db	85	.type = MT_DEVICE,
110d322b BD	86	}, {
	87	.virtual = (u32)OSIRIS_VA_CTRL2,
	88	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
	89	.length = SZ_16K,
705630db	90	.type = MT_DEVICE,
c362aecd BD	91	}, {
	92	.virtual = (u32)OSIRIS_VA_IDREG,
	93	.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
	94	.length = SZ_16K,
	95	.type = MT_DEVICE,
110d322b BD	96	},
	97	};
	98
	99	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	100	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	101	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	102
66a9b49a	103	static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b BD	104	[0] = {
	105	.hwport = 0,
	106	.flags = 0,
	107	.ucon = UCON,
	108	.ulcon = ULCON,
	109	.ufcon = UFCON,
afba7f91	110	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
110d322b BD	111	},
110d322b BD	112	[1] = {
e2e5810f	113	.hwport = 1,
110d322b BD	114	.flags = 0,
	115	.ucon = UCON,
	116	.ulcon = ULCON,
	117	.ufcon = UFCON,
afba7f91	118	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
110d322b	119	},
ca7aa4de BD	120	[2] = {
	121	.hwport = 2,
	122	.flags = 0,
	123	.ucon = UCON,
	124	.ulcon = ULCON,
	125	.ufcon = UFCON,
afba7f91	126	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
ca7aa4de	127	}
110d322b BD	128	};
	129
	130	/* NAND Flash on Osiris board */
	131
	132	static int external_map[] = { 2 };
	133	static int chip0_map[] = { 0 };
	134	static int chip1_map[] = { 1 };
	135
2a3a1804	136	static struct mtd_partition __initdata osiris_default_nand_part[] = {
110d322b BD	137	[0] = {
	138	.name = "Boot Agent",
	139	.size = SZ_16K,
705630db	140	.offset = 0,
110d322b BD	141	},
	142	[1] = {
	143	.name = "/boot",
	144	.size = SZ_4M - SZ_16K,
	145	.offset = SZ_16K,
	146	},
	147	[2] = {
	148	.name = "user1",
	149	.offset = SZ_4M,
	150	.size = SZ_32M - SZ_4M,
	151	},
	152	[3] = {
	153	.name = "user2",
	154	.offset = SZ_32M,
	155	.size = MTDPART_SIZ_FULL,
	156	}
	157	};
	158
2a3a1804	159	static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
3c3e69cd BD	160	[0] = {
	161	.name = "Boot Agent",
	162	.size = SZ_128K,
	163	.offset = 0,
	164	},
	165	[1] = {
	166	.name = "/boot",
	167	.size = SZ_4M - SZ_128K,
	168	.offset = SZ_128K,
	169	},
	170	[2] = {
	171	.name = "user1",
	172	.offset = SZ_4M,
	173	.size = SZ_32M - SZ_4M,
	174	},
	175	[3] = {
	176	.name = "user2",
	177	.offset = SZ_32M,
	178	.size = MTDPART_SIZ_FULL,
	179	}
	180	};
	181
110d322b BD	182	/* the Osiris has 3 selectable slots for nand-flash, the two
	183	* on-board chip areas, as well as the external slot.
	184	*
	185	* Note, there is no current hot-plug support for the External
	186	* socket.
	187	*/
	188
2a3a1804	189	static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
110d322b BD	190	[1] = {
	191	.name = "External",
	192	.nr_chips = 1,
	193	.nr_map = external_map,
d9237380	194	.options = NAND_SCAN_SILENT_NODEV,
110d322b	195	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	196	.partitions = osiris_default_nand_part,
110d322b BD	197	},
	198	[0] = {
	199	.name = "chip0",
	200	.nr_chips = 1,
	201	.nr_map = chip0_map,
	202	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	203	.partitions = osiris_default_nand_part,
110d322b BD	204	},
	205	[2] = {
	206	.name = "chip1",
	207	.nr_chips = 1,
	208	.nr_map = chip1_map,
d9237380	209	.options = NAND_SCAN_SILENT_NODEV,
110d322b	210	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	211	.partitions = osiris_default_nand_part,
110d322b BD	212	},
	213	};
	214
	215	static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
	216	{
	217	unsigned int tmp;
	218
	219	slot = set->nr_map[slot] & 3;
	220
	221	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
	222	slot, set, set->nr_map);
	223
c362aecd BD	224	tmp = __raw_readb(OSIRIS_VA_CTRL0);
c362aecd BD	225	tmp &= ~OSIRIS_CTRL0_NANDSEL;
110d322b BD	226	tmp \|= slot;
110d322b BD	227
c362aecd	228	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
110d322b	229
c362aecd	230	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
110d322b BD	231	}
110d322b BD	232
2a3a1804	233	static struct s3c2410_platform_nand __initdata osiris_nand_info = {
110d322b BD	234	.tacls = 25,
	235	.twrph0 = 60,
	236	.twrph1 = 60,
	237	.nr_sets = ARRAY_SIZE(osiris_nand_sets),
	238	.sets = osiris_nand_sets,
	239	.select_chip = osiris_nand_select,
	240	};
	241
	242	/* PCMCIA control and configuration */
	243
	244	static struct resource osiris_pcmcia_resource[] = {
	245	[0] = {
	246	.start = 0x0f000000,
	247	.end = 0x0f100000,
	248	.flags = IORESOURCE_MEM,
	249	},
	250	[1] = {
	251	.start = 0x0c000000,
	252	.end = 0x0c100000,
	253	.flags = IORESOURCE_MEM,
	254	}
	255	};
	256
	257	static struct platform_device osiris_pcmcia = {
	258	.name = "osiris-pcmcia",
	259	.id = -1,
	260	.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
	261	.resource = osiris_pcmcia_resource,
	262	};
	263
5698bd28 BD	264	/* Osiris power management device */
	265
	266	#ifdef CONFIG_PM
	267	static unsigned char pm_osiris_ctrl0;
	268
bb072c3c	269	static int osiris_pm_suspend(void)
5698bd28	270	{
28047ece BD	271	unsigned int tmp;
28047ece BD	272
5698bd28	273	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
28047ece BD	274	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
	275
	276	/* ensure correct NAND slot is selected on resume */
	277	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	278	tmp \|= 2;
	279
	280	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
	281
4afcddae	282	/* ensure that an nRESET is not generated on resume. */
070276d5	283	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
40b956f0	284	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
4afcddae	285
5698bd28 BD	286	return 0;
	287	}
	288
bb072c3c	289	static void osiris_pm_resume(void)
5698bd28 BD	290	{
	291	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
	292	__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
	293
28047ece BD	294	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
28047ece BD	295
40b956f0	296	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
5698bd28 BD	297	}
	298
	299	#else
	300	#define osiris_pm_suspend NULL
	301	#define osiris_pm_resume NULL
	302	#endif
	303
bb072c3c	304	static struct syscore_ops osiris_pm_syscore_ops = {
5698bd28 BD	305	.suspend = osiris_pm_suspend,
	306	.resume = osiris_pm_resume,
	307	};
	308
4fa084af BD	309	/* Link for DVS driver to TPS65011 */
	310
	311	static void osiris_tps_release(struct device *dev)
	312	{
	313	/* static device, do not need to release anything */
	314	}
	315
	316	static struct platform_device osiris_tps_device = {
	317	.name = "osiris-dvs",
	318	.id = -1,
	319	.dev.release = osiris_tps_release,
	320	};
	321
	322	static int osiris_tps_setup(struct i2c_client client, void context)
	323	{
	324	osiris_tps_device.dev.parent = &client->dev;
	325	return platform_device_register(&osiris_tps_device);
	326	}
	327
	328	static int osiris_tps_remove(struct i2c_client client, void context)
	329	{
	330	platform_device_unregister(&osiris_tps_device);
	331	return 0;
	332	}
	333
	334	static struct tps65010_board osiris_tps_board = {
	335	.base = -1, /* GPIO can go anywhere at the moment */
	336	.setup = osiris_tps_setup,
	337	.teardown = osiris_tps_remove,
	338	};
	339
f3374221 BD	340	/* I2C devices fitted. */
	341
	342	static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	343	{
	344	I2C_BOARD_INFO("tps65011", 0x48),
	345	.irq = IRQ_EINT20,
4fa084af	346	.platform_data = &osiris_tps_board,
f3374221 BD	347	},
	348	};
	349
110d322b BD	350	/* Standard Osiris devices */
	351
	352	static struct platform_device *osiris_devices[] __initdata = {
3e1b776c	353	&s3c_device_i2c0,
55ba86bc	354	&s3c_device_wdt,
110d322b BD	355	&s3c_device_nand,
	356	&osiris_pcmcia,
	357	};
	358
2bc7509f	359	static struct clk *osiris_clocks[] __initdata = {
110d322b BD	360	&s3c24xx_dclk0,
	361	&s3c24xx_dclk1,
	362	&s3c24xx_clkout0,
	363	&s3c24xx_clkout1,
	364	&s3c24xx_uclk,
	365	};
	366
baf6b281 BD	367	static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	368	.refresh = 7800, /* refresh period is 7.8usec */
	369	.auto_io = 1,
	370	.need_io = 1,
	371	};
	372
da956fd6	373	static void __init osiris_map_io(void)
110d322b	374	{
da956fd6 BD	375	unsigned long flags;
da956fd6 BD	376
110d322b BD	377	/* initialise the clocks */
110d322b BD	378
d96a9804	379	s3c24xx_dclk0.parent = &clk_upll;
110d322b BD	380	s3c24xx_dclk0.rate = 1210001000;
110d322b BD	381
d96a9804	382	s3c24xx_dclk1.parent = &clk_upll;
110d322b BD	383	s3c24xx_dclk1.rate = 2410001000;
	384
	385	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	386	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	387
	388	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	389
ce89c206 BD	390	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
ce89c206 BD	391
110d322b BD	392	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	393	s3c24xx_init_clocks(0);
	394	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
110d322b	395
3c3e69cd BD	396	/* check for the newer revision boards with large page nand */
	397
	398	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
	399	printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
	400	__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
	401	osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
	402	osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	403	} else {
	404	/* write-protect line to the NAND */
070276d5	405	s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
3c3e69cd BD	406	}
3c3e69cd BD	407
110d322b	408	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6 BD	409
da956fd6 BD	410	local_irq_save(flags);
110d322b	411	__raw_writel(__raw_readl(S3C2410_BWSCON) \| S3C2410_BWSCON_ST1 \| S3C2410_BWSCON_ST2 \| S3C2410_BWSCON_ST3 \| S3C2410_BWSCON_ST4 \| S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6	412	local_irq_restore(flags);
110d322b BD	413	}
110d322b BD	414
57e5171c BD	415	static void __init osiris_init(void)
57e5171c BD	416	{
bb072c3c	417	register_syscore_ops(&osiris_pm_syscore_ops);
5698bd28	418
3e1b776c	419	s3c_i2c0_set_platdata(NULL);
2a3a1804	420	s3c_nand_set_platdata(&osiris_nand_info);
3e1b776c	421
baf6b281 BD	422	s3c_cpufreq_setboard(&osiris_cpufreq);
baf6b281 BD	423
f3374221 BD	424	i2c_register_board_info(0, osiris_i2c_devs,
	425	ARRAY_SIZE(osiris_i2c_devs));
	426
57e5171c BD	427	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
	428	};
	429
110d322b BD	430	MACHINE_START(OSIRIS, "Simtec-OSIRIS")
110d322b BD	431	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
69d50710	432	.atag_offset = 0x100,
110d322b BD	433	.map_io = osiris_map_io,
110d322b BD	434	.init_irq = s3c24xx_init_irq,
5698bd28	435	.init_machine = osiris_init,
110d322b BD	436	.timer = &s3c24xx_timer,
110d322b BD	437	MACHINE_END