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9db829f4 BD |
1 | /* linux/arch/arm/mach-s3c2410/mach-jive.c |
2 | * | |
3 | * Copyright 2007 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/sysdev.h> | |
c2c1708f | 20 | #include <linux/delay.h> |
9db829f4 BD |
21 | #include <linux/serial_core.h> |
22 | #include <linux/platform_device.h> | |
d10d8a5f | 23 | #include <linux/i2c.h> |
9db829f4 | 24 | |
c2c1708f BD |
25 | #include <video/ili9320.h> |
26 | ||
a2ed4065 BD |
27 | #include <linux/spi/spi.h> |
28 | ||
9db829f4 BD |
29 | #include <linux/mtd/mtd.h> |
30 | #include <linux/mtd/partitions.h> | |
31 | ||
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
34 | #include <asm/mach/irq.h> | |
35 | ||
36 | #include <asm/plat-s3c/regs-serial.h> | |
37 | #include <asm/plat-s3c/nand.h> | |
d10d8a5f | 38 | #include <asm/plat-s3c/iic.h> |
9db829f4 | 39 | |
a09e64fb RK |
40 | #include <mach/regs-power.h> |
41 | #include <mach/regs-gpio.h> | |
42 | #include <mach/regs-mem.h> | |
43 | #include <mach/regs-lcd.h> | |
44 | #include <mach/spi-gpio.h> | |
45 | #include <mach/fb.h> | |
9db829f4 BD |
46 | |
47 | #include <asm/mach-types.h> | |
48 | ||
49 | #include <linux/mtd/mtd.h> | |
50 | #include <linux/mtd/nand.h> | |
51 | #include <linux/mtd/nand_ecc.h> | |
52 | #include <linux/mtd/partitions.h> | |
53 | ||
54 | #include <asm/plat-s3c24xx/clock.h> | |
55 | #include <asm/plat-s3c24xx/devs.h> | |
56 | #include <asm/plat-s3c24xx/cpu.h> | |
57 | #include <asm/plat-s3c24xx/pm.h> | |
58 | #include <asm/plat-s3c24xx/udc.h> | |
59 | ||
60 | static struct map_desc jive_iodesc[] __initdata = { | |
61 | }; | |
62 | ||
63 | #define UCON S3C2410_UCON_DEFAULT | |
64 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | |
65 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
66 | ||
67 | static struct s3c2410_uartcfg jive_uartcfgs[] = { | |
68 | [0] = { | |
69 | .hwport = 0, | |
70 | .flags = 0, | |
71 | .ucon = UCON, | |
72 | .ulcon = ULCON, | |
73 | .ufcon = UFCON, | |
74 | }, | |
75 | [1] = { | |
76 | .hwport = 1, | |
77 | .flags = 0, | |
78 | .ucon = UCON, | |
79 | .ulcon = ULCON, | |
80 | .ufcon = UFCON, | |
81 | }, | |
82 | [2] = { | |
83 | .hwport = 2, | |
84 | .flags = 0, | |
85 | .ucon = UCON, | |
86 | .ulcon = ULCON, | |
87 | .ufcon = UFCON, | |
88 | } | |
89 | }; | |
90 | ||
91 | /* Jive flash assignment | |
92 | * | |
93 | * 0x00000000-0x00028000 : uboot | |
94 | * 0x00028000-0x0002c000 : uboot env | |
95 | * 0x0002c000-0x00030000 : spare | |
96 | * 0x00030000-0x00200000 : zimage A | |
97 | * 0x00200000-0x01600000 : cramfs A | |
98 | * 0x01600000-0x017d0000 : zimage B | |
99 | * 0x017d0000-0x02bd0000 : cramfs B | |
100 | * 0x02bd0000-0x03fd0000 : yaffs | |
101 | */ | |
102 | static struct mtd_partition jive_imageA_nand_part[] = { | |
103 | ||
104 | #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER | |
105 | /* Don't allow access to the bootloader from linux */ | |
106 | { | |
107 | .name = "uboot", | |
108 | .offset = 0, | |
109 | .size = (160 * SZ_1K), | |
110 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
111 | }, | |
112 | ||
113 | /* spare */ | |
114 | { | |
115 | .name = "spare", | |
116 | .offset = (176 * SZ_1K), | |
117 | .size = (16 * SZ_1K), | |
118 | }, | |
119 | #endif | |
120 | ||
121 | /* booted images */ | |
122 | { | |
123 | .name = "kernel (ro)", | |
124 | .offset = (192 * SZ_1K), | |
125 | .size = (SZ_2M) - (192 * SZ_1K), | |
126 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
127 | }, { | |
128 | .name = "root (ro)", | |
129 | .offset = (SZ_2M), | |
130 | .size = (20 * SZ_1M), | |
131 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
132 | }, | |
133 | ||
134 | /* yaffs */ | |
135 | { | |
136 | .name = "yaffs", | |
137 | .offset = (44 * SZ_1M), | |
138 | .size = (20 * SZ_1M), | |
139 | }, | |
140 | ||
141 | /* bootloader environment */ | |
142 | { | |
143 | .name = "env", | |
144 | .offset = (160 * SZ_1K), | |
145 | .size = (16 * SZ_1K), | |
146 | }, | |
147 | ||
148 | /* upgrade images */ | |
149 | { | |
150 | .name = "zimage", | |
151 | .offset = (22 * SZ_1M), | |
152 | .size = (2 * SZ_1M) - (192 * SZ_1K), | |
153 | }, { | |
154 | .name = "cramfs", | |
155 | .offset = (24 * SZ_1M) - (192*SZ_1K), | |
156 | .size = (20 * SZ_1M), | |
157 | }, | |
158 | }; | |
159 | ||
160 | static struct mtd_partition jive_imageB_nand_part[] = { | |
161 | ||
162 | #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER | |
163 | /* Don't allow access to the bootloader from linux */ | |
164 | { | |
165 | .name = "uboot", | |
166 | .offset = 0, | |
167 | .size = (160 * SZ_1K), | |
168 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
169 | }, | |
170 | ||
171 | /* spare */ | |
172 | { | |
173 | .name = "spare", | |
174 | .offset = (176 * SZ_1K), | |
175 | .size = (16 * SZ_1K), | |
176 | }, | |
177 | #endif | |
178 | ||
179 | /* booted images */ | |
180 | { | |
181 | .name = "kernel (ro)", | |
182 | .offset = (22 * SZ_1M), | |
183 | .size = (2 * SZ_1M) - (192 * SZ_1K), | |
184 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
185 | }, | |
186 | { | |
187 | .name = "root (ro)", | |
188 | .offset = (24 * SZ_1M) - (192 * SZ_1K), | |
189 | .size = (20 * SZ_1M), | |
190 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
191 | }, | |
192 | ||
193 | /* yaffs */ | |
194 | { | |
195 | .name = "yaffs", | |
196 | .offset = (44 * SZ_1M), | |
197 | .size = (20 * SZ_1M), | |
198 | }, | |
199 | ||
200 | /* bootloader environment */ | |
201 | { | |
202 | .name = "env", | |
203 | .offset = (160 * SZ_1K), | |
204 | .size = (16 * SZ_1K), | |
205 | }, | |
206 | ||
207 | /* upgrade images */ | |
208 | { | |
209 | .name = "zimage", | |
210 | .offset = (192 * SZ_1K), | |
211 | .size = (2 * SZ_1M) - (192 * SZ_1K), | |
212 | }, { | |
213 | .name = "cramfs", | |
214 | .offset = (2 * SZ_1M), | |
215 | .size = (20 * SZ_1M), | |
216 | }, | |
217 | }; | |
218 | ||
219 | static struct s3c2410_nand_set jive_nand_sets[] = { | |
220 | [0] = { | |
221 | .name = "flash", | |
222 | .nr_chips = 1, | |
223 | .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part), | |
224 | .partitions = jive_imageA_nand_part, | |
225 | }, | |
226 | }; | |
227 | ||
228 | static struct s3c2410_platform_nand jive_nand_info = { | |
229 | /* set taken from osiris nand timings, possibly still conservative */ | |
230 | .tacls = 30, | |
231 | .twrph0 = 55, | |
232 | .twrph1 = 40, | |
233 | .sets = jive_nand_sets, | |
234 | .nr_sets = ARRAY_SIZE(jive_nand_sets), | |
235 | }; | |
236 | ||
237 | static int __init jive_mtdset(char *options) | |
238 | { | |
239 | struct s3c2410_nand_set *nand = &jive_nand_sets[0]; | |
240 | unsigned long set; | |
241 | ||
242 | if (options == NULL || options[0] == '\0') | |
243 | return 0; | |
244 | ||
245 | if (strict_strtoul(options, 10, &set)) { | |
246 | printk(KERN_ERR "failed to parse mtdset=%s\n", options); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | switch (set) { | |
251 | case 1: | |
252 | nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part); | |
253 | nand->partitions = jive_imageB_nand_part; | |
254 | case 0: | |
255 | /* this is already setup in the nand info */ | |
256 | break; | |
257 | default: | |
258 | printk(KERN_ERR "Unknown mtd set %ld specified," | |
259 | "using default.", set); | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | /* parse the mtdset= option given to the kernel command line */ | |
266 | __setup("mtdset=", jive_mtdset); | |
267 | ||
0f99263c BD |
268 | /* LCD timing and setup */ |
269 | ||
270 | #define LCD_XRES (240) | |
271 | #define LCD_YRES (320) | |
272 | #define LCD_LEFT_MARGIN (12) | |
273 | #define LCD_RIGHT_MARGIN (12) | |
274 | #define LCD_LOWER_MARGIN (12) | |
275 | #define LCD_UPPER_MARGIN (12) | |
276 | #define LCD_VSYNC (2) | |
277 | #define LCD_HSYNC (2) | |
278 | ||
279 | #define LCD_REFRESH (60) | |
280 | ||
281 | #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN) | |
282 | #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN) | |
283 | ||
284 | struct s3c2410fb_display jive_vgg2432a4_display[] = { | |
285 | [0] = { | |
286 | .width = LCD_XRES, | |
287 | .height = LCD_YRES, | |
288 | .xres = LCD_XRES, | |
289 | .yres = LCD_YRES, | |
290 | .left_margin = LCD_LEFT_MARGIN, | |
291 | .right_margin = LCD_RIGHT_MARGIN, | |
292 | .upper_margin = LCD_UPPER_MARGIN, | |
293 | .lower_margin = LCD_LOWER_MARGIN, | |
294 | .hsync_len = LCD_HSYNC, | |
295 | .vsync_len = LCD_VSYNC, | |
296 | ||
297 | .pixclock = (1000000000000LL / | |
298 | (LCD_REFRESH * LCD_HTOT * LCD_VTOT)), | |
299 | ||
300 | .bpp = 16, | |
301 | .type = (S3C2410_LCDCON1_TFT16BPP | | |
302 | S3C2410_LCDCON1_TFT), | |
303 | ||
304 | .lcdcon5 = (S3C2410_LCDCON5_FRM565 | | |
305 | S3C2410_LCDCON5_INVVLINE | | |
306 | S3C2410_LCDCON5_INVVFRAME | | |
307 | S3C2410_LCDCON5_INVVDEN | | |
308 | S3C2410_LCDCON5_PWREN), | |
309 | }, | |
310 | }; | |
311 | ||
312 | /* todo - put into gpio header */ | |
313 | ||
314 | #define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2)) | |
315 | #define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2)) | |
316 | ||
317 | struct s3c2410fb_mach_info jive_lcd_config = { | |
318 | .displays = jive_vgg2432a4_display, | |
319 | .num_displays = ARRAY_SIZE(jive_vgg2432a4_display), | |
320 | .default_display = 0, | |
321 | ||
322 | /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN | |
323 | * and disable the pull down resistors on pins we are using for LCD | |
324 | * data. */ | |
325 | ||
326 | .gpcup = (0xf << 1) | (0x3f << 10), | |
327 | ||
328 | .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE | | |
329 | S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM | | |
330 | S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 | | |
331 | S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 | | |
332 | S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7), | |
333 | ||
334 | .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) | | |
335 | S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) | | |
336 | S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) | | |
337 | S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | | |
338 | S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), | |
339 | ||
340 | .gpdup = (0x3f << 2) | (0x3f << 10), | |
341 | ||
342 | .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | | |
343 | S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 | | |
344 | S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 | | |
345 | S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 | | |
346 | S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 | | |
347 | S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23), | |
348 | ||
349 | .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) | | |
350 | S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) | | |
351 | S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) | | |
352 | S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| | |
353 | S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| | |
354 | S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), | |
355 | }; | |
356 | ||
c2c1708f BD |
357 | /* ILI9320 support. */ |
358 | ||
359 | static void jive_lcm_reset(unsigned int set) | |
360 | { | |
361 | printk(KERN_DEBUG "%s(%d)\n", __func__, set); | |
362 | ||
363 | s3c2410_gpio_setpin(S3C2410_GPG13, set); | |
364 | s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); | |
365 | } | |
366 | ||
367 | #undef LCD_UPPER_MARGIN | |
368 | #define LCD_UPPER_MARGIN 2 | |
369 | ||
370 | static struct ili9320_platdata jive_lcm_config = { | |
371 | .hsize = LCD_XRES, | |
372 | .vsize = LCD_YRES, | |
373 | ||
374 | .reset = jive_lcm_reset, | |
375 | .suspend = ILI9320_SUSPEND_DEEP, | |
376 | ||
377 | .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR, | |
378 | .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) | | |
379 | ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)), | |
380 | .display3 = 0x0, | |
381 | .display4 = 0x0, | |
382 | .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 | | |
383 | ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF), | |
384 | .rgb_if2 = ILI9320_RGBIF2_DPL, | |
385 | .interface2 = 0x0, | |
386 | .interface3 = 0x3, | |
387 | .interface4 = (ILI9320_INTERFACE4_RTNE(16) | | |
388 | ILI9320_INTERFACE4_DIVE(1)), | |
389 | .interface5 = 0x0, | |
390 | .interface6 = 0x0, | |
391 | }; | |
392 | ||
a2ed4065 BD |
393 | /* LCD SPI support */ |
394 | ||
395 | static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) | |
396 | { | |
397 | s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1); | |
398 | } | |
399 | ||
400 | static struct s3c2410_spigpio_info jive_lcd_spi = { | |
d10d8a5f | 401 | .bus_num = 0, |
a2ed4065 BD |
402 | .pin_clk = S3C2410_GPG8, |
403 | .pin_mosi = S3C2410_GPB8, | |
404 | .chip_select = jive_lcd_spi_chipselect, | |
405 | }; | |
406 | ||
407 | static struct platform_device jive_device_lcdspi = { | |
408 | .name = "s3c24xx-spi-gpio", | |
409 | .id = 1, | |
410 | .num_resources = 0, | |
411 | .dev.platform_data = &jive_lcd_spi, | |
412 | }; | |
413 | ||
fd2de272 BD |
414 | /* WM8750 audio code SPI definition */ |
415 | ||
416 | static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) | |
417 | { | |
418 | s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1); | |
419 | } | |
420 | ||
421 | static struct s3c2410_spigpio_info jive_wm8750_spi = { | |
422 | .bus_num = 2, | |
423 | .pin_clk = S3C2410_GPB4, | |
424 | .pin_mosi = S3C2410_GPB9, | |
425 | .chip_select = jive_wm8750_chipselect, | |
426 | }; | |
427 | ||
428 | static struct platform_device jive_device_wm8750 = { | |
429 | .name = "s3c24xx-spi-gpio", | |
430 | .id = 2, | |
431 | .num_resources = 0, | |
432 | .dev.platform_data = &jive_wm8750_spi, | |
433 | }; | |
a2ed4065 | 434 | |
fd2de272 | 435 | /* JIVE SPI devices. */ |
a2ed4065 BD |
436 | |
437 | static struct spi_board_info __initdata jive_spi_devs[] = { | |
438 | [0] = { | |
439 | .modalias = "VGG2432A4", | |
440 | .bus_num = 1, | |
441 | .chip_select = 0, | |
442 | .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */ | |
443 | .max_speed_hz = 100000, | |
c2c1708f | 444 | .platform_data = &jive_lcm_config, |
fd2de272 BD |
445 | }, { |
446 | .modalias = "WM8750", | |
447 | .bus_num = 2, | |
448 | .chip_select = 0, | |
449 | .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */ | |
450 | .max_speed_hz = 100000, | |
a2ed4065 BD |
451 | }, |
452 | }; | |
453 | ||
d10d8a5f BD |
454 | /* I2C bus and device configuration. */ |
455 | ||
456 | static struct s3c2410_platform_i2c jive_i2c_cfg = { | |
457 | .max_freq = 80 * 1000, | |
458 | .bus_freq = 50 * 1000, | |
459 | .flags = S3C_IICFLG_FILTER, | |
460 | .sda_delay = 2, | |
461 | }; | |
462 | ||
463 | static struct i2c_board_info jive_i2c_devs[] = { | |
464 | [0] = { | |
465 | I2C_BOARD_INFO("lis302dl", 0x1c), | |
466 | .irq = IRQ_EINT14, | |
467 | }, | |
468 | }; | |
469 | ||
470 | /* The platform devices being used. */ | |
471 | ||
9db829f4 BD |
472 | static struct platform_device *jive_devices[] __initdata = { |
473 | &s3c_device_usb, | |
474 | &s3c_device_rtc, | |
475 | &s3c_device_wdt, | |
476 | &s3c_device_i2c, | |
0f99263c | 477 | &s3c_device_lcd, |
a2ed4065 | 478 | &jive_device_lcdspi, |
fd2de272 | 479 | &jive_device_wm8750, |
9db829f4 BD |
480 | &s3c_device_nand, |
481 | &s3c_device_usbgadget, | |
482 | }; | |
483 | ||
484 | static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { | |
485 | .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */ | |
486 | }; | |
487 | ||
488 | /* Jive power management device */ | |
489 | ||
490 | #ifdef CONFIG_PM | |
491 | static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) | |
492 | { | |
493 | /* Write the magic value u-boot uses to check for resume into | |
494 | * the INFORM0 register, and ensure INFORM1 is set to the | |
495 | * correct address to resume from. */ | |
496 | ||
497 | __raw_writel(0x2BED, S3C2412_INFORM0); | |
498 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static int jive_pm_resume(struct sys_device *sd) | |
504 | { | |
505 | __raw_writel(0x0, S3C2412_INFORM0); | |
506 | return 0; | |
507 | } | |
508 | ||
509 | #else | |
510 | #define jive_pm_suspend NULL | |
511 | #define jive_pm_resume NULL | |
512 | #endif | |
513 | ||
514 | static struct sysdev_class jive_pm_sysclass = { | |
515 | .name = "jive-pm", | |
516 | .suspend = jive_pm_suspend, | |
517 | .resume = jive_pm_resume, | |
518 | }; | |
519 | ||
520 | static struct sys_device jive_pm_sysdev = { | |
521 | .cls = &jive_pm_sysclass, | |
522 | }; | |
523 | ||
524 | static void __init jive_map_io(void) | |
525 | { | |
526 | s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); | |
527 | s3c24xx_init_clocks(12000000); | |
528 | s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); | |
529 | } | |
530 | ||
dd1086f4 BD |
531 | static void jive_power_off(void) |
532 | { | |
533 | printk(KERN_INFO "powering system down...\n"); | |
534 | ||
535 | s3c2410_gpio_setpin(S3C2410_GPC5, 1); | |
536 | s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT); | |
537 | } | |
538 | ||
9db829f4 BD |
539 | static void __init jive_machine_init(void) |
540 | { | |
541 | /* register system devices for managing low level suspend */ | |
542 | ||
543 | sysdev_class_register(&jive_pm_sysclass); | |
544 | sysdev_register(&jive_pm_sysdev); | |
545 | ||
54c272ac BD |
546 | /* write our sleep configurations for the IO. Pull down all unused |
547 | * IO, ensure that we have turned off all peripherals we do not | |
548 | * need, and configure the ones we do need. */ | |
549 | ||
550 | /* Port B sleep */ | |
551 | ||
552 | __raw_writel(S3C2412_SLPCON_IN(0) | | |
553 | S3C2412_SLPCON_PULL(1) | | |
554 | S3C2412_SLPCON_HIGH(2) | | |
555 | S3C2412_SLPCON_PULL(3) | | |
556 | S3C2412_SLPCON_PULL(4) | | |
557 | S3C2412_SLPCON_PULL(5) | | |
558 | S3C2412_SLPCON_PULL(6) | | |
559 | S3C2412_SLPCON_HIGH(7) | | |
560 | S3C2412_SLPCON_PULL(8) | | |
561 | S3C2412_SLPCON_PULL(9) | | |
562 | S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON); | |
563 | ||
564 | /* Port C sleep */ | |
565 | ||
566 | __raw_writel(S3C2412_SLPCON_PULL(0) | | |
567 | S3C2412_SLPCON_PULL(1) | | |
568 | S3C2412_SLPCON_PULL(2) | | |
569 | S3C2412_SLPCON_PULL(3) | | |
570 | S3C2412_SLPCON_PULL(4) | | |
571 | S3C2412_SLPCON_PULL(5) | | |
572 | S3C2412_SLPCON_LOW(6) | | |
573 | S3C2412_SLPCON_PULL(6) | | |
574 | S3C2412_SLPCON_PULL(7) | | |
575 | S3C2412_SLPCON_PULL(8) | | |
576 | S3C2412_SLPCON_PULL(9) | | |
577 | S3C2412_SLPCON_PULL(10) | | |
578 | S3C2412_SLPCON_PULL(11) | | |
579 | S3C2412_SLPCON_PULL(12) | | |
580 | S3C2412_SLPCON_PULL(13) | | |
581 | S3C2412_SLPCON_PULL(14) | | |
582 | S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON); | |
583 | ||
584 | /* Port D sleep */ | |
585 | ||
586 | __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON); | |
587 | ||
588 | /* Port F sleep */ | |
589 | ||
590 | __raw_writel(S3C2412_SLPCON_LOW(0) | | |
591 | S3C2412_SLPCON_LOW(1) | | |
592 | S3C2412_SLPCON_LOW(2) | | |
593 | S3C2412_SLPCON_EINT(3) | | |
594 | S3C2412_SLPCON_EINT(4) | | |
595 | S3C2412_SLPCON_EINT(5) | | |
596 | S3C2412_SLPCON_EINT(6) | | |
597 | S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON); | |
598 | ||
599 | /* Port G sleep */ | |
600 | ||
601 | __raw_writel(S3C2412_SLPCON_IN(0) | | |
602 | S3C2412_SLPCON_IN(1) | | |
603 | S3C2412_SLPCON_IN(2) | | |
604 | S3C2412_SLPCON_IN(3) | | |
605 | S3C2412_SLPCON_IN(4) | | |
606 | S3C2412_SLPCON_IN(5) | | |
607 | S3C2412_SLPCON_IN(6) | | |
608 | S3C2412_SLPCON_IN(7) | | |
609 | S3C2412_SLPCON_PULL(8) | | |
610 | S3C2412_SLPCON_PULL(9) | | |
611 | S3C2412_SLPCON_IN(10) | | |
612 | S3C2412_SLPCON_PULL(11) | | |
613 | S3C2412_SLPCON_PULL(12) | | |
614 | S3C2412_SLPCON_PULL(13) | | |
615 | S3C2412_SLPCON_IN(14) | | |
616 | S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON); | |
617 | ||
618 | /* Port H sleep */ | |
619 | ||
620 | __raw_writel(S3C2412_SLPCON_PULL(0) | | |
621 | S3C2412_SLPCON_PULL(1) | | |
622 | S3C2412_SLPCON_PULL(2) | | |
623 | S3C2412_SLPCON_PULL(3) | | |
624 | S3C2412_SLPCON_PULL(4) | | |
625 | S3C2412_SLPCON_PULL(5) | | |
626 | S3C2412_SLPCON_PULL(6) | | |
627 | S3C2412_SLPCON_IN(7) | | |
628 | S3C2412_SLPCON_IN(8) | | |
629 | S3C2412_SLPCON_PULL(9) | | |
630 | S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON); | |
631 | ||
632 | /* initialise the power management now we've setup everything. */ | |
633 | ||
9db829f4 BD |
634 | s3c2410_pm_init(); |
635 | ||
636 | s3c_device_nand.dev.platform_data = &jive_nand_info; | |
637 | ||
a2ed4065 BD |
638 | /* initialise the spi */ |
639 | ||
640 | s3c2410_gpio_setpin(S3C2410_GPG13, 0); | |
641 | s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); | |
642 | ||
643 | s3c2410_gpio_setpin(S3C2410_GPB7, 1); | |
644 | s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT); | |
645 | ||
646 | s3c2410_gpio_setpin(S3C2410_GPB6, 0); | |
647 | s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT); | |
648 | ||
649 | s3c2410_gpio_setpin(S3C2410_GPG8, 1); | |
650 | s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT); | |
651 | ||
fd2de272 BD |
652 | /* initialise the WM8750 spi */ |
653 | ||
654 | s3c2410_gpio_setpin(S3C2410_GPH10, 1); | |
655 | s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT); | |
656 | ||
9db829f4 BD |
657 | /* Turn off suspend on both USB ports, and switch the |
658 | * selectable USB port to USB device mode. */ | |
659 | ||
660 | s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | | |
661 | S3C2410_MISCCR_USBSUSPND0 | | |
662 | S3C2410_MISCCR_USBSUSPND1, 0x0); | |
663 | ||
664 | s3c24xx_udc_set_platdata(&jive_udc_cfg); | |
0f99263c | 665 | s3c24xx_fb_set_platdata(&jive_lcd_config); |
9db829f4 | 666 | |
a2ed4065 BD |
667 | spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs)); |
668 | ||
d10d8a5f BD |
669 | s3c_device_i2c.dev.platform_data = &jive_i2c_cfg; |
670 | i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs)); | |
671 | ||
dd1086f4 BD |
672 | pm_power_off = jive_power_off; |
673 | ||
9db829f4 BD |
674 | platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices)); |
675 | } | |
676 | ||
677 | MACHINE_START(JIVE, "JIVE") | |
678 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | |
679 | .phys_io = S3C2410_PA_UART, | |
680 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | |
681 | .boot_params = S3C2410_SDRAM_PA + 0x100, | |
682 | ||
683 | .init_irq = s3c24xx_init_irq, | |
684 | .map_io = jive_map_io, | |
685 | .init_machine = jive_machine_init, | |
686 | .timer = &s3c24xx_timer, | |
687 | MACHINE_END |