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1 | /* linux/arch/arm/mach-s3c2410/time.c |
2 | * | |
3 | * Copyright (C) 2003-2005 Simtec Electronics | |
4 | * Ben Dooks, <ben@simtec.co.uk> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <linux/config.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/err.h> | |
f8ce2547 | 27 | #include <linux/clk.h> |
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28 | |
29 | #include <asm/system.h> | |
30 | #include <asm/leds.h> | |
31 | #include <asm/mach-types.h> | |
32 | ||
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | #include <asm/arch/map.h> | |
36 | #include <asm/arch/regs-timer.h> | |
37 | #include <asm/arch/regs-irq.h> | |
38 | #include <asm/mach/time.h> | |
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39 | |
40 | #include "clock.h" | |
0eea3c0b | 41 | #include "cpu.h" |
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42 | |
43 | static unsigned long timer_startval; | |
44 | static unsigned long timer_usec_ticks; | |
45 | ||
46 | #define TIMER_USEC_SHIFT 16 | |
47 | ||
48 | /* we use the shifted arithmetic to work out the ratio of timer ticks | |
49 | * to usecs, as often the peripheral clock is not a nice even multiple | |
50 | * of 1MHz. | |
51 | * | |
52 | * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok | |
53 | * for the current HZ value of 200 without producing overflows. | |
54 | * | |
55 | * Original patch by Dimitry Andric, updated by Ben Dooks | |
56 | */ | |
57 | ||
58 | ||
59 | /* timer_mask_usec_ticks | |
60 | * | |
61 | * given a clock and divisor, make the value to pass into timer_ticks_to_usec | |
62 | * to scale the ticks into usecs | |
63 | */ | |
64 | ||
65 | static inline unsigned long | |
66 | timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) | |
67 | { | |
68 | unsigned long den = pclk / 1000; | |
69 | ||
70 | return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; | |
71 | } | |
72 | ||
73 | /* timer_ticks_to_usec | |
74 | * | |
75 | * convert timer ticks to usec. | |
76 | */ | |
77 | ||
78 | static inline unsigned long timer_ticks_to_usec(unsigned long ticks) | |
79 | { | |
80 | unsigned long res; | |
81 | ||
82 | res = ticks * timer_usec_ticks; | |
83 | res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ | |
84 | ||
85 | return res >> TIMER_USEC_SHIFT; | |
86 | } | |
87 | ||
88 | /*** | |
89 | * Returns microsecond since last clock interrupt. Note that interrupts | |
90 | * will have been disabled by do_gettimeoffset() | |
91 | * IRQs are disabled before entering here from do_gettimeofday() | |
92 | */ | |
93 | ||
94 | #define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) | |
95 | ||
96 | static unsigned long s3c2410_gettimeoffset (void) | |
97 | { | |
98 | unsigned long tdone; | |
99 | unsigned long irqpend; | |
100 | unsigned long tval; | |
101 | ||
102 | /* work out how many ticks have gone since last timer interrupt */ | |
103 | ||
104 | tval = __raw_readl(S3C2410_TCNTO(4)); | |
105 | tdone = timer_startval - tval; | |
106 | ||
107 | /* check to see if there is an interrupt pending */ | |
108 | ||
109 | irqpend = __raw_readl(S3C2410_SRCPND); | |
110 | if (irqpend & SRCPND_TIMER4) { | |
111 | /* re-read the timer, and try and fix up for the missed | |
112 | * interrupt. Note, the interrupt may go off before the | |
113 | * timer has re-loaded from wrapping. | |
114 | */ | |
115 | ||
116 | tval = __raw_readl(S3C2410_TCNTO(4)); | |
117 | tdone = timer_startval - tval; | |
118 | ||
119 | if (tval != 0) | |
120 | tdone += timer_startval; | |
121 | } | |
122 | ||
123 | return timer_ticks_to_usec(tdone); | |
124 | } | |
125 | ||
126 | ||
127 | /* | |
128 | * IRQ handler for the timer | |
129 | */ | |
130 | static irqreturn_t | |
131 | s3c2410_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
132 | { | |
133 | write_seqlock(&xtime_lock); | |
134 | timer_tick(regs); | |
135 | write_sequnlock(&xtime_lock); | |
136 | return IRQ_HANDLED; | |
137 | } | |
138 | ||
139 | static struct irqaction s3c2410_timer_irq = { | |
140 | .name = "S3C2410 Timer Tick", | |
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141 | .flags = SA_INTERRUPT | SA_TIMER, |
142 | .handler = s3c2410_timer_interrupt, | |
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143 | }; |
144 | ||
145 | /* | |
146 | * Set up timer interrupt, and return the current time in seconds. | |
147 | * | |
148 | * Currently we only use timer4, as it is the only timer which has no | |
149 | * other function that can be exploited externally | |
150 | */ | |
151 | static void s3c2410_timer_setup (void) | |
152 | { | |
153 | unsigned long tcon; | |
154 | unsigned long tcnt; | |
155 | unsigned long tcfg1; | |
156 | unsigned long tcfg0; | |
157 | ||
158 | tcnt = 0xffff; /* default value for tcnt */ | |
159 | ||
160 | /* read the current timer configuration bits */ | |
161 | ||
162 | tcon = __raw_readl(S3C2410_TCON); | |
163 | tcfg1 = __raw_readl(S3C2410_TCFG1); | |
164 | tcfg0 = __raw_readl(S3C2410_TCFG0); | |
165 | ||
166 | /* configure the system for whichever machine is in use */ | |
167 | ||
7efb833d | 168 | if (machine_is_bast() || machine_is_vr1000() || machine_is_anubis()) { |
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169 | /* timer is at 12MHz, scaler is 1 */ |
170 | timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); | |
171 | tcnt = 12000000 / HZ; | |
172 | ||
173 | tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; | |
174 | tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; | |
175 | } else { | |
176 | unsigned long pclk; | |
177 | struct clk *clk; | |
178 | ||
179 | /* for the h1940 (and others), we use the pclk from the core | |
180 | * to generate the timer values. since values around 50 to | |
181 | * 70MHz are not values we can directly generate the timer | |
182 | * value from, we need to pre-scale and divide before using it. | |
183 | * | |
184 | * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz | |
185 | * (8.45 ticks per usec) | |
186 | */ | |
187 | ||
188 | /* this is used as default if no other timer can be found */ | |
189 | ||
190 | clk = clk_get(NULL, "timers"); | |
191 | if (IS_ERR(clk)) | |
192 | panic("failed to get clock for system timer"); | |
193 | ||
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194 | clk_enable(clk); |
195 | ||
196 | pclk = clk_get_rate(clk); | |
197 | ||
198 | /* configure clock tick */ | |
199 | ||
200 | timer_usec_ticks = timer_mask_usec_ticks(6, pclk); | |
201 | ||
202 | tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; | |
203 | tcfg1 |= S3C2410_TCFG1_MUX4_DIV2; | |
204 | ||
205 | tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; | |
206 | tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT; | |
207 | ||
208 | tcnt = (pclk / 6) / HZ; | |
209 | } | |
210 | ||
211 | /* timers reload after counting zero, so reduce the count by 1 */ | |
212 | ||
213 | tcnt--; | |
214 | ||
215 | printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", | |
216 | tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); | |
217 | ||
218 | /* check to see if timer is within 16bit range... */ | |
219 | if (tcnt > 0xffff) { | |
220 | panic("setup_timer: HZ is too small, cannot configure timer!"); | |
221 | return; | |
222 | } | |
223 | ||
224 | __raw_writel(tcfg1, S3C2410_TCFG1); | |
225 | __raw_writel(tcfg0, S3C2410_TCFG0); | |
226 | ||
227 | timer_startval = tcnt; | |
228 | __raw_writel(tcnt, S3C2410_TCNTB(4)); | |
229 | ||
230 | /* ensure timer is stopped... */ | |
231 | ||
232 | tcon &= ~(7<<20); | |
233 | tcon |= S3C2410_TCON_T4RELOAD; | |
234 | tcon |= S3C2410_TCON_T4MANUALUPD; | |
235 | ||
236 | __raw_writel(tcon, S3C2410_TCON); | |
237 | __raw_writel(tcnt, S3C2410_TCNTB(4)); | |
238 | __raw_writel(tcnt, S3C2410_TCMPB(4)); | |
239 | ||
240 | /* start the timer running */ | |
241 | tcon |= S3C2410_TCON_T4START; | |
242 | tcon &= ~S3C2410_TCON_T4MANUALUPD; | |
243 | __raw_writel(tcon, S3C2410_TCON); | |
244 | } | |
245 | ||
246 | static void __init s3c2410_timer_init (void) | |
247 | { | |
248 | s3c2410_timer_setup(); | |
249 | setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); | |
250 | } | |
251 | ||
252 | struct sys_timer s3c24xx_timer = { | |
253 | .init = s3c2410_timer_init, | |
254 | .offset = s3c2410_gettimeoffset, | |
255 | .resume = s3c2410_timer_setup | |
256 | }; |