ARM: move CP15 definitions to separate header file
[linux-2.6-block.git] / arch / arm / mach-s3c2410 / s3c2410.c
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1da177e4
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1/* linux/arch/arm/mach-s3c2410/s3c2410.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
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11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
1ec7269f 19#include <linux/gpio.h>
e425382e 20#include <linux/clk.h>
4a858cfc 21#include <linux/device.h>
bb072c3c 22#include <linux/syscore_ops.h>
b6d1f542 23#include <linux/serial_core.h>
d052d1be 24#include <linux/platform_device.h>
fced80c7 25#include <linux/io.h>
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26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
a09e64fb 31#include <mach/hardware.h>
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32#include <asm/irq.h>
33
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34#include <plat/cpu-freq.h>
35
a09e64fb 36#include <mach/regs-clock.h>
a2b7ba9c 37#include <plat/regs-serial.h>
1da177e4 38
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39#include <plat/s3c2410.h>
40#include <plat/cpu.h>
41#include <plat/devs.h>
d5120ae7 42#include <plat/clock.h>
e24b864a 43#include <plat/pll.h>
bb072c3c 44#include <plat/pm.h>
b27b0727 45#include <plat/watchdog-reset.h>
1da177e4 46
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47#include <plat/gpio-core.h>
48#include <plat/gpio-cfg.h>
49#include <plat/gpio-cfg-helpers.h>
50
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51/* Initial IO mappings */
52
53static struct map_desc s3c2410_iodesc[] __initdata = {
1da177e4 54 IODESC_ENT(CLKPWR),
1da177e4 55 IODESC_ENT(TIMER),
62ee914e 56 IODESC_ENT(WATCHDOG),
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57};
58
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59/* our uart devices */
60
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61/* uart registration process */
62
63void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
64{
66a9b49a 65 s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no);
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66}
67
68/* s3c2410_map_io
69 *
70 * register the standard cpu IO areas, and any passed in from the
71 * machine specific initialisation.
72*/
73
74b265d4 74void __init s3c2410_map_io(void)
1da177e4 75{
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76 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
77 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
1ec7269f 78
1da177e4 79 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
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80}
81
e425382e 82void __init_or_cpufreq s3c2410_setup_clocks(void)
1da177e4 83{
e425382e 84 struct clk *xtal_clk;
1da177e4 85 unsigned long tmp;
e425382e 86 unsigned long xtal;
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87 unsigned long fclk;
88 unsigned long hclk;
89 unsigned long pclk;
90
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91 xtal_clk = clk_get(NULL, "xtal");
92 xtal = clk_get_rate(xtal_clk);
93 clk_put(xtal_clk);
94
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95 /* now we've got our machine bits initialised, work out what
96 * clocks we've got */
97
e24b864a 98 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
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99
100 tmp = __raw_readl(S3C2410_CLKDIVN);
101
102 /* work out clock scalings */
103
104 hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
105 pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
106
107 /* print brieft summary of clocks, etc */
108
109 printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
110 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
111
112 /* initialise the clocks here, to allow other things like the
113 * console to use them
114 */
115
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116 s3c24xx_setup_clocks(fclk, hclk, pclk);
117}
118
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119/* fake ARMCLK for use with cpufreq, etc. */
120
121static struct clk s3c2410_armclk = {
122 .name = "armclk",
123 .parent = &clk_f,
124 .id = -1,
125};
126
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127static struct clk_lookup s3c2410_clk_lookup[] = {
128 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
129 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
130};
131
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132void __init s3c2410_init_clocks(int xtal)
133{
134 s3c24xx_register_baseclocks(xtal);
135 s3c2410_setup_clocks();
99c13853 136 s3c2410_baseclk_add();
ad787595 137 s3c24xx_register_clock(&s3c2410_armclk);
0cfb26e1 138 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
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139}
140
4a858cfc 141struct bus_type s3c2410_subsys = {
af5ca3f4 142 .name = "s3c2410-core",
4a858cfc 143 .dev_name = "s3c2410-core",
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144};
145
f0176794 146/* Note, we would have liked to name this s3c2410-core, but we cannot
4a858cfc 147 * register two subsystems with the same name.
f0176794 148 */
4a858cfc 149struct bus_type s3c2410a_subsys = {
f0176794 150 .name = "s3c2410a-core",
4a858cfc 151 .dev_name = "s3c2410a-core",
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152};
153
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154static struct device s3c2410_dev = {
155 .bus = &s3c2410_subsys,
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156};
157
4a858cfc 158/* need to register the subsystem before we actually register the device, and
a341305e 159 * we also need to ensure that it has been initialised before any of the
6db3eee4 160 * drivers even try to use it (even if not on an s3c2410 based system)
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161 * as a driver which may support both 2410 and 2440 may try and use it.
162*/
163
164static int __init s3c2410_core_init(void)
165{
4a858cfc 166 return subsys_system_register(&s3c2410_subsys, NULL);
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167}
168
169core_initcall(s3c2410_core_init);
170
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171static int __init s3c2410a_core_init(void)
172{
4a858cfc 173 return subsys_system_register(&s3c2410a_subsys, NULL);
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174}
175
176core_initcall(s3c2410a_core_init);
177
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178int __init s3c2410_init(void)
179{
180 printk("S3C2410: Initialising architecture\n");
181
fb630b9f 182#ifdef CONFIG_PM
bb072c3c 183 register_syscore_ops(&s3c2410_pm_syscore_ops);
fb630b9f 184#endif
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185 register_syscore_ops(&s3c24xx_irq_syscore_ops);
186
4a858cfc 187 return device_register(&s3c2410_dev);
1da177e4 188}
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189
190int __init s3c2410a_init(void)
191{
4a858cfc 192 s3c2410_dev.bus = &s3c2410a_subsys;
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193 return s3c2410_init();
194}
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195
196void s3c2410_restart(char mode, const char *cmd)
197{
198 if (mode == 's') {
199 soft_restart(0);
200 }
201
202 arch_wdt_reset();
203
204 /* we'll take a jump through zero as a poor second */
205 soft_restart(0);
206}