Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/s3c2410.c |
2 | * | |
3 | * Copyright (c) 2003-2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://www.simtec.co.uk/products/EB2410ITX/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
e425382e | 19 | #include <linux/clk.h> |
a341305e | 20 | #include <linux/sysdev.h> |
b6d1f542 | 21 | #include <linux/serial_core.h> |
d052d1be | 22 | #include <linux/platform_device.h> |
fced80c7 | 23 | #include <linux/io.h> |
1da177e4 LT |
24 | |
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach/map.h> | |
27 | #include <asm/mach/irq.h> | |
28 | ||
a09e64fb | 29 | #include <mach/hardware.h> |
1da177e4 LT |
30 | #include <asm/irq.h> |
31 | ||
e425382e BD |
32 | #include <plat/cpu-freq.h> |
33 | ||
a09e64fb | 34 | #include <mach/regs-clock.h> |
a2b7ba9c | 35 | #include <plat/regs-serial.h> |
1da177e4 | 36 | |
a2b7ba9c BD |
37 | #include <plat/s3c2410.h> |
38 | #include <plat/cpu.h> | |
39 | #include <plat/devs.h> | |
d5120ae7 | 40 | #include <plat/clock.h> |
e24b864a | 41 | #include <plat/pll.h> |
1da177e4 LT |
42 | |
43 | /* Initial IO mappings */ | |
44 | ||
45 | static struct map_desc s3c2410_iodesc[] __initdata = { | |
1da177e4 | 46 | IODESC_ENT(CLKPWR), |
1da177e4 | 47 | IODESC_ENT(TIMER), |
62ee914e | 48 | IODESC_ENT(WATCHDOG), |
1da177e4 LT |
49 | }; |
50 | ||
1da177e4 LT |
51 | /* our uart devices */ |
52 | ||
1da177e4 LT |
53 | /* uart registration process */ |
54 | ||
55 | void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |
56 | { | |
66a9b49a | 57 | s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no); |
1da177e4 LT |
58 | } |
59 | ||
60 | /* s3c2410_map_io | |
61 | * | |
62 | * register the standard cpu IO areas, and any passed in from the | |
63 | * machine specific initialisation. | |
64 | */ | |
65 | ||
74b265d4 | 66 | void __init s3c2410_map_io(void) |
1da177e4 | 67 | { |
1da177e4 | 68 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); |
1da177e4 LT |
69 | } |
70 | ||
e425382e | 71 | void __init_or_cpufreq s3c2410_setup_clocks(void) |
1da177e4 | 72 | { |
e425382e | 73 | struct clk *xtal_clk; |
1da177e4 | 74 | unsigned long tmp; |
e425382e | 75 | unsigned long xtal; |
1da177e4 LT |
76 | unsigned long fclk; |
77 | unsigned long hclk; | |
78 | unsigned long pclk; | |
79 | ||
e425382e BD |
80 | xtal_clk = clk_get(NULL, "xtal"); |
81 | xtal = clk_get_rate(xtal_clk); | |
82 | clk_put(xtal_clk); | |
83 | ||
1da177e4 LT |
84 | /* now we've got our machine bits initialised, work out what |
85 | * clocks we've got */ | |
86 | ||
e24b864a | 87 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); |
1da177e4 LT |
88 | |
89 | tmp = __raw_readl(S3C2410_CLKDIVN); | |
90 | ||
91 | /* work out clock scalings */ | |
92 | ||
93 | hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); | |
94 | pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); | |
95 | ||
96 | /* print brieft summary of clocks, etc */ | |
97 | ||
98 | printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | |
99 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | |
100 | ||
101 | /* initialise the clocks here, to allow other things like the | |
102 | * console to use them | |
103 | */ | |
104 | ||
e425382e BD |
105 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
106 | } | |
107 | ||
108 | void __init s3c2410_init_clocks(int xtal) | |
109 | { | |
110 | s3c24xx_register_baseclocks(xtal); | |
111 | s3c2410_setup_clocks(); | |
99c13853 | 112 | s3c2410_baseclk_add(); |
1da177e4 LT |
113 | } |
114 | ||
a341305e | 115 | struct sysdev_class s3c2410_sysclass = { |
af5ca3f4 | 116 | .name = "s3c2410-core", |
a341305e BD |
117 | }; |
118 | ||
119 | static struct sys_device s3c2410_sysdev = { | |
120 | .cls = &s3c2410_sysclass, | |
121 | }; | |
122 | ||
123 | /* need to register class before we actually register the device, and | |
124 | * we also need to ensure that it has been initialised before any of the | |
6db3eee4 | 125 | * drivers even try to use it (even if not on an s3c2410 based system) |
a341305e BD |
126 | * as a driver which may support both 2410 and 2440 may try and use it. |
127 | */ | |
128 | ||
129 | static int __init s3c2410_core_init(void) | |
130 | { | |
131 | return sysdev_class_register(&s3c2410_sysclass); | |
132 | } | |
133 | ||
134 | core_initcall(s3c2410_core_init); | |
135 | ||
1da177e4 LT |
136 | int __init s3c2410_init(void) |
137 | { | |
138 | printk("S3C2410: Initialising architecture\n"); | |
139 | ||
a341305e | 140 | return sysdev_register(&s3c2410_sysdev); |
1da177e4 | 141 | } |