ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX
[linux-2.6-block.git] / arch / arm / mach-s3c2410 / pm.c
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1da177e4
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1/* linux/arch/arm/mach-s3c2410/pm.c
2 *
a21765a7 3 * Copyright (c) 2006 Simtec Electronics
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4 * Ben Dooks <ben@simtec.co.uk>
5 *
a21765a7 6 * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
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7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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21*/
22
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23#include <linux/init.h>
24#include <linux/suspend.h>
25#include <linux/errno.h>
26#include <linux/time.h>
4a858cfc 27#include <linux/device.h>
bb072c3c 28#include <linux/syscore_ops.h>
ec976d6e 29#include <linux/gpio.h>
fced80c7 30#include <linux/io.h>
1da177e4 31
a09e64fb 32#include <mach/hardware.h>
1da177e4 33
a21765a7 34#include <asm/mach-types.h>
1da177e4 35
a09e64fb
RK
36#include <mach/regs-gpio.h>
37#include <mach/h1940.h>
1da177e4 38
a2b7ba9c
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39#include <plat/cpu.h>
40#include <plat/pm.h>
1da177e4 41
a21765a7 42static void s3c2410_pm_prepare(void)
1da177e4 43{
a21765a7 44 /* ensure at least GSTATUS3 has the resume address */
1da177e4 45
ef30e144 46 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
1da177e4 47
6419711a
BD
48 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
49 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
1da177e4 50
a21765a7
BD
51 if (machine_is_h1940()) {
52 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
53 unsigned long ptr;
54 unsigned long calc = 0;
1da177e4 55
a21765a7 56 /* generate check for the bootloader to check on resume */
1da177e4 57
a21765a7
BD
58 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
59 calc += __raw_readl(base+ptr);
1da177e4 60
a21765a7 61 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
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62 }
63
0741b7d2 64 /* RX3715 and RX1950 use similar to H1940 code and the
a21765a7 65 * same offsets for resume and checksum pointers */
1da177e4 66
0741b7d2 67 if (machine_is_rx3715() || machine_is_rx1950()) {
a21765a7
BD
68 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
69 unsigned long ptr;
70 unsigned long calc = 0;
1da177e4 71
a21765a7 72 /* generate check for the bootloader to check on resume */
1da177e4 73
a21765a7
BD
74 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
75 calc += __raw_readl(base+ptr);
1da177e4 76
a21765a7 77 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
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78 }
79
a21765a7 80 if ( machine_is_aml_m5900() )
070276d5 81 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
1da177e4 82
192ff91f
VK
83 if (machine_is_rx1950()) {
84 /* According to S3C2442 user's manual, page 7-17,
85 * when the system is operating in NAND boot mode,
86 * the hardware pin configuration - EINT[23:21] –
87 * must be set as input for starting up after
88 * wakeup from sleep mode
89 */
90 s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
91 s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
92 s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
93 }
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94}
95
bb072c3c 96static void s3c2410_pm_resume(void)
1da177e4 97{
a21765a7 98 unsigned long tmp;
1da177e4 99
a21765a7 100 /* unset the return-from-sleep flag, to ensure reset */
1da177e4 101
a21765a7
BD
102 tmp = __raw_readl(S3C2410_GSTATUS2);
103 tmp &= S3C2410_GSTATUS2_OFFRESET;
104 __raw_writel(tmp, S3C2410_GSTATUS2);
1da177e4 105
a21765a7 106 if ( machine_is_aml_m5900() )
070276d5 107 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
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108}
109
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110struct syscore_ops s3c2410_pm_syscore_ops = {
111 .resume = s3c2410_pm_resume,
112};
113
4a858cfc 114static int s3c2410_pm_add(struct device *dev)
1da177e4 115{
a21765a7
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116 pm_cpu_prep = s3c2410_pm_prepare;
117 pm_cpu_sleep = s3c2410_cpu_suspend;
1da177e4 118
a21765a7 119 return 0;
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120}
121
a21765a7 122#if defined(CONFIG_CPU_S3C2410)
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123static struct subsys_interface s3c2410_pm_interface = {
124 .name = "s3c2410_pm",
125 .subsys = &s3c2410_subsys,
126 .add_dev = s3c2410_pm_add,
a21765a7 127};
1da177e4 128
a21765a7 129/* register ourselves */
1da177e4 130
a21765a7 131static int __init s3c2410_pm_drvinit(void)
1da177e4 132{
4a858cfc 133 return subsys_interface_register(&s3c2410_pm_interface);
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134}
135
a21765a7 136arch_initcall(s3c2410_pm_drvinit);
f0176794 137
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138static struct subsys_interface s3c2410a_pm_interface = {
139 .name = "s3c2410a_pm",
ea04018e 140 .subsys = &s3c2410a_subsys,
4a858cfc 141 .add_dev = s3c2410_pm_add,
f0176794
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142};
143
144static int __init s3c2410a_pm_drvinit(void)
145{
4a858cfc 146 return subsys_interface_register(&s3c2410a_pm_interface);
f0176794
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147}
148
149arch_initcall(s3c2410a_pm_drvinit);
a21765a7 150#endif
1da177e4 151
a21765a7 152#if defined(CONFIG_CPU_S3C2440)
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153static struct subsys_interface s3c2440_pm_interface = {
154 .name = "s3c2440_pm",
155 .subsys = &s3c2440_subsys,
156 .add_dev = s3c2410_pm_add,
a21765a7 157};
1da177e4 158
a21765a7 159static int __init s3c2440_pm_drvinit(void)
1da177e4 160{
4a858cfc 161 return subsys_interface_register(&s3c2440_pm_interface);
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162}
163
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164arch_initcall(s3c2440_pm_drvinit);
165#endif
1da177e4 166
a21765a7 167#if defined(CONFIG_CPU_S3C2442)
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168static struct subsys_interface s3c2442_pm_interface = {
169 .name = "s3c2442_pm",
170 .subsys = &s3c2442_subsys,
171 .add_dev = s3c2410_pm_add,
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172};
173
a21765a7 174static int __init s3c2442_pm_drvinit(void)
1da177e4 175{
4a858cfc 176 return subsys_interface_register(&s3c2442_pm_interface);
1da177e4 177}
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178
179arch_initcall(s3c2442_pm_drvinit);
180#endif