[linux-2.6-block.git] / arch / arm / mach-s3c2410 / mach-qt2410.c

/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
 *
 * Copyright (C) 2006 by OpenMoko, Inc.
 * Author: Harald Welte <laforge@openmoko.org>
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <mach/regs-gpio.h>
#include <mach/leds-gpio.h>
#include <plat/regs-serial.h>
#include <mach/fb.h>
#include <plat/nand.h>
#include <plat/udc.h>
#include <plat/iic.h>

#include <plat/common-smdk.h>
#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>

static struct map_desc qt2410_iodesc[] __initdata = {
	{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
};

#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	}
};

/* LCD driver info */

static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
	{
		/* Configuration for 640x480 SHARP LQ080V3DG01 */
		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
			   S3C2410_LCDCON5_INVVLINE |
			   S3C2410_LCDCON5_INVVFRAME |
			   S3C2410_LCDCON5_PWREN |
			   S3C2410_LCDCON5_HWSWP,

		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 40000, /* HCLK/4 */
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 44,
		.right_margin	= 116,
		.hsync_len	= 96,
		.upper_margin	= 19,
		.lower_margin	= 11,
		.vsync_len	= 15,
	},
	{
		/* Configuration for 480x640 toppoly TD028TTEC1 */
		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
			   S3C2410_LCDCON5_INVVLINE |
			   S3C2410_LCDCON5_INVVFRAME |
			   S3C2410_LCDCON5_PWREN |
			   S3C2410_LCDCON5_HWSWP,

		.type		= S3C2410_LCDCON1_TFT,
		.width		= 480,
		.height		= 640,
		.pixclock	= 40000, /* HCLK/4 */
		.xres		= 480,
		.yres		= 640,
		.bpp		= 16,
		.left_margin	= 8,
		.right_margin	= 24,
		.hsync_len	= 8,
		.upper_margin	= 2,
		.lower_margin	= 4,
		.vsync_len	= 2,
	},
	{
		/* Config for 240x320 LCD */
		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
			   S3C2410_LCDCON5_INVVLINE |
			   S3C2410_LCDCON5_INVVFRAME |
			   S3C2410_LCDCON5_PWREN |
			   S3C2410_LCDCON5_HWSWP,

		.type		= S3C2410_LCDCON1_TFT,
		.width		= 240,
		.height		= 320,
		.pixclock	= 100000, /* HCLK/10 */
		.xres		= 240,
		.yres		= 320,
		.bpp		= 16,
		.left_margin	= 13,
		.right_margin	= 8,
		.hsync_len	= 4,
		.upper_margin	= 2,
		.lower_margin	= 7,
		.vsync_len	= 4,
	},
};


static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
	.displays 	= qt2410_lcd_cfg,
	.num_displays 	= ARRAY_SIZE(qt2410_lcd_cfg),
	.default_display = 0,

	.lpcsel		= ((0xCE6) & ~7) | 1<<4,
};

/* CS8900 */

static struct resource qt2410_cs89x0_resources[] = {
	[0] = {
		.start	= 0x19000000,
		.end	= 0x19000000 + 16,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_EINT9,
		.end	= IRQ_EINT9,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device qt2410_cs89x0 = {
	.name		= "cirrus-cs89x0",
	.num_resources	= ARRAY_SIZE(qt2410_cs89x0_resources),
	.resource	= qt2410_cs89x0_resources,
};

/* LED */

static struct s3c24xx_led_platdata qt2410_pdata_led = {
	.gpio		= S3C2410_GPB(0),
	.flags		= S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
	.name		= "led",
	.def_trigger	= "timer",
};

static struct platform_device qt2410_led = {
	.name		= "s3c24xx_led",
	.id		= 0,
	.dev		= {
		.platform_data = &qt2410_pdata_led,
	},
};

/* SPI */

static struct spi_gpio_platform_data spi_gpio_cfg = {
	.sck		= S3C2410_GPG(7),
	.mosi		= S3C2410_GPG(6),
	.miso		= S3C2410_GPG(5),
};

static struct platform_device qt2410_spi = {
	.name		= "spi-gpio",
	.id		= 1,
	.dev.platform_data = &spi_gpio_cfg,
};

/* Board devices */

static struct platform_device *qt2410_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
	&s3c_device_iis,
	&s3c_device_sdi,
	&s3c_device_usbgadget,
	&qt2410_spi,
	&qt2410_cs89x0,
	&qt2410_led,
};

static struct mtd_partition __initdata qt2410_nand_part[] = {
	[0] = {
		.name	= "U-Boot",
		.size	= 0x30000,
		.offset	= 0,
	},
	[1] = {
		.name	= "U-Boot environment",
		.offset = 0x30000,
		.size	= 0x4000,
	},
	[2] = {
		.name	= "kernel",
		.offset = 0x34000,
		.size	= SZ_2M,
	},
	[3] = {
		.name	= "initrd",
		.offset	= 0x234000,
		.size	= SZ_4M,
	},
	[4] = {
		.name	= "jffs2",
		.offset = 0x634000,
		.size	= 0x39cc000,
	},
};

static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
	[0] = {
		.name		= "NAND",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(qt2410_nand_part),
		.partitions	= qt2410_nand_part,
	},
};

/* choose a set of timings which should suit most 512Mbit
 * chips and beyond.
 */

static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
	.tacls		= 20,
	.twrph0		= 60,
	.twrph1		= 20,
	.nr_sets	= ARRAY_SIZE(qt2410_nand_sets),
	.sets		= qt2410_nand_sets,
};

/* UDC */

static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
};

static char tft_type = 's';

static int __init qt2410_tft_setup(char *str)
{
	tft_type = str[0];
	return 1;
}

__setup("tft=", qt2410_tft_setup);

static void __init qt2410_map_io(void)
{
	s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
	s3c24xx_init_clocks(12*1000*1000);
	s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
}

static void __init qt2410_machine_init(void)
{
	s3c_nand_set_platdata(&qt2410_nand_info);

	switch (tft_type) {
	case 'p': /* production */
		qt2410_fb_info.default_display = 1;
		break;
	case 'b': /* big */
		qt2410_fb_info.default_display = 0;
		break;
	case 's': /* small */
	default:
		qt2410_fb_info.default_display = 2;
		break;
	}
	s3c24xx_fb_set_platdata(&qt2410_fb_info);

	s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
	s3c2410_gpio_setpin(S3C2410_GPB(0), 1);

	s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
	s3c_i2c0_set_platdata(NULL);

	WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
	gpio_direction_output(S3C2410_GPB(5), 1);

	platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
	s3c_pm_init();
}

MACHINE_START(QT2410, "QT2410")
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= qt2410_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= qt2410_machine_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
c6184e27 BD	1	/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
	2	*
	3	* Copyright (C) 2006 by OpenMoko, Inc.
	4	* Author: Harald Welte <laforge@openmoko.org>
	5	* All rights reserved.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/types.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/list.h>
	28	#include <linux/timer.h>
	29	#include <linux/init.h>
ec976d6e	30	#include <linux/gpio.h>
333a42e1	31	#include <linux/sysdev.h>
c6184e27 BD	32	#include <linux/platform_device.h>
c6184e27 BD	33	#include <linux/serial_core.h>
c6184e27	34	#include <linux/spi/spi.h>
aa353169	35	#include <linux/spi/spi_gpio.h>
fced80c7	36	#include <linux/io.h>
c6184e27 BD	37	#include <linux/mtd/mtd.h>
	38	#include <linux/mtd/nand.h>
	39	#include <linux/mtd/nand_ecc.h>
	40	#include <linux/mtd/partitions.h>
	41
	42	#include <asm/mach/arch.h>
	43	#include <asm/mach/map.h>
	44	#include <asm/mach/irq.h>
	45
a09e64fb	46	#include <mach/hardware.h>
c6184e27 BD	47	#include <asm/irq.h>
	48	#include <asm/mach-types.h>
	49
a09e64fb RK	50	#include <mach/regs-gpio.h>
a09e64fb RK	51	#include <mach/leds-gpio.h>
a2b7ba9c	52	#include <plat/regs-serial.h>
a09e64fb	53	#include <mach/fb.h>
7926b5a3	54	#include <plat/nand.h>
57bd4b91	55	#include <plat/udc.h>
3e1b776c	56	#include <plat/iic.h>
c6184e27	57
d5120ae7	58	#include <plat/common-smdk.h>
40b956f0	59	#include <plat/gpio-cfg.h>
a2b7ba9c BD	60	#include <plat/devs.h>
	61	#include <plat/cpu.h>
	62	#include <plat/pm.h>
c6184e27 BD	63
	64	static struct map_desc qt2410_iodesc[] __initdata = {
	65	{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
	66	};
	67
	68	#define UCON S3C2410_UCON_DEFAULT
	69	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	70	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	71
	72	static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
	73	[0] = {
	74	.hwport = 0,
	75	.flags = 0,
	76	.ucon = UCON,
	77	.ulcon = ULCON,
	78	.ufcon = UFCON,
	79	},
	80	[1] = {
	81	.hwport = 1,
	82	.flags = 0,
	83	.ucon = UCON,
	84	.ulcon = ULCON,
	85	.ufcon = UFCON,
	86	},
	87	[2] = {
	88	.hwport = 2,
	89	.flags = 0,
	90	.ucon = UCON,
	91	.ulcon = ULCON,
	92	.ufcon = UFCON,
	93	}
	94	};
	95
	96	/* LCD driver info */
	97
09fe75f6 KH	98	static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
	99	{
	100	/* Configuration for 640x480 SHARP LQ080V3DG01 */
f28ef573 KH	101	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	102	S3C2410_LCDCON5_INVVLINE \|
	103	S3C2410_LCDCON5_INVVFRAME \|
	104	S3C2410_LCDCON5_PWREN \|
	105	S3C2410_LCDCON5_HWSWP,
09fe75f6	106
1f411537	107	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	108	.width = 640,
	109	.height = 480,
	110
69816699	111	.pixclock = 40000, /* HCLK/4 */
09fe75f6 KH	112	.xres = 640,
	113	.yres = 480,
	114	.bpp = 16,
1f411537 KH	115	.left_margin = 44,
1f411537 KH	116	.right_margin = 116,
93d11f5a	117	.hsync_len = 96,
5f20f69b KH	118	.upper_margin = 19,
5f20f69b KH	119	.lower_margin = 11,
93d11f5a	120	.vsync_len = 15,
c6184e27	121	},
09fe75f6 KH	122	{
09fe75f6 KH	123	/* Configuration for 480x640 toppoly TD028TTEC1 */
f28ef573 KH	124	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	125	S3C2410_LCDCON5_INVVLINE \|
	126	S3C2410_LCDCON5_INVVFRAME \|
	127	S3C2410_LCDCON5_PWREN \|
	128	S3C2410_LCDCON5_HWSWP,
09fe75f6	129
1f411537	130	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	131	.width = 480,
09fe75f6 KH	132	.height = 640,
69816699	133	.pixclock = 40000, /* HCLK/4 */
09fe75f6 KH	134	.xres = 480,
	135	.yres = 640,
	136	.bpp = 16,
1f411537 KH	137	.left_margin = 8,
1f411537 KH	138	.right_margin = 24,
93d11f5a	139	.hsync_len = 8,
5f20f69b KH	140	.upper_margin = 2,
5f20f69b KH	141	.lower_margin = 4,
93d11f5a	142	.vsync_len = 2,
c6184e27	143	},
09fe75f6 KH	144	{
09fe75f6 KH	145	/* Config for 240x320 LCD */
f28ef573 KH	146	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	147	S3C2410_LCDCON5_INVVLINE \|
	148	S3C2410_LCDCON5_INVVFRAME \|
	149	S3C2410_LCDCON5_PWREN \|
	150	S3C2410_LCDCON5_HWSWP,
09fe75f6	151
1f411537	152	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	153	.width = 240,
09fe75f6 KH	154	.height = 320,
69816699	155	.pixclock = 100000, /* HCLK/10 */
09fe75f6 KH	156	.xres = 240,
	157	.yres = 320,
	158	.bpp = 16,
1f411537 KH	159	.left_margin = 13,
1f411537 KH	160	.right_margin = 8,
93d11f5a	161	.hsync_len = 4,
5f20f69b KH	162	.upper_margin = 2,
5f20f69b KH	163	.lower_margin = 7,
93d11f5a	164	.vsync_len = 4,
c6184e27 BD	165	},
	166	};
	167
c6184e27	168
09fe75f6 KH	169	static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
	170	.displays = qt2410_lcd_cfg,
	171	.num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
	172	.default_display = 0,
c6184e27 BD	173
c6184e27 BD	174	.lpcsel = ((0xCE6) & ~7) \| 1<<4,
c6184e27 BD	175	};
	176
	177	/* CS8900 */
	178
	179	static struct resource qt2410_cs89x0_resources[] = {
	180	[0] = {
	181	.start = 0x19000000,
	182	.end = 0x19000000 + 16,
	183	.flags = IORESOURCE_MEM,
	184	},
	185	[1] = {
	186	.start = IRQ_EINT9,
	187	.end = IRQ_EINT9,
	188	.flags = IORESOURCE_IRQ,
	189	},
	190	};
	191
	192	static struct platform_device qt2410_cs89x0 = {
	193	.name = "cirrus-cs89x0",
	194	.num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
	195	.resource = qt2410_cs89x0_resources,
	196	};
	197
	198	/* LED */
	199
	200	static struct s3c24xx_led_platdata qt2410_pdata_led = {
070276d5	201	.gpio = S3C2410_GPB(0),
c6184e27 BD	202	.flags = S3C24XX_LEDF_ACTLOW \| S3C24XX_LEDF_TRISTATE,
	203	.name = "led",
	204	.def_trigger = "timer",
	205	};
	206
	207	static struct platform_device qt2410_led = {
	208	.name = "s3c24xx_led",
	209	.id = 0,
	210	.dev = {
	211	.platform_data = &qt2410_pdata_led,
	212	},
	213	};
	214
	215	/* SPI */
	216
aa353169 PK	217	static struct spi_gpio_platform_data spi_gpio_cfg = {
	218	.sck = S3C2410_GPG(7),
	219	.mosi = S3C2410_GPG(6),
	220	.miso = S3C2410_GPG(5),
c6184e27 BD	221	};
c6184e27 BD	222
c6184e27	223	static struct platform_device qt2410_spi = {
aa353169 PK	224	.name = "spi-gpio",
	225	.id = 1,
	226	.dev.platform_data = &spi_gpio_cfg,
c6184e27 BD	227	};
	228
	229	/* Board devices */
	230
	231	static struct platform_device *qt2410_devices[] __initdata = {
b813248c	232	&s3c_device_ohci,
c6184e27 BD	233	&s3c_device_lcd,
c6184e27 BD	234	&s3c_device_wdt,
3e1b776c	235	&s3c_device_i2c0,
c6184e27 BD	236	&s3c_device_iis,
	237	&s3c_device_sdi,
	238	&s3c_device_usbgadget,
	239	&qt2410_spi,
	240	&qt2410_cs89x0,
	241	&qt2410_led,
	242	};
	243
2a3a1804	244	static struct mtd_partition __initdata qt2410_nand_part[] = {
c6184e27 BD	245	[0] = {
	246	.name = "U-Boot",
	247	.size = 0x30000,
	248	.offset = 0,
	249	},
	250	[1] = {
	251	.name = "U-Boot environment",
	252	.offset = 0x30000,
	253	.size = 0x4000,
	254	},
	255	[2] = {
	256	.name = "kernel",
	257	.offset = 0x34000,
	258	.size = SZ_2M,
	259	},
	260	[3] = {
	261	.name = "initrd",
	262	.offset = 0x234000,
	263	.size = SZ_4M,
	264	},
	265	[4] = {
	266	.name = "jffs2",
	267	.offset = 0x634000,
	268	.size = 0x39cc000,
	269	},
	270	};
	271
2a3a1804	272	static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
c6184e27 BD	273	[0] = {
	274	.name = "NAND",
	275	.nr_chips = 1,
	276	.nr_partitions = ARRAY_SIZE(qt2410_nand_part),
	277	.partitions = qt2410_nand_part,
	278	},
	279	};
	280
	281	/* choose a set of timings which should suit most 512Mbit
	282	* chips and beyond.
	283	*/
	284
2a3a1804	285	static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
c6184e27 BD	286	.tacls = 20,
	287	.twrph0 = 60,
	288	.twrph1 = 20,
	289	.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
	290	.sets = qt2410_nand_sets,
	291	};
	292
	293	/* UDC */
	294
	295	static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
	296	};
	297
	298	static char tft_type = 's';
	299
	300	static int __init qt2410_tft_setup(char *str)
	301	{
	302	tft_type = str[0];
	303	return 1;
	304	}
	305
	306	__setup("tft=", qt2410_tft_setup);
	307
	308	static void __init qt2410_map_io(void)
	309	{
	310	s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
	311	s3c24xx_init_clocks(1210001000);
	312	s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
c6184e27 BD	313	}
	314
	315	static void __init qt2410_machine_init(void)
	316	{
2a3a1804	317	s3c_nand_set_platdata(&qt2410_nand_info);
c6184e27 BD	318
	319	switch (tft_type) {
	320	case 'p': /* production */
09fe75f6	321	qt2410_fb_info.default_display = 1;
c6184e27 BD	322	break;
c6184e27 BD	323	case 'b': /* big */
09fe75f6	324	qt2410_fb_info.default_display = 0;
c6184e27 BD	325	break;
	326	case 's': /* small */
	327	default:
09fe75f6	328	qt2410_fb_info.default_display = 2;
c6184e27 BD	329	break;
c6184e27 BD	330	}
09fe75f6	331	s3c24xx_fb_set_platdata(&qt2410_fb_info);
c6184e27	332
40b956f0	333	s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
070276d5	334	s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
c6184e27 BD	335
c6184e27 BD	336	s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
3e1b776c	337	s3c_i2c0_set_platdata(NULL);
c6184e27	338
2d2e0c89 BD	339	WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
2d2e0c89 BD	340	gpio_direction_output(S3C2410_GPB(5), 1);
c6184e27	341
57e5171c	342	platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
4e59c25d	343	s3c_pm_init();
c6184e27 BD	344	}
	345
	346	MACHINE_START(QT2410, "QT2410")
c6184e27 BD	347	.boot_params = S3C2410_SDRAM_PA + 0x100,
	348	.map_io = qt2410_map_io,
	349	.init_irq = s3c24xx_init_irq,
	350	.init_machine = qt2410_machine_init,
	351	.timer = &s3c24xx_timer,
	352	MACHINE_END
	353
	354