[linux-2.6-block.git] / arch / arm / mach-realview / realview_pb11mp.c

/*
 *  linux/arch/arm/mach-realview/realview_pb11mp.c
 *
 *  Copyright (C) 2008 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/amba/mmci.h>
#include <linux/amba/pl022.h>
#include <linux/io.h>
#include <linux/platform_data/clk-realview.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_twd.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <mach/board-pb11mp.h>
#include <mach/irqs.h>

#include "core.h"

static struct map_desc realview_pb11mp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(REALVIEW_SYS_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_SYS_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {	/* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
		.virtual	= IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
		.length		= REALVIEW_TC11MP_PRIV_MEM_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_SCTL_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_SCTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	},
#ifdef CONFIG_DEBUG_LL
	{
		.virtual	= IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
#endif
};

static void __init realview_pb11mp_map_io(void)
{
	iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
}

static struct pl061_platform_data gpio0_plat_data = {
	.gpio_base	= 0,
};

static struct pl061_platform_data gpio1_plat_data = {
	.gpio_base	= 8,
};

static struct pl061_platform_data gpio2_plat_data = {
	.gpio_base	= 16,
};

static struct pl022_ssp_controller ssp0_plat_data = {
	.bus_id = 0,
	.enable_dma = 0,
	.num_chipselect = 1,
};

/*
 * RealView PB11MPCore AMBA devices
 */

#define GPIO2_IRQ		{ IRQ_PB11MP_GPIO2 }
#define GPIO3_IRQ		{ IRQ_PB11MP_GPIO3 }
#define AACI_IRQ		{ IRQ_TC11MP_AACI }
#define MMCI0_IRQ		{ IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
#define KMI0_IRQ		{ IRQ_TC11MP_KMI0 }
#define KMI1_IRQ		{ IRQ_TC11MP_KMI1 }
#define PB11MP_SMC_IRQ		{ }
#define MPMC_IRQ		{ }
#define PB11MP_CLCD_IRQ		{ IRQ_PB11MP_CLCD }
#define DMAC_IRQ		{ IRQ_PB11MP_DMAC }
#define SCTL_IRQ		{ }
#define PB11MP_WATCHDOG_IRQ	{ IRQ_PB11MP_WATCHDOG }
#define PB11MP_GPIO0_IRQ	{ IRQ_PB11MP_GPIO0 }
#define GPIO1_IRQ		{ IRQ_PB11MP_GPIO1 }
#define PB11MP_RTC_IRQ		{ IRQ_TC11MP_RTC }
#define SCI_IRQ			{ IRQ_PB11MP_SCI }
#define PB11MP_UART0_IRQ	{ IRQ_TC11MP_UART0 }
#define PB11MP_UART1_IRQ	{ IRQ_TC11MP_UART1 }
#define PB11MP_UART2_IRQ	{ IRQ_PB11MP_UART2 }
#define PB11MP_UART3_IRQ	{ IRQ_PB11MP_UART3 }
#define PB11MP_SSP_IRQ		{ IRQ_PB11MP_SSP }

/* FPGA Primecells */
APB_DEVICE(aaci,	"fpga:aaci",	AACI,		NULL);
APB_DEVICE(mmc0,	"fpga:mmc0",	MMCI0,		&realview_mmc0_plat_data);
APB_DEVICE(kmi0,	"fpga:kmi0",	KMI0,		NULL);
APB_DEVICE(kmi1,	"fpga:kmi1",	KMI1,		NULL);
APB_DEVICE(uart3,	"fpga:uart3",	PB11MP_UART3,	NULL);

/* DevChip Primecells */
AHB_DEVICE(smc,		"dev:smc",	PB11MP_SMC,	NULL);
AHB_DEVICE(sctl,	"dev:sctl",	SCTL,		NULL);
APB_DEVICE(wdog,	"dev:wdog",	PB11MP_WATCHDOG, NULL);
APB_DEVICE(gpio0,	"dev:gpio0",	PB11MP_GPIO0,	&gpio0_plat_data);
APB_DEVICE(gpio1,	"dev:gpio1",	GPIO1,		&gpio1_plat_data);
APB_DEVICE(gpio2,	"dev:gpio2",	GPIO2,		&gpio2_plat_data);
APB_DEVICE(rtc,		"dev:rtc",	PB11MP_RTC,	NULL);
APB_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
APB_DEVICE(uart0,	"dev:uart0",	PB11MP_UART0,	NULL);
APB_DEVICE(uart1,	"dev:uart1",	PB11MP_UART1,	NULL);
APB_DEVICE(uart2,	"dev:uart2",	PB11MP_UART2,	NULL);
APB_DEVICE(ssp0,	"dev:ssp0",	PB11MP_SSP,	&ssp0_plat_data);

/* Primecells on the NEC ISSP chip */
AHB_DEVICE(clcd,	"issp:clcd",	PB11MP_CLCD,	&clcd_plat_data);
AHB_DEVICE(dmac,	"issp:dmac",	DMAC,		NULL);

static struct amba_device *amba_devs[] __initdata = {
	&dmac_device,
	&uart0_device,
	&uart1_device,
	&uart2_device,
	&uart3_device,
	&smc_device,
	&clcd_device,
	&sctl_device,
	&wdog_device,
	&gpio0_device,
	&gpio1_device,
	&gpio2_device,
	&rtc_device,
	&sci0_device,
	&ssp0_device,
	&aaci_device,
	&mmc0_device,
	&kmi0_device,
	&kmi1_device,
};

/*
 * RealView PB11MPCore platform devices
 */
static struct resource realview_pb11mp_flash_resource[] = {
	[0] = {
		.start		= REALVIEW_PB11MP_FLASH0_BASE,
		.end		= REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= REALVIEW_PB11MP_FLASH1_BASE,
		.end		= REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct resource realview_pb11mp_smsc911x_resources[] = {
	[0] = {
		.start		= REALVIEW_PB11MP_ETH_BASE,
		.end		= REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= IRQ_TC11MP_ETH,
		.end		= IRQ_TC11MP_ETH,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct resource realview_pb11mp_isp1761_resources[] = {
	[0] = {
		.start		= REALVIEW_PB11MP_USB_BASE,
		.end		= REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= IRQ_TC11MP_USB,
		.end		= IRQ_TC11MP_USB,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct resource pmu_resources[] = {
	[0] = {
		.start		= IRQ_TC11MP_PMU_CPU0,
		.end		= IRQ_TC11MP_PMU_CPU0,
		.flags		= IORESOURCE_IRQ,
	},
	[1] = {
		.start		= IRQ_TC11MP_PMU_CPU1,
		.end		= IRQ_TC11MP_PMU_CPU1,
		.flags		= IORESOURCE_IRQ,
	},
	[2] = {
		.start		= IRQ_TC11MP_PMU_CPU2,
		.end		= IRQ_TC11MP_PMU_CPU2,
		.flags		= IORESOURCE_IRQ,
	},
	[3] = {
		.start		= IRQ_TC11MP_PMU_CPU3,
		.end		= IRQ_TC11MP_PMU_CPU3,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device pmu_device = {
	.name			= "arm-pmu",
	.id			= ARM_PMU_DEVICE_CPU,
	.num_resources		= ARRAY_SIZE(pmu_resources),
	.resource		= pmu_resources,
};

static void __init gic_init_irq(void)
{
	unsigned int pldctrl;

	/* new irq mode with no DCC */
	writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
	pldctrl = readl(__io_address(REALVIEW_SYS_BASE)	+ REALVIEW_PB11MP_SYS_PLD_CTRL1);
	pldctrl |= 2 << 22;
	writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
	writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));

	/* ARM11MPCore test chip GIC, primary */
	gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
		 __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));

	/* board GIC, secondary */
	gic_init(1, IRQ_PB11MP_GIC_START,
		 __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
		 __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
	gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
}

#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
			      REALVIEW_TC11MP_TWD_BASE,
			      IRQ_LOCALTIMER);

static void __init realview_pb11mp_twd_init(void)
{
	int err = twd_local_timer_register(&twd_local_timer);
	if (err)
		pr_err("twd_local_timer_register failed %d\n", err);
}
#else
#define realview_pb11mp_twd_init()	do {} while(0)
#endif

static void __init realview_pb11mp_timer_init(void)
{
	timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
	timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
	timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
	timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;

	realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
	realview_timer_init(IRQ_TC11MP_TIMER0_1);
	realview_pb11mp_twd_init();
}

static struct sys_timer realview_pb11mp_timer = {
	.init		= realview_pb11mp_timer_init,
};

static void realview_pb11mp_restart(char mode, const char *cmd)
{
	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);

	/*
	 * To reset, we hit the on-board reset register
	 * in the system FPGA
	 */
	__raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
	__raw_writel(0x0000, reset_ctrl);
	__raw_writel(0x0004, reset_ctrl);
	dsb();
}

static void __init realview_pb11mp_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
	 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
	l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
#endif

	realview_flash_register(realview_pb11mp_flash_resource,
				ARRAY_SIZE(realview_pb11mp_flash_resource));
	realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	platform_device_register(&realview_cf_device);
	realview_usb_register(realview_pb11mp_isp1761_resources);
	platform_device_register(&pmu_device);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
}

MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.atag_offset	= 0x100,
	.fixup		= realview_fixup,
	.map_io		= realview_pb11mp_map_io,
	.init_early	= realview_init_early,
	.init_irq	= gic_init_irq,
	.timer		= &realview_pb11mp_timer,
	.handle_irq	= gic_handle_irq,
	.init_machine	= realview_pb11mp_init,
#ifdef CONFIG_ZONE_DMA
	.dma_zone_size	= SZ_256M,
#endif
	.restart	= realview_pb11mp_restart,
MACHINE_END
Commit	Line	Data
a9b67db5 BB	1	/*
	2	* linux/arch/arm/mach-realview/realview_pb11mp.c
	3	*
	4	* Copyright (C) 2008 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/init.h>
	23	#include <linux/platform_device.h>
edbaa603	24	#include <linux/device.h>
a9b67db5	25	#include <linux/amba/bus.h>
eb7fffa3	26	#include <linux/amba/pl061.h>
6ef297f8	27	#include <linux/amba/mmci.h>
d6ada860	28	#include <linux/amba/pl022.h>
fced80c7	29	#include <linux/io.h>
f9a6aa43	30	#include <linux/platform_data/clk-realview.h>
a9b67db5	31
a09e64fb	32	#include <mach/hardware.h>
a9b67db5 BB	33	#include <asm/irq.h>
	34	#include <asm/leds.h>
	35	#include <asm/mach-types.h>
f417cbad	36	#include <asm/pmu.h>
cc9897df	37	#include <asm/pgtable.h>
a9b67db5	38	#include <asm/hardware/gic.h>
a9b67db5	39	#include <asm/hardware/cache-l2x0.h>
7c380f27	40	#include <asm/smp_twd.h>
a9b67db5 BB	41
	42	#include <asm/mach/arch.h>
	43	#include <asm/mach/flash.h>
	44	#include <asm/mach/map.h>
a9b67db5 BB	45	#include <asm/mach/time.h>
a9b67db5 BB	46
a09e64fb RK	47	#include <mach/board-pb11mp.h>
a09e64fb RK	48	#include <mach/irqs.h>
a9b67db5 BB	49
a9b67db5 BB	50	#include "core.h"
a9b67db5 BB	51
	52	static struct map_desc realview_pb11mp_io_desc[] __initdata = {
	53	{
	54	.virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
	55	.pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
	56	.length = SZ_4K,
	57	.type = MT_DEVICE,
	58	}, {
	59	.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
	60	.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
	61	.length = SZ_4K,
	62	.type = MT_DEVICE,
	63	}, {
	64	.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
	65	.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
	66	.length = SZ_4K,
	67	.type = MT_DEVICE,
34ae6c96 MZ	68	}, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
	69	.virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
	70	.pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
	71	.length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
a9b67db5 BB	72	.type = MT_DEVICE,
	73	}, {
	74	.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
	75	.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
	76	.length = SZ_4K,
	77	.type = MT_DEVICE,
	78	}, {
	79	.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
	80	.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
	81	.length = SZ_4K,
	82	.type = MT_DEVICE,
	83	}, {
	84	.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
	85	.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
	86	.length = SZ_4K,
	87	.type = MT_DEVICE,
	88	}, {
	89	.virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
	90	.pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
	91	.length = SZ_8K,
	92	.type = MT_DEVICE,
	93	},
	94	#ifdef CONFIG_DEBUG_LL
	95	{
	96	.virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
	97	.pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
	98	.length = SZ_4K,
	99	.type = MT_DEVICE,
	100	},
	101	#endif
	102	};
	103
	104	static void __init realview_pb11mp_map_io(void)
	105	{
	106	iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
	107	}
	108
eb7fffa3 RK	109	static struct pl061_platform_data gpio0_plat_data = {
eb7fffa3 RK	110	.gpio_base = 0,
eb7fffa3 RK	111	};
	112
	113	static struct pl061_platform_data gpio1_plat_data = {
	114	.gpio_base = 8,
eb7fffa3 RK	115	};
	116
	117	static struct pl061_platform_data gpio2_plat_data = {
	118	.gpio_base = 16,
eb7fffa3 RK	119	};
eb7fffa3 RK	120
d6ada860 LW	121	static struct pl022_ssp_controller ssp0_plat_data = {
	122	.bus_id = 0,
	123	.enable_dma = 0,
	124	.num_chipselect = 1,
	125	};
	126
a9b67db5 BB	127	/*
	128	* RealView PB11MPCore AMBA devices
	129	*/
	130
0dada61a RK	131	#define GPIO2_IRQ { IRQ_PB11MP_GPIO2 }
	132	#define GPIO3_IRQ { IRQ_PB11MP_GPIO3 }
	133	#define AACI_IRQ { IRQ_TC11MP_AACI }
a9b67db5	134	#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
0dada61a RK	135	#define KMI0_IRQ { IRQ_TC11MP_KMI0 }
	136	#define KMI1_IRQ { IRQ_TC11MP_KMI1 }
	137	#define PB11MP_SMC_IRQ { }
	138	#define MPMC_IRQ { }
	139	#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD }
	140	#define DMAC_IRQ { IRQ_PB11MP_DMAC }
	141	#define SCTL_IRQ { }
	142	#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG }
	143	#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0 }
	144	#define GPIO1_IRQ { IRQ_PB11MP_GPIO1 }
	145	#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC }
	146	#define SCI_IRQ { IRQ_PB11MP_SCI }
	147	#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0 }
	148	#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1 }
	149	#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2 }
	150	#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3 }
	151	#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP }
a9b67db5 BB	152
a9b67db5 BB	153	/* FPGA Primecells */
9199340b RK	154	APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
	155	APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
	156	APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
	157	APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
	158	APB_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL);
a9b67db5 BB	159
a9b67db5 BB	160	/* DevChip Primecells */
9199340b RK	161	AHB_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL);
	162	AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
	163	APB_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL);
	164	APB_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data);
	165	APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
	166	APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
	167	APB_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL);
	168	APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
	169	APB_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL);
	170	APB_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL);
	171	APB_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL);
	172	APB_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data);
a9b67db5 BB	173
a9b67db5 BB	174	/* Primecells on the NEC ISSP chip */
9199340b RK	175	AHB_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data);
9199340b RK	176	AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
a9b67db5 BB	177
	178	static struct amba_device *amba_devs[] __initdata = {
	179	&dmac_device,
	180	&uart0_device,
	181	&uart1_device,
	182	&uart2_device,
	183	&uart3_device,
	184	&smc_device,
	185	&clcd_device,
	186	&sctl_device,
	187	&wdog_device,
	188	&gpio0_device,
	189	&gpio1_device,
	190	&gpio2_device,
	191	&rtc_device,
	192	&sci0_device,
	193	&ssp0_device,
	194	&aaci_device,
	195	&mmc0_device,
	196	&kmi0_device,
	197	&kmi1_device,
	198	};
	199
	200	/*
	201	* RealView PB11MPCore platform devices
	202	*/
	203	static struct resource realview_pb11mp_flash_resource[] = {
	204	[0] = {
	205	.start = REALVIEW_PB11MP_FLASH0_BASE,
	206	.end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
	207	.flags = IORESOURCE_MEM,
	208	},
	209	[1] = {
	210	.start = REALVIEW_PB11MP_FLASH1_BASE,
	211	.end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
	212	.flags = IORESOURCE_MEM,
	213	},
	214	};
	215
	216	static struct resource realview_pb11mp_smsc911x_resources[] = {
	217	[0] = {
	218	.start = REALVIEW_PB11MP_ETH_BASE,
	219	.end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
	220	.flags = IORESOURCE_MEM,
	221	},
	222	[1] = {
	223	.start = IRQ_TC11MP_ETH,
	224	.end = IRQ_TC11MP_ETH,
	225	.flags = IORESOURCE_IRQ,
	226	},
	227	};
	228
7db21712 CM	229	static struct resource realview_pb11mp_isp1761_resources[] = {
	230	[0] = {
	231	.start = REALVIEW_PB11MP_USB_BASE,
	232	.end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
	233	.flags = IORESOURCE_MEM,
	234	},
	235	[1] = {
	236	.start = IRQ_TC11MP_USB,
	237	.end = IRQ_TC11MP_USB,
	238	.flags = IORESOURCE_IRQ,
	239	},
	240	};
	241
f417cbad WD	242	static struct resource pmu_resources[] = {
	243	[0] = {
	244	.start = IRQ_TC11MP_PMU_CPU0,
	245	.end = IRQ_TC11MP_PMU_CPU0,
	246	.flags = IORESOURCE_IRQ,
	247	},
	248	[1] = {
	249	.start = IRQ_TC11MP_PMU_CPU1,
	250	.end = IRQ_TC11MP_PMU_CPU1,
	251	.flags = IORESOURCE_IRQ,
	252	},
	253	[2] = {
	254	.start = IRQ_TC11MP_PMU_CPU2,
	255	.end = IRQ_TC11MP_PMU_CPU2,
	256	.flags = IORESOURCE_IRQ,
	257	},
	258	[3] = {
	259	.start = IRQ_TC11MP_PMU_CPU3,
	260	.end = IRQ_TC11MP_PMU_CPU3,
	261	.flags = IORESOURCE_IRQ,
	262	},
	263	};
	264
	265	static struct platform_device pmu_device = {
	266	.name = "arm-pmu",
	267	.id = ARM_PMU_DEVICE_CPU,
	268	.num_resources = ARRAY_SIZE(pmu_resources),
	269	.resource = pmu_resources,
	270	};
	271
a9b67db5 BB	272	static void __init gic_init_irq(void)
	273	{
	274	unsigned int pldctrl;
	275
	276	/* new irq mode with no DCC */
	277	writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
	278	pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
	279	pldctrl \|= 2 << 22;
	280	writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
	281	writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
	282
	283	/* ARM11MPCore test chip GIC, primary */
b580b899	284	gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
ff2e27ae	285	__io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
a9b67db5 BB	286
a9b67db5 BB	287	/* board GIC, secondary */
b580b899 RK	288	gic_init(1, IRQ_PB11MP_GIC_START,
	289	__io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
	290	__io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
a9b67db5 BB	291	gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
	292	}
	293
7c380f27 MZ	294	#ifdef CONFIG_HAVE_ARM_TWD
	295	static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
	296	REALVIEW_TC11MP_TWD_BASE,
	297	IRQ_LOCALTIMER);
	298
	299	static void __init realview_pb11mp_twd_init(void)
	300	{
	301	int err = twd_local_timer_register(&twd_local_timer);
	302	if (err)
	303	pr_err("twd_local_timer_register failed %d\n", err);
	304	}
	305	#else
	306	#define realview_pb11mp_twd_init() do {} while(0)
	307	#endif
	308
a9b67db5 BB	309	static void __init realview_pb11mp_timer_init(void)
	310	{
	311	timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
	312	timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
	313	timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
	314	timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
	315
f9a6aa43	316	realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
a9b67db5	317	realview_timer_init(IRQ_TC11MP_TIMER0_1);
7c380f27	318	realview_pb11mp_twd_init();
a9b67db5 BB	319	}
	320
	321	static struct sys_timer realview_pb11mp_timer = {
	322	.init = realview_pb11mp_timer_init,
	323	};
	324
47cacdd4	325	static void realview_pb11mp_restart(char mode, const char *cmd)
426fcd2a	326	{
4c9f8be7 CT	327	void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
4c9f8be7 CT	328	void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
426fcd2a PJ	329
	330	/*
	331	* To reset, we hit the on-board reset register
	332	* in the system FPGA
	333	*/
4c9f8be7 CT	334	__raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
	335	__raw_writel(0x0000, reset_ctrl);
	336	__raw_writel(0x0004, reset_ctrl);
47cacdd4	337	dsb();
426fcd2a PJ	338	}
426fcd2a PJ	339
a9b67db5 BB	340	static void __init realview_pb11mp_init(void)
	341	{
	342	int i;
	343
ba927951	344	#ifdef CONFIG_CACHE_L2X0
a9b67db5 BB	345	/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
	346	* Bits: .... ...0 0111 1001 0000 .... .... .... */
	347	l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
ba927951	348	#endif
a9b67db5	349
a9b67db5 BB	350	realview_flash_register(realview_pb11mp_flash_resource,
a9b67db5 BB	351	ARRAY_SIZE(realview_pb11mp_flash_resource));
0a381330	352	realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
a9b67db5	353	platform_device_register(&realview_i2c_device);
6be62ba2	354	platform_device_register(&realview_cf_device);
7db21712	355	realview_usb_register(realview_pb11mp_isp1761_resources);
f417cbad	356	platform_device_register(&pmu_device);
a9b67db5 BB	357
	358	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	359	struct amba_device *d = amba_devs[i];
	360	amba_device_register(d, &iomem_resource);
	361	}
	362
	363	#ifdef CONFIG_LEDS
	364	leds_event = realview_leds_event;
	365	#endif
	366	}
	367
	368	MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
	369	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
9ddea57e	370	.atag_offset = 0x100,
5b39d154	371	.fixup = realview_fixup,
a9b67db5	372	.map_io = realview_pb11mp_map_io,
631e55f9	373	.init_early = realview_init_early,
a9b67db5 BB	374	.init_irq = gic_init_irq,
a9b67db5 BB	375	.timer = &realview_pb11mp_timer,
1b99d9cc	376	.handle_irq = gic_handle_irq,
a9b67db5	377	.init_machine = realview_pb11mp_init,
00e9125e NP	378	#ifdef CONFIG_ZONE_DMA
	379	.dma_zone_size = SZ_256M,
	380	#endif
47cacdd4	381	.restart = realview_pb11mp_restart,
a9b67db5	382	MACHINE_END