[linux-2.6-block.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/ata_platform.h>
#include <linux/amba/mmci.h>
#include <linux/gfp.h>
#include <linux/clkdev.h>

#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>

#include <asm/hardware/gic.h>

#include <mach/platform.h>
#include <mach/irqs.h>
#include <plat/timer-sp.h>

#include "core.h"

/* used by entry-macro.S and platsmp.c */
void __iomem *gic_cpu_base_addr;

#ifdef CONFIG_ZONE_DMA
/*
 * Adjust the zones if there are restrictions for DMA access.
 */
void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
{
	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;

	if (!machine_is_realview_pbx() || size[0] <= dma_size)
		return;

	size[ZONE_NORMAL] = size[0] - dma_size;
	size[ZONE_DMA] = dma_size;
	hole[ZONE_NORMAL] = hole[0];
	hole[ZONE_DMA] = 0;
}
#endif


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
};

int realview_flash_register(struct resource *res, u32 num)
{
	realview_flash_device.resource = res;
	realview_flash_device.num_resources = num;
	return platform_device_register(&realview_flash_device);
}

static struct smsc911x_platform_config smsc911x_config = {
	.flags		= SMSC911X_USE_32BIT,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device realview_eth_device = {
	.name		= "smsc911x",
	.id		= 0,
	.num_resources	= 2,
};

int realview_eth_register(const char *name, struct resource *res)
{
	if (name)
		realview_eth_device.name = name;
	realview_eth_device.resource = res;
	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
		realview_eth_device.dev.platform_data = &smsc911x_config;

	return platform_device_register(&realview_eth_device);
}

struct platform_device realview_usb_device = {
	.name			= "isp1760",
	.num_resources		= 2,
};

int realview_usb_register(struct resource *res)
{
	realview_usb_device.resource = res;
	return platform_device_register(&realview_usb_device);
}

static struct pata_platform_info pata_platform_data = {
	.ioport_shift		= 1,
};

static struct resource pata_resources[] = {
	[0] = {
		.start		= REALVIEW_CF_BASE,
		.end		= REALVIEW_CF_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= REALVIEW_CF_BASE + 0x100,
		.end		= REALVIEW_CF_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

struct platform_device realview_cf_device = {
	.name			= "pata_platform",
	.id			= -1,
	.num_resources		= ARRAY_SIZE(pata_resources),
	.resource		= pata_resources,
	.dev			= {
		.platform_data	= &pata_platform_data,
	},
};

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= 0,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

static struct i2c_board_info realview_i2c_board_info[] = {
	{
		I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
	},
};

static int __init realview_i2c_init(void)
{
	return i2c_register_board_info(0, realview_i2c_board_info,
				       ARRAY_SIZE(realview_i2c_board_info));
}
arch_initcall(realview_i2c_init);

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

/*
 * This is only used if GPIOLIB support is disabled
 */
static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (machine_is_realview_pb1176()) {
		static bool inserted = false;

		/*
		 * The PB1176 does not have the status register,
		 * assume it is inserted at startup, then invert
		 * for each call so card insertion/removal will
		 * be detected anyway. This will not be called if
		 * GPIO on PL061 is active, which is the proper
		 * way to do this on the PB1176.
		 */
		inserted = !inserted;
		return inserted ? 0 : 1;
	}

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return readl(REALVIEW_SYSMCI) & mask;
}

struct mmci_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
	.gpio_wp	= 17,
	.gpio_cd	= 16,
	.cd_invert	= true,
};

struct mmci_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
	.gpio_wp	= 19,
	.gpio_cd	= 18,
	.cd_invert	= true,
};

/*
 * Clock handling
 */
static const struct icst_params realview_oscvco_params = {
	.ref		= 24000000,
	.vco_max	= ICST307_VCO_MAX,
	.vco_min	= ICST307_VCO_MIN,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
	.s2div		= icst307_s2div,
	.idx2s		= icst307_idx2s,
};

static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	u32 val;

	val = readl(clk->vcoreg) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, clk->vcoreg);
	writel(0, sys_lock);
}

static const struct clk_ops oscvco_clk_ops = {
	.round	= icst_clk_round,
	.set	= icst_clk_set,
	.setvco	= realview_oscvco_set,
};

static struct clk oscvco_clk = {
	.ops	= &oscvco_clk_ops,
	.params	= &realview_oscvco_params,
};

/*
 * These are fixed clocks.
 */
static struct clk ref24_clk = {
	.rate	= 24000000,
};

static struct clk dummy_apb_pclk;

static struct clk_lookup lookups[] = {
	{	/* Bus clock */
		.con_id		= "apb_pclk",
		.clk		= &dummy_apb_pclk,
	}, {	/* UART0 */
		.dev_id		= "dev:uart0",
		.clk		= &ref24_clk,
	}, {	/* UART1 */
		.dev_id		= "dev:uart1",
		.clk		= &ref24_clk,
	}, {	/* UART2 */
		.dev_id		= "dev:uart2",
		.clk		= &ref24_clk,
	}, {	/* UART3 */
		.dev_id		= "fpga:uart3",
		.clk		= &ref24_clk,
	}, {	/* UART3 is on the dev chip in PB1176 */
		.dev_id		= "dev:uart3",
		.clk		= &ref24_clk,
	}, {	/* UART4 only exists in PB1176 */
		.dev_id		= "fpga:uart4",
		.clk		= &ref24_clk,
	}, {	/* KMI0 */
		.dev_id		= "fpga:kmi0",
		.clk		= &ref24_clk,
	}, {	/* KMI1 */
		.dev_id		= "fpga:kmi1",
		.clk		= &ref24_clk,
	}, {	/* MMC0 */
		.dev_id		= "fpga:mmc0",
		.clk		= &ref24_clk,
	}, {	/* CLCD is in the PB1176 and EB DevChip */
		.dev_id		= "dev:clcd",
		.clk		= &oscvco_clk,
	}, {	/* PB:CLCD */
		.dev_id		= "issp:clcd",
		.clk		= &oscvco_clk,
	}, {	/* SSP */
		.dev_id		= "dev:ssp0",
		.clk		= &ref24_clk,
	}
};

static int __init clk_init(void)
{
	if (machine_is_realview_pb1176())
		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	else
		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	return 0;
}
core_initcall(clk_init);

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel xvga = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15748,
		.left_margin	= 152,
		.right_margin	= 48,
		.upper_margin	= 23,
		.lower_margin	= 3,
		.hsync_len	= 104,
		.vsync_len	= 4,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *vga_panel;
	struct clcd_panel *panel;
	u32 val;

	if (machine_is_realview_eb())
		vga_panel = &vga;
	else
		vga_panel = &xvga;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = vga_panel;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = vga_panel;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static int realview_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize;
	dma_addr_t dma;

	if (machine_is_realview_eb())
		/* VGA, 16bpp */
		framesize = 640 * 480 * 2;
	else
		/* XVGA, 16bpp */
		framesize = 1024 * 768 * 2;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL | GFP_DMA);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;
	u32 led = 1 << smp_processor_id();

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~led;
		break;

	case led_idle_end:
		val = val | led;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED7;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
void __iomem *timer0_va_base;
void __iomem *timer1_va_base;
void __iomem *timer2_va_base;
void __iomem *timer3_va_base;

/*
 * Set up the clock source and clock events devices
 */
void __init realview_timer_init(unsigned int timer_irq)
{
	u32 val;

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, timer0_va_base + TIMER_CTRL);
	writel(0, timer1_va_base + TIMER_CTRL);
	writel(0, timer2_va_base + TIMER_CTRL);
	writel(0, timer3_va_base + TIMER_CTRL);

	sp804_clocksource_init(timer3_va_base);
	sp804_clockevents_init(timer0_va_base, timer_irq);
}

/*
 * Setup the memory banks.
 */
void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
		    struct meminfo *meminfo)
{
	/*
	 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
	 * Half of this is mirrored at 0.
	 */
#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
	meminfo->bank[0].start = 0x70000000;
	meminfo->bank[0].size = SZ_512M;
	meminfo->nr_banks = 1;
#else
	meminfo->bank[0].start = 0;
	meminfo->bank[0].size = SZ_256M;
	meminfo->nr_banks = 1;
#endif
}
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
fced80c7	28	#include <linux/io.h>
c5142e84	29	#include <linux/smsc911x.h>
6be62ba2	30	#include <linux/ata_platform.h>
6ef297f8	31	#include <linux/amba/mmci.h>
5a0e3ad6	32	#include <linux/gfp.h>
6d803ba7	33	#include <linux/clkdev.h>
8ad68bbf CM	34
8ad68bbf CM	35	#include <asm/system.h>
a09e64fb	36	#include <mach/hardware.h>
8ad68bbf CM	37	#include <asm/irq.h>
8ad68bbf CM	38	#include <asm/leds.h>
68c3d935	39	#include <asm/mach-types.h>
8ad68bbf	40	#include <asm/hardware/arm_timer.h>
c5a0adb5	41	#include <asm/hardware/icst.h>
8ad68bbf CM	42
	43	#include <asm/mach/arch.h>
	44	#include <asm/mach/flash.h>
	45	#include <asm/mach/irq.h>
8ad68bbf	46	#include <asm/mach/map.h>
8ad68bbf CM	47
	48	#include <asm/hardware/gic.h>
	49
ee8c9571 CM	50	#include <mach/platform.h>
ee8c9571 CM	51	#include <mach/irqs.h>
e3887714	52	#include <plat/timer-sp.h>
ee8c9571	53
8ad68bbf	54	#include "core.h"
8ad68bbf	55
1bbdf637	56	/* used by entry-macro.S and platsmp.c */
c4057f52 CM	57	void __iomem *gic_cpu_base_addr;
c4057f52 CM	58
c97c5aa8 CM	59	#ifdef CONFIG_ZONE_DMA
	60	/*
	61	* Adjust the zones if there are restrictions for DMA access.
	62	*/
b65b4781	63	void __init realview_adjust_zones(unsigned long size, unsigned long hole)
c97c5aa8 CM	64	{
	65	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
	66
b65b4781	67	if (!machine_is_realview_pbx() \|\| size[0] <= dma_size)
c97c5aa8 CM	68	return;
	69
	70	size[ZONE_NORMAL] = size[0] - dma_size;
	71	size[ZONE_DMA] = dma_size;
	72	hole[ZONE_NORMAL] = hole[0];
	73	hole[ZONE_DMA] = 0;
	74	}
	75	#endif
	76
8ad68bbf CM	77
	78	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	79
	80	static int realview_flash_init(void)
	81	{
	82	u32 val;
	83
	84	val = __raw_readl(REALVIEW_FLASHCTRL);
	85	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	86	__raw_writel(val, REALVIEW_FLASHCTRL);
	87
	88	return 0;
	89	}
	90
	91	static void realview_flash_exit(void)
	92	{
	93	u32 val;
	94
	95	val = __raw_readl(REALVIEW_FLASHCTRL);
	96	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	97	__raw_writel(val, REALVIEW_FLASHCTRL);
	98	}
	99
	100	static void realview_flash_set_vpp(int on)
	101	{
	102	u32 val;
	103
	104	val = __raw_readl(REALVIEW_FLASHCTRL);
	105	if (on)
	106	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	107	else
	108	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	109	__raw_writel(val, REALVIEW_FLASHCTRL);
	110	}
	111
	112	static struct flash_platform_data realview_flash_data = {
	113	.map_name = "cfi_probe",
	114	.width = 4,
	115	.init = realview_flash_init,
	116	.exit = realview_flash_exit,
	117	.set_vpp = realview_flash_set_vpp,
	118	};
	119
8ad68bbf CM	120	struct platform_device realview_flash_device = {
	121	.name = "armflash",
	122	.id = 0,
	123	.dev = {
	124	.platform_data = &realview_flash_data,
	125	},
8ad68bbf CM	126	};
8ad68bbf CM	127
a44ddfd5 CM	128	int realview_flash_register(struct resource *res, u32 num)
	129	{
	130	realview_flash_device.resource = res;
	131	realview_flash_device.num_resources = num;
	132	return platform_device_register(&realview_flash_device);
	133	}
	134
c5142e84 SG	135	static struct smsc911x_platform_config smsc911x_config = {
	136	.flags = SMSC911X_USE_32BIT,
	137	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	138	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	139	.phy_interface = PHY_INTERFACE_MODE_MII,
0a5b2f6b CM	140	};
0a5b2f6b CM	141
0a381330	142	static struct platform_device realview_eth_device = {
c5142e84	143	.name = "smsc911x",
0a381330 CM	144	.id = 0,
	145	.num_resources = 2,
	146	};
	147
	148	int realview_eth_register(const char name, struct resource res)
	149	{
	150	if (name)
	151	realview_eth_device.name = name;
	152	realview_eth_device.resource = res;
c5142e84 SG	153	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
c5142e84 SG	154	realview_eth_device.dev.platform_data = &smsc911x_config;
0a381330 CM	155
0a381330 CM	156	return platform_device_register(&realview_eth_device);
7db21712 CM	157	}
	158
	159	struct platform_device realview_usb_device = {
	160	.name = "isp1760",
	161	.num_resources = 2,
	162	};
	163
	164	int realview_usb_register(struct resource *res)
	165	{
	166	realview_usb_device.resource = res;
	167	return platform_device_register(&realview_usb_device);
0a381330 CM	168	}
0a381330 CM	169
6be62ba2 CM	170	static struct pata_platform_info pata_platform_data = {
	171	.ioport_shift = 1,
	172	};
	173
	174	static struct resource pata_resources[] = {
	175	[0] = {
	176	.start = REALVIEW_CF_BASE,
	177	.end = REALVIEW_CF_BASE + 0xff,
	178	.flags = IORESOURCE_MEM,
	179	},
	180	[1] = {
	181	.start = REALVIEW_CF_BASE + 0x100,
	182	.end = REALVIEW_CF_BASE + SZ_4K - 1,
	183	.flags = IORESOURCE_MEM,
	184	},
	185	};
	186
	187	struct platform_device realview_cf_device = {
	188	.name = "pata_platform",
	189	.id = -1,
	190	.num_resources = ARRAY_SIZE(pata_resources),
	191	.resource = pata_resources,
	192	.dev = {
	193	.platform_data = &pata_platform_data,
	194	},
	195	};
	196
6b65cd74 RK	197	static struct resource realview_i2c_resource = {
	198	.start = REALVIEW_I2C_BASE,
	199	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	200	.flags = IORESOURCE_MEM,
	201	};
	202
	203	struct platform_device realview_i2c_device = {
	204	.name = "versatile-i2c",
533ad5e6	205	.id = 0,
6b65cd74 RK	206	.num_resources = 1,
	207	.resource = &realview_i2c_resource,
	208	};
	209
533ad5e6 CM	210	static struct i2c_board_info realview_i2c_board_info[] = {
533ad5e6 CM	211	{
64e8be6e	212	I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6 CM	213	},
	214	};
	215
	216	static int __init realview_i2c_init(void)
	217	{
	218	return i2c_register_board_info(0, realview_i2c_board_info,
	219	ARRAY_SIZE(realview_i2c_board_info));
	220	}
	221	arch_initcall(realview_i2c_init);
	222
8ad68bbf CM	223	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
8ad68bbf CM	224
98b0979f RK	225	/*
	226	* This is only used if GPIOLIB support is disabled
	227	*/
8ad68bbf CM	228	static unsigned int realview_mmc_status(struct device *dev)
	229	{
	230	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	231	u32 mask;
	232
48f1d5a3 LW	233	if (machine_is_realview_pb1176()) {
	234	static bool inserted = false;
	235
	236	/*
	237	* The PB1176 does not have the status register,
	238	* assume it is inserted at startup, then invert
	239	* for each call so card insertion/removal will
	240	* be detected anyway. This will not be called if
	241	* GPIO on PL061 is active, which is the proper
	242	* way to do this on the PB1176.
	243	*/
	244	inserted = !inserted;
	245	return inserted ? 0 : 1;
	246	}
	247
8ad68bbf CM	248	if (adev->res.start == REALVIEW_MMCI0_BASE)
	249	mask = 1;
	250	else
	251	mask = 2;
	252
74bc8093	253	return readl(REALVIEW_SYSMCI) & mask;
8ad68bbf CM	254	}
8ad68bbf CM	255
6ef297f8	256	struct mmci_platform_data realview_mmc0_plat_data = {
8ad68bbf CM	257	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
8ad68bbf CM	258	.status = realview_mmc_status,
98b0979f RK	259	.gpio_wp = 17,
98b0979f RK	260	.gpio_cd = 16,
29719445	261	.cd_invert = true,
8ad68bbf CM	262	};
8ad68bbf CM	263
6ef297f8	264	struct mmci_platform_data realview_mmc1_plat_data = {
8ad68bbf CM	265	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
8ad68bbf CM	266	.status = realview_mmc_status,
98b0979f RK	267	.gpio_wp = 19,
98b0979f RK	268	.gpio_cd = 18,
29719445	269	.cd_invert = true,
8ad68bbf CM	270	};
	271
	272	/*
	273	* Clock handling
	274	*/
39c0cb02	275	static const struct icst_params realview_oscvco_params = {
64fceb1d	276	.ref = 24000000,
4de2edbd	277	.vco_max = ICST307_VCO_MAX,
e73a46a3	278	.vco_min = ICST307_VCO_MIN,
8ad68bbf CM	279	.vd_min = 4 + 8,
	280	.vd_max = 511 + 8,
	281	.rd_min = 1 + 2,
	282	.rd_max = 127 + 2,
232eaf7f RK	283	.s2div = icst307_s2div,
232eaf7f RK	284	.idx2s = icst307_idx2s,
8ad68bbf CM	285	};
8ad68bbf CM	286
39c0cb02	287	static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
8ad68bbf CM	288	{
8ad68bbf CM	289	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
8ad68bbf CM	290	u32 val;
8ad68bbf CM	291
d1914c7e	292	val = readl(clk->vcoreg) & ~0x7ffff;
8ad68bbf CM	293	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	294
	295	writel(0xa05f, sys_lock);
d1914c7e	296	writel(val, clk->vcoreg);
8ad68bbf CM	297	writel(0, sys_lock);
	298	}
	299
9bf5b2ef RK	300	static const struct clk_ops oscvco_clk_ops = {
	301	.round = icst_clk_round,
	302	.set = icst_clk_set,
	303	.setvco = realview_oscvco_set,
	304	};
	305
cf30fb4a	306	static struct clk oscvco_clk = {
9bf5b2ef	307	.ops = &oscvco_clk_ops,
8ad68bbf	308	.params = &realview_oscvco_params,
8ad68bbf CM	309	};
8ad68bbf CM	310
cf30fb4a RK	311	/*
	312	* These are fixed clocks.
	313	*/
	314	static struct clk ref24_clk = {
	315	.rate = 24000000,
	316	};
	317
3126c7bc RK	318	static struct clk dummy_apb_pclk;
3126c7bc RK	319
cf30fb4a	320	static struct clk_lookup lookups[] = {
3126c7bc RK	321	{ /* Bus clock */
	322	.con_id = "apb_pclk",
	323	.clk = &dummy_apb_pclk,
	324	}, { /* UART0 */
4321532c	325	.dev_id = "dev:uart0",
cf30fb4a RK	326	.clk = &ref24_clk,
cf30fb4a RK	327	}, { /* UART1 */
4321532c	328	.dev_id = "dev:uart1",
cf30fb4a RK	329	.clk = &ref24_clk,
cf30fb4a RK	330	}, { /* UART2 */
4321532c	331	.dev_id = "dev:uart2",
cf30fb4a RK	332	.clk = &ref24_clk,
cf30fb4a RK	333	}, { /* UART3 */
4321532c	334	.dev_id = "fpga:uart3",
cf30fb4a	335	.clk = &ref24_clk,
48f1d5a3 LW	336	}, { /* UART3 is on the dev chip in PB1176 */
	337	.dev_id = "dev:uart3",
	338	.clk = &ref24_clk,
	339	}, { /* UART4 only exists in PB1176 */
	340	.dev_id = "fpga:uart4",
	341	.clk = &ref24_clk,
cf30fb4a	342	}, { /* KMI0 */
4321532c	343	.dev_id = "fpga:kmi0",
cf30fb4a RK	344	.clk = &ref24_clk,
cf30fb4a RK	345	}, { /* KMI1 */
4321532c	346	.dev_id = "fpga:kmi1",
cf30fb4a RK	347	.clk = &ref24_clk,
cf30fb4a RK	348	}, { /* MMC0 */
4321532c	349	.dev_id = "fpga:mmc0",
cf30fb4a	350	.clk = &ref24_clk,
48f1d5a3	351	}, { /* CLCD is in the PB1176 and EB DevChip */
4321532c	352	.dev_id = "dev:clcd",
cf30fb4a RK	353	.clk = &oscvco_clk,
cf30fb4a RK	354	}, { /* PB:CLCD */
4321532c	355	.dev_id = "issp:clcd",
cf30fb4a	356	.clk = &oscvco_clk,
d6ada860 LW	357	}, { /* SSP */
	358	.dev_id = "dev:ssp0",
	359	.clk = &ref24_clk,
cf30fb4a RK	360	}
	361	};
	362
	363	static int __init clk_init(void)
	364	{
d1914c7e RK	365	if (machine_is_realview_pb1176())
	366	oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	367	else
	368	oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	369
0a0300dc	370	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
d1914c7e	371
cf30fb4a RK	372	return 0;
cf30fb4a RK	373	}
06385e49	374	core_initcall(clk_init);
cf30fb4a	375
8ad68bbf CM	376	/*
	377	* CLCD support.
	378	*/
8ad68bbf CM	379	#define SYS_CLCD_NLCDIOON (1 << 2)
	380	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	381	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	382	#define SYS_CLCD_ID_MASK (0x1f << 8)
	383	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	384	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	385	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	386	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	387	#define SYS_CLCD_ID_VGA (0x1f << 8)
	388
	389	static struct clcd_panel vga = {
	390	.mode = {
	391	.name = "VGA",
	392	.refresh = 60,
	393	.xres = 640,
	394	.yres = 480,
	395	.pixclock = 39721,
	396	.left_margin = 40,
	397	.right_margin = 24,
	398	.upper_margin = 32,
	399	.lower_margin = 11,
	400	.hsync_len = 96,
	401	.vsync_len = 2,
	402	.sync = 0,
	403	.vmode = FB_VMODE_NONINTERLACED,
	404	},
	405	.width = -1,
	406	.height = -1,
	407	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	408	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	409	.bpp = 16,
	410	};
	411
c34a1025 CT	412	static struct clcd_panel xvga = {
	413	.mode = {
	414	.name = "XVGA",
	415	.refresh = 60,
	416	.xres = 1024,
	417	.yres = 768,
	418	.pixclock = 15748,
	419	.left_margin = 152,
	420	.right_margin = 48,
	421	.upper_margin = 23,
	422	.lower_margin = 3,
	423	.hsync_len = 104,
	424	.vsync_len = 4,
	425	.sync = 0,
	426	.vmode = FB_VMODE_NONINTERLACED,
	427	},
	428	.width = -1,
	429	.height = -1,
	430	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	431	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	432	.bpp = 16,
	433	};
	434
	435	static struct clcd_panel sanyo_3_8_in = {
	436	.mode = {
	437	.name = "Sanyo QVGA",
	438	.refresh = 116,
	439	.xres = 320,
	440	.yres = 240,
	441	.pixclock = 100000,
	442	.left_margin = 6,
	443	.right_margin = 6,
	444	.upper_margin = 5,
	445	.lower_margin = 5,
	446	.hsync_len = 6,
	447	.vsync_len = 6,
	448	.sync = 0,
	449	.vmode = FB_VMODE_NONINTERLACED,
	450	},
	451	.width = -1,
	452	.height = -1,
	453	.tim2 = TIM2_BCD,
4eccca20	454	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	455	.bpp = 16,
	456	};
	457
	458	static struct clcd_panel sanyo_2_5_in = {
	459	.mode = {
	460	.name = "Sanyo QVGA Portrait",
	461	.refresh = 116,
	462	.xres = 240,
	463	.yres = 320,
	464	.pixclock = 100000,
	465	.left_margin = 20,
	466	.right_margin = 10,
	467	.upper_margin = 2,
	468	.lower_margin = 2,
	469	.hsync_len = 10,
	470	.vsync_len = 2,
	471	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	472	.vmode = FB_VMODE_NONINTERLACED,
	473	},
	474	.width = -1,
	475	.height = -1,
	476	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
4eccca20	477	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	478	.bpp = 16,
	479	};
	480
	481	static struct clcd_panel epson_2_2_in = {
	482	.mode = {
	483	.name = "Epson QCIF",
	484	.refresh = 390,
	485	.xres = 176,
	486	.yres = 220,
	487	.pixclock = 62500,
	488	.left_margin = 3,
	489	.right_margin = 2,
	490	.upper_margin = 1,
	491	.lower_margin = 0,
	492	.hsync_len = 3,
	493	.vsync_len = 2,
	494	.sync = 0,
	495	.vmode = FB_VMODE_NONINTERLACED,
	496	},
	497	.width = -1,
	498	.height = -1,
	499	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	500	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	501	.bpp = 16,
	502	};
	503
	504	/*
	505	* Detect which LCD panel is connected, and return the appropriate
	506	* clcd_panel structure. Note: we do not have any information on
	507	* the required timings for the 8.4in panel, so we presently assume
	508	* VGA timings.
	509	*/
	510	static struct clcd_panel *realview_clcd_panel(void)
	511	{
	512	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025 CT	513	struct clcd_panel *vga_panel;
c34a1025 CT	514	struct clcd_panel *panel;
8ad68bbf CM	515	u32 val;
8ad68bbf CM	516
c34a1025 CT	517	if (machine_is_realview_eb())
	518	vga_panel = &vga;
	519	else
	520	vga_panel = &xvga;
	521
8ad68bbf CM	522	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	523	if (val == SYS_CLCD_ID_SANYO_3_8)
	524	panel = &sanyo_3_8_in;
	525	else if (val == SYS_CLCD_ID_SANYO_2_5)
	526	panel = &sanyo_2_5_in;
	527	else if (val == SYS_CLCD_ID_EPSON_2_2)
	528	panel = &epson_2_2_in;
	529	else if (val == SYS_CLCD_ID_VGA)
c34a1025	530	panel = vga_panel;
8ad68bbf CM	531	else {
	532	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
	533	val);
c34a1025	534	panel = vga_panel;
8ad68bbf CM	535	}
	536
	537	return panel;
	538	}
	539
	540	/*
	541	* Disable all display connectors on the interface module.
	542	*/
	543	static void realview_clcd_disable(struct clcd_fb *fb)
	544	{
	545	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	546	u32 val;
	547
	548	val = readl(sys_clcd);
	549	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	550	writel(val, sys_clcd);
	551	}
	552
	553	/*
	554	* Enable the relevant connector on the interface module.
	555	*/
	556	static void realview_clcd_enable(struct clcd_fb *fb)
	557	{
	558	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	559	u32 val;
	560
8ad68bbf	561	/*
9e7714d0	562	* Enable the PSUs
8ad68bbf	563	*/
9e7714d0	564	val = readl(sys_clcd);
8ad68bbf CM	565	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	566	writel(val, sys_clcd);
	567	}
	568
8ad68bbf CM	569	static int realview_clcd_setup(struct clcd_fb *fb)
8ad68bbf CM	570	{
c34a1025	571	unsigned long framesize;
8ad68bbf CM	572	dma_addr_t dma;
8ad68bbf CM	573
c34a1025 CT	574	if (machine_is_realview_eb())
	575	/* VGA, 16bpp */
	576	framesize = 640 * 480 * 2;
	577	else
	578	/* XVGA, 16bpp */
	579	framesize = 1024 * 768 * 2;
	580
8ad68bbf CM	581	fb->panel = realview_clcd_panel();
	582
	583	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
c97c5aa8	584	&dma, GFP_KERNEL \| GFP_DMA);
8ad68bbf CM	585	if (!fb->fb.screen_base) {
	586	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	587	return -ENOMEM;
	588	}
	589
	590	fb->fb.fix.smem_start = dma;
	591	fb->fb.fix.smem_len = framesize;
	592
	593	return 0;
	594	}
	595
	596	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	597	{
	598	return dma_mmap_writecombine(&fb->dev->dev, vma,
	599	fb->fb.screen_base,
	600	fb->fb.fix.smem_start,
	601	fb->fb.fix.smem_len);
	602	}
	603
	604	static void realview_clcd_remove(struct clcd_fb *fb)
	605	{
	606	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	607	fb->fb.screen_base, fb->fb.fix.smem_start);
	608	}
	609
	610	struct clcd_board clcd_plat_data = {
	611	.name = "RealView",
	612	.check = clcdfb_check,
	613	.decode = clcdfb_decode,
	614	.disable = realview_clcd_disable,
	615	.enable = realview_clcd_enable,
	616	.setup = realview_clcd_setup,
	617	.mmap = realview_clcd_mmap,
	618	.remove = realview_clcd_remove,
	619	};
	620
	621	#ifdef CONFIG_LEDS
	622	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	623
	624	void realview_leds_event(led_event_t ledevt)
	625	{
	626	unsigned long flags;
	627	u32 val;
da055eb5	628	u32 led = 1 << smp_processor_id();
8ad68bbf CM	629
	630	local_irq_save(flags);
	631	val = readl(VA_LEDS_BASE);
	632
	633	switch (ledevt) {
	634	case led_idle_start:
da055eb5	635	val = val & ~led;
8ad68bbf CM	636	break;
	637
	638	case led_idle_end:
da055eb5	639	val = val \| led;
8ad68bbf CM	640	break;
	641
	642	case led_timer:
da055eb5	643	val = val ^ REALVIEW_SYS_LED7;
8ad68bbf CM	644	break;
	645
	646	case led_halted:
	647	val = 0;
	648	break;
	649
	650	default:
	651	break;
	652	}
	653
	654	writel(val, VA_LEDS_BASE);
	655	local_irq_restore(flags);
	656	}
	657	#endif /* CONFIG_LEDS */
	658
	659	/*
	660	* Where is the timer (VA)?
	661	*/
80192735 CM	662	void __iomem *timer0_va_base;
	663	void __iomem *timer1_va_base;
	664	void __iomem *timer2_va_base;
	665	void __iomem *timer3_va_base;
8ad68bbf	666
8ad68bbf	667	/*
a8655e83	668	* Set up the clock source and clock events devices
8ad68bbf	669	*/
8cc4c548	670	void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf CM	671	{
	672	u32 val;
	673
	674	/*
	675	* set clock frequency:
	676	* REALVIEW_REFCLK is 32KHz
	677	* REALVIEW_TIMCLK is 1MHz
	678	*/
	679	val = readl(__io_address(REALVIEW_SCTL_BASE));
	680	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	681	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	682	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	683	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	684	__io_address(REALVIEW_SCTL_BASE));
	685
	686	/*
	687	* Initialise to a known state (all timers off)
	688	*/
80192735 CM	689	writel(0, timer0_va_base + TIMER_CTRL);
	690	writel(0, timer1_va_base + TIMER_CTRL);
	691	writel(0, timer2_va_base + TIMER_CTRL);
	692	writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf	693
e3887714 RK	694	sp804_clocksource_init(timer3_va_base);
e3887714 RK	695	sp804_clockevents_init(timer0_va_base, timer_irq);
8ad68bbf	696	}
5b39d154 CM	697
	698	/*
	699	* Setup the memory banks.
	700	*/
	701	void realview_fixup(struct machine_desc mdesc, struct tag tags, char **from,
	702	struct meminfo *meminfo)
	703	{
	704	/*
	705	* Most RealView platforms have 512MB contiguous RAM at 0x70000000.
	706	* Half of this is mirrored at 0.
	707	*/
	708	#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
	709	meminfo->bank[0].start = 0x70000000;
	710	meminfo->bank[0].size = SZ_512M;
	711	meminfo->nr_banks = 1;
	712	#else
	713	meminfo->bank[0].start = 0;
	714	meminfo->bank[0].size = SZ_256M;
	715	meminfo->nr_banks = 1;
	716	#endif
	717	}