[linux-block.git] / arch / arm / mach-pxa / standby.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * PXA27x standby mode
 *
 * Author: David Burrage
 *
 * 2005 (c) MontaVista Software, Inc.
 */

#include <linux/linkage.h>
#include <asm/assembler.h>

#include "pxa2xx-regs.h"

		.text

#ifdef CONFIG_PXA27x
ENTRY(pxa_cpu_standby)
	ldr	r0, =PSSR
	mov	r1, #(PSSR_PH | PSSR_STS)
	mov	r2, #PWRMODE_STANDBY
	mov	r3, #UNCACHED_PHYS_0	@ Read mem context in.
	ldr	ip, [r3]
	b	1f

	.align	5
1:	mcr	p14, 0, r2, c7, c0, 0	@ put the system into Standby
	str	r1, [r0]		@ make sure PSSR_PH/STS are clear
	ret	lr

#endif

#ifdef CONFIG_PXA3xx

#define PXA3_MDCNFG		0x0000
#define PXA3_MDCNFG_DMCEN	(1 << 30)
#define PXA3_DDR_HCAL		0x0060
#define PXA3_DDR_HCAL_HCRNG	0x1f
#define PXA3_DDR_HCAL_HCPROG	(1 << 28)
#define PXA3_DDR_HCAL_HCEN	(1 << 31)
#define PXA3_DMCIER		0x0070
#define PXA3_DMCIER_EDLP	(1 << 29)
#define PXA3_DMCISR		0x0078
#define PXA3_RCOMP		0x0100
#define PXA3_RCOMP_SWEVAL	(1 << 31)

ENTRY(pm_enter_standby_start)
	mov	r1, #0xf6000000			@ DMEMC_REG_BASE (PXA3_MDCNFG)
	add	r1, r1, #0x00100000

	/*
	 * Preload the TLB entry for accessing the dynamic memory
	 * controller registers.  Note that page table lookups will
	 * fail until the dynamic memory controller has been
	 * reinitialised - and that includes MMU page table walks.
	 * This also means that only the dynamic memory controller
	 * can be reliably accessed in the code following standby.
	 */
	ldr	r2, [r1]			@ Dummy read PXA3_MDCNFG

	mcr	p14, 0, r0, c7, c0, 0
	.rept	8
	nop
	.endr

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ Clear (and wait for) HCEN
	bic	r0, r0, #PXA3_DDR_HCAL_HCEN
	str	r0, [r1, #PXA3_DDR_HCAL]
1:	ldr	r0, [r1, #PXA3_DDR_HCAL]
	tst	r0, #PXA3_DDR_HCAL_HCEN
	bne	1b

	ldr	r0, [r1, #PXA3_RCOMP]		@ Initiate RCOMP
	orr	r0, r0, #PXA3_RCOMP_SWEVAL
	str	r0, [r1, #PXA3_RCOMP]

	mov	r0, #~0				@ Clear interrupts
	str	r0, [r1, #PXA3_DMCISR]

	ldr	r0, [r1, #PXA3_DMCIER]		@ set DMIER[EDLP]
	orr	r0, r0, #PXA3_DMCIER_EDLP
	str	r0, [r1, #PXA3_DMCIER]

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ clear HCRNG, set HCPROG, HCEN
	bic	r0, r0, #PXA3_DDR_HCAL_HCRNG
	orr	r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
	str	r0, [r1, #PXA3_DDR_HCAL]

1:	ldr	r0, [r1, #PXA3_DMCISR]
	tst	r0, #PXA3_DMCIER_EDLP
	beq	1b

	ldr	r0, [r1, #PXA3_MDCNFG]		@ set PXA3_MDCNFG[DMCEN]
	orr	r0, r0, #PXA3_MDCNFG_DMCEN
	str	r0, [r1, #PXA3_MDCNFG]
1:	ldr	r0, [r1, #PXA3_MDCNFG]
	tst	r0, #PXA3_MDCNFG_DMCEN
	beq	1b

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ set PXA3_DDR_HCAL[HCRNG]
	orr	r0, r0, #2 @ HCRNG
	str	r0, [r1, #PXA3_DDR_HCAL]

	ldr	r0, [r1, #PXA3_DMCIER]		@ Clear the interrupt
	bic	r0, r0, #0x20000000
	str	r0, [r1, #PXA3_DMCIER]

	ret	lr
ENTRY(pm_enter_standby_end)

#endif
Commit	Line	Data
0fdebc5e	1	/* SPDX-License-Identifier: GPL-2.0-only */
26705ca4 TP	2	/*
	3	* PXA27x standby mode
	4	*
	5	* Author: David Burrage
	6	*
0fdebc5e	7	* 2005 (c) MontaVista Software, Inc.
26705ca4 TP	8	*/
26705ca4 TP	9
26705ca4 TP	10	#include <linux/linkage.h>
26705ca4 TP	11	#include <asm/assembler.h>
26705ca4	12
e6acc406	13	#include "pxa2xx-regs.h"
26705ca4 TP	14
	15	.text
	16
533462fb	17	#ifdef CONFIG_PXA27x
26705ca4 TP	18	ENTRY(pxa_cpu_standby)
	19	ldr r0, =PSSR
	20	mov r1, #(PSSR_PH \| PSSR_STS)
80a18573	21	mov r2, #PWRMODE_STANDBY
26705ca4 TP	22	mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
	23	ldr ip, [r3]
	24	b 1f
	25
	26	.align 5
	27	1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
	28	str r1, [r0] @ make sure PSSR_PH/STS are clear
6ebbf2ce	29	ret lr
533462fb RK	30
533462fb RK	31	#endif
7b5dea12 RK	32
	33	#ifdef CONFIG_PXA3xx
	34
ffdf7862 RK	35	#define PXA3_MDCNFG 0x0000
	36	#define PXA3_MDCNFG_DMCEN (1 << 30)
	37	#define PXA3_DDR_HCAL 0x0060
	38	#define PXA3_DDR_HCAL_HCRNG 0x1f
	39	#define PXA3_DDR_HCAL_HCPROG (1 << 28)
	40	#define PXA3_DDR_HCAL_HCEN (1 << 31)
	41	#define PXA3_DMCIER 0x0070
	42	#define PXA3_DMCIER_EDLP (1 << 29)
	43	#define PXA3_DMCISR 0x0078
	44	#define PXA3_RCOMP 0x0100
	45	#define PXA3_RCOMP_SWEVAL (1 << 31)
7b5dea12 RK	46
7b5dea12 RK	47	ENTRY(pm_enter_standby_start)
ffdf7862	48	mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
7b5dea12 RK	49	add r1, r1, #0x00100000
	50
	51	/*
	52	* Preload the TLB entry for accessing the dynamic memory
	53	* controller registers. Note that page table lookups will
	54	* fail until the dynamic memory controller has been
	55	* reinitialised - and that includes MMU page table walks.
	56	* This also means that only the dynamic memory controller
	57	* can be reliably accessed in the code following standby.
	58	*/
ffdf7862	59	ldr r2, [r1] @ Dummy read PXA3_MDCNFG
7b5dea12 RK	60
	61	mcr p14, 0, r0, c7, c0, 0
	62	.rept 8
	63	nop
	64	.endr
	65
ffdf7862 RK	66	ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
	67	bic r0, r0, #PXA3_DDR_HCAL_HCEN
	68	str r0, [r1, #PXA3_DDR_HCAL]
	69	1: ldr r0, [r1, #PXA3_DDR_HCAL]
	70	tst r0, #PXA3_DDR_HCAL_HCEN
7b5dea12 RK	71	bne 1b
7b5dea12 RK	72
ffdf7862 RK	73	ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
	74	orr r0, r0, #PXA3_RCOMP_SWEVAL
	75	str r0, [r1, #PXA3_RCOMP]
7b5dea12	76
ffdf7862 RK	77	mov r0, #~0 @ Clear interrupts
ffdf7862 RK	78	str r0, [r1, #PXA3_DMCISR]
7b5dea12	79
ffdf7862 RK	80	ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
	81	orr r0, r0, #PXA3_DMCIER_EDLP
	82	str r0, [r1, #PXA3_DMCIER]
7b5dea12	83
ffdf7862 RK	84	ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
	85	bic r0, r0, #PXA3_DDR_HCAL_HCRNG
	86	orr r0, r0, #PXA3_DDR_HCAL_HCEN \| PXA3_DDR_HCAL_HCPROG
	87	str r0, [r1, #PXA3_DDR_HCAL]
7b5dea12	88
ffdf7862 RK	89	1: ldr r0, [r1, #PXA3_DMCISR]
ffdf7862 RK	90	tst r0, #PXA3_DMCIER_EDLP
7b5dea12 RK	91	beq 1b
7b5dea12 RK	92
ffdf7862 RK	93	ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
	94	orr r0, r0, #PXA3_MDCNFG_DMCEN
	95	str r0, [r1, #PXA3_MDCNFG]
	96	1: ldr r0, [r1, #PXA3_MDCNFG]
	97	tst r0, #PXA3_MDCNFG_DMCEN
7b5dea12 RK	98	beq 1b
7b5dea12 RK	99
ffdf7862	100	ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
7b5dea12	101	orr r0, r0, #2 @ HCRNG
ffdf7862	102	str r0, [r1, #PXA3_DDR_HCAL]
7b5dea12	103
ffdf7862	104	ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
7b5dea12	105	bic r0, r0, #0x20000000
ffdf7862	106	str r0, [r1, #PXA3_DMCIER]
7b5dea12	107
6ebbf2ce	108	ret lr
7b5dea12 RK	109	ENTRY(pm_enter_standby_end)
	110
	111	#endif