[linux-2.6-block.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/device.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/pxa-regs.h>

#include "generic.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int get_clk_frequency_khz( int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 1);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
unsigned int get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

EXPORT_SYMBOL(get_clk_frequency_khz);
EXPORT_SYMBOL(get_memclk_frequency_10khz);
EXPORT_SYMBOL(get_lcdclk_frequency_10khz);

int pxa_cpu_pm_prepare(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_MEM:
		return 0;
	default:
		return -EINVAL;
	}
}

void pxa_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);
	extern void pxa_cpu_suspend(unsigned int);
	extern void pxa_cpu_resume(void);

	CKEN = CKEN22_MEMC | CKEN9_OSTIMER;

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	switch (state) {
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa_cpu_suspend(3);
		break;
	}
}

/*
 * device registration specific to PXA27x.
 */

static u64 pxa27x_dmamask = 0xffffffffUL;

static struct resource pxa27x_ohci_resources[] = {
	[0] = {
		.start  = 0x4C000000,
		.end    = 0x4C00ff6f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = IRQ_USBH1,
		.end    = IRQ_USBH1,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device ohci_device = {
	.name		= "pxa27x-ohci",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxa27x_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources  = ARRAY_SIZE(pxa27x_ohci_resources),
	.resource       = pxa27x_ohci_resources,
};

static struct platform_device *devices[] __initdata = {
	&ohci_device,
};

static int __init pxa27x_init(void)
{
	return platform_add_devices(devices, ARRAY_SIZE(devices));
}

subsys_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14	#include <linux/config.h>
	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/pm.h>
	19	#include <linux/device.h>
	20
	21	#include <asm/hardware.h>
	22	#include <asm/irq.h>
	23	#include <asm/arch/pxa-regs.h>
	24
	25	#include "generic.h"
	26
	27	/* Crystal clock: 13MHz */
	28	#define BASE_CLK 13000000
	29
	30	/*
	31	* Get the clock frequency as reflected by CCSR and the turbo flag.
	32	* We assume these values have been applied via a fcs.
	33	* If info is not 0 we also display the current settings.
	34	*/
	35	unsigned int get_clk_frequency_khz( int info)
	36	{
	37	unsigned long ccsr, clkcfg;
	38	unsigned int l, L, m, M, n2, N, S;
	39	int cccr_a, t, ht, b;
	40
	41	ccsr = CCSR;
	42	cccr_a = CCCR & (1 << 25);
	43
	44	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	45	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	46	t = clkcfg & (1 << 1);
	47	ht = clkcfg & (1 << 2);
	48	b = clkcfg & (1 << 3);
	49
	50	l = ccsr & 0x1f;
	51	n2 = (ccsr>>7) & 0xf;
	52	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	53
	54	L = l * BASE_CLK;
	55	N = (L * n2) / 2;
	56	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	57	S = (b) ? L : (L/2);
	58
	59	if (info) {
	60	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	61	L / 1000000, (L % 1000000) / 10000, l );
	62	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	63	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	64	(t) ? "" : "in" );
65	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
66	M / 1000000, (M % 1000000) / 10000, m );
67	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
68	S / 1000000, (S % 1000000) / 10000 );
69	}
70
71	return (t) ? (N/1000) : (L/1000);
72	}
73
74	/*
75	* Return the current mem clock frequency in units of 10kHz as
76	* reflected by CCCR[A], B, and L
77	*/
78	unsigned int get_memclk_frequency_10khz(void)
79	{
80	unsigned long ccsr, clkcfg;
81	unsigned int l, L, m, M;
82	int cccr_a, b;
83
84	ccsr = CCSR;
85	cccr_a = CCCR & (1 << 25);
86
87	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
88	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
89	b = clkcfg & (1 << 3);
90
91	l = ccsr & 0x1f;
92	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
93
94	L = l * BASE_CLK;
95	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
96
97	return (M / 10000);
98	}
99
100	/*
101	* Return the current LCD clock frequency in units of 10kHz as
102	*/
103	unsigned int get_lcdclk_frequency_10khz(void)
104	{
105	unsigned long ccsr;
106	unsigned int l, L, k, K;
107
108	ccsr = CCSR;
109
110	l = ccsr & 0x1f;
111	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
112
113	L = l * BASE_CLK;
114	K = L / k;
115
116	return (K / 10000);
117	}
118
119	EXPORT_SYMBOL(get_clk_frequency_khz);
120	EXPORT_SYMBOL(get_memclk_frequency_10khz);
121	EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
122
8775420d TP	123	int pxa_cpu_pm_prepare(suspend_state_t state)
	124	{
	125	switch (state) {
	126	case PM_SUSPEND_MEM:
	127	return 0;
	128	default:
	129	return -EINVAL;
	130	}
	131	}
	132
	133	void pxa_cpu_pm_enter(suspend_state_t state)
	134	{
	135	extern void pxa_cpu_standby(void);
	136	extern void pxa_cpu_suspend(unsigned int);
	137	extern void pxa_cpu_resume(void);
	138
	139	CKEN = CKEN22_MEMC \| CKEN9_OSTIMER;
	140
	141	/* ensure voltage-change sequencer not initiated, which hangs */
	142	PCFR &= ~PCFR_FVC;
	143
	144	/* Clear edge-detect status register. */
	145	PEDR = 0xDF12FE1B;
	146
	147	switch (state) {
	148	case PM_SUSPEND_MEM:
	149	/* set resume return address */
	150	PSPR = virt_to_phys(pxa_cpu_resume);
	151	pxa_cpu_suspend(3);
	152	break;
	153	}
	154	}
1da177e4 LT	155
	156	/*
	157	* device registration specific to PXA27x.
	158	*/
	159
	160	static u64 pxa27x_dmamask = 0xffffffffUL;
	161
	162	static struct resource pxa27x_ohci_resources[] = {
	163	[0] = {
	164	.start = 0x4C000000,
	165	.end = 0x4C00ff6f,
	166	.flags = IORESOURCE_MEM,
	167	},
	168	[1] = {
	169	.start = IRQ_USBH1,
	170	.end = IRQ_USBH1,
	171	.flags = IORESOURCE_IRQ,
	172	},
	173	};
	174
	175	static struct platform_device ohci_device = {
	176	.name = "pxa27x-ohci",
	177	.id = -1,
	178	.dev = {
	179	.dma_mask = &pxa27x_dmamask,
	180	.coherent_dma_mask = 0xffffffff,
	181	},
	182	.num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
	183	.resource = pxa27x_ohci_resources,
	184	};
	185
	186	static struct platform_device *devices[] __initdata = {
	187	&ohci_device,
	188	};
	189
	190	static int __init pxa27x_init(void)
	191	{
	192	return platform_add_devices(devices, ARRAY_SIZE(devices));
	193	}
	194
	195	subsys_initcall(pxa27x_init);