[linux-2.6-block.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/sysdev.h>

#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

/*
 * Return the current memory clock frequency in units of 10kHz
 */
unsigned int pxa25x_get_memclk_frequency_10khz(void)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
}

static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
{
	return pxa25x_get_memclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa25x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa25x_lcd_getrate,
};

/*
 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */
static struct clk pxa25x_hwuart_clk =
	INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
;

static struct clk pxa25x_clks[] = {
	INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
	INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
	INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
	INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
	INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
	INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),

	INIT_CKEN("SSPCLK",  SSP, 3686400, 0, &pxa25x_device_ssp.dev),
	INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
	INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),

	/*
	INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
	INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
	INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
	*/
	INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {	SLEEP_SAVE_START = 0,

	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,

	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,

	SLEEP_SAVE_PSTR,

	SLEEP_SAVE_CKEN,

	SLEEP_SAVE_SIZE
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);

	SAVE(GAFR0_L); SAVE(GAFR0_U);
	SAVE(GAFR1_L); SAVE(GAFR1_U);
	SAVE(GAFR2_L); SAVE(GAFR2_U);

	SAVE(CKEN);
	SAVE(PSTR);

	/* Clear GPIO transition detect bits */
	GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;

	/* restore registers */
	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa25x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_size	= SLEEP_SAVE_SIZE,
	.valid		= suspend_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#else
static inline void pxa25x_init_pm(void) {}
#endif

/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 */

static int pxa25x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t gpio_bit, mask = 0;

	if (gpio >= 0 && gpio <= 15) {
		gpio_bit = GPIO_bit(gpio);
		mask = gpio_bit;
		if (on) {
			if (GRER(gpio) | gpio_bit)
				PRER |= gpio_bit;
			else
				PRER &= ~gpio_bit;

			if (GFER(gpio) | gpio_bit)
				PFER |= gpio_bit;
			else
				PFER &= ~gpio_bit;
		}
		goto set_pwer;
	}

	if (irq == IRQ_RTCAlrm) {
		mask = PWER_RTC;
		goto set_pwer;
	}

	return -EINVAL;

set_pwer:
	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa25x_init_irq(void)
{
	pxa_init_irq_low();
	pxa_init_irq_gpio(85);
	pxa_init_irq_set_wake(pxa25x_set_wake);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa_device_udc,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&pxa_device_rtc,
	&pxa25x_device_ssp,
	&pxa25x_device_nssp,
	&pxa25x_device_assp,
};

static struct sys_device pxa25x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa25x_init(void)
{
	int i, ret = 0;

	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	if (cpu_is_pxa25x())
		clks_register(&pxa25x_hwuart_clk, 1);

	if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
		clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));

		if ((ret = pxa_init_dma(16)))
			return ret;

		pxa25x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
			ret = sysdev_register(&pxa25x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
		if (ret)
			return ret;
	}

	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	if (cpu_is_pxa25x())
		ret = platform_device_register(&pxa_device_hwuart);

	return ret;
}

subsys_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
34f3231f	22	#include <linux/platform_device.h>
95d9ffbe	23	#include <linux/suspend.h>
c0165504	24	#include <linux/sysdev.h>
1da177e4 LT	25
1da177e4 LT	26	#include <asm/hardware.h>
cd49104d	27	#include <asm/arch/irqs.h>
1da177e4	28	#include <asm/arch/pxa-regs.h>
e176bb05	29	#include <asm/arch/pm.h>
f53f066c	30	#include <asm/arch/dma.h>
1da177e4 LT	31
1da177e4 LT	32	#include "generic.h"
46c41e62	33	#include "devices.h"
a6dba20c	34	#include "clock.h"
1da177e4 LT	35
	36	/*
	37	* Various clock factors driven by the CCCR register.
	38	*/
	39
	40	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	41	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	42
	43	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	44	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	45
	46	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	47	/* Note: we store the value N * 2 here. */
	48	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	49
	50	/* Crystal clock */
	51	#define BASE_CLK 3686400
	52
	53	/*
	54	* Get the clock frequency as reflected by CCCR and the turbo flag.
	55	* We assume these values have been applied via a fcs.
	56	* If info is not 0 we also display the current settings.
	57	*/
15a40333	58	unsigned int pxa25x_get_clk_frequency_khz(int info)
1da177e4 LT	59	{
	60	unsigned long cccr, turbo;
	61	unsigned int l, L, m, M, n2, N;
	62
	63	cccr = CCCR;
	64	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	65
	66	l = L_clk_mult[(cccr >> 0) & 0x1f];
	67	m = M_clk_mult[(cccr >> 5) & 0x03];
	68	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	69
	70	L = l * BASE_CLK;
	71	M = m * L;
	72	N = n2 * M / 2;
	73
	74	if(info)
	75	{
	76	L += 5000;
	77	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	78	L / 1000000, (L % 1000000) / 10000, l );
	79	M += 5000;
	80	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	81	M / 1000000, (M % 1000000) / 10000, m );
	82	N += 5000;
	83	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	84	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	85	(turbo & 1) ? "" : "in" );
	86	}
	87
	88	return (turbo & 1) ? (N/1000) : (M/1000);
	89	}
	90
1da177e4 LT	91	/*
	92	* Return the current memory clock frequency in units of 10kHz
	93	*/
15a40333	94	unsigned int pxa25x_get_memclk_frequency_10khz(void)
1da177e4 LT	95	{
	96	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
	97	}
	98
a6dba20c RK	99	static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
	100	{
	101	return pxa25x_get_memclk_frequency_10khz() * 10000;
	102	}
	103
	104	static const struct clkops clk_pxa25x_lcd_ops = {
	105	.enable = clk_cken_enable,
	106	.disable = clk_cken_disable,
	107	.getrate = clk_pxa25x_lcd_getrate,
	108	};
	109
	110	/*
	111	* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
	112	* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
	113	* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
	114	*/
e01dbdb4 DB	115	static struct clk pxa25x_hwuart_clk =
	116	INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
	117	;
	118
a6dba20c RK	119	static struct clk pxa25x_clks[] = {
	120	INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
	121	INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
	122	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
435b6e94	123	INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
a6dba20c RK	124	INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
	125	INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
	126	INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
d8e0db11	127
	128	INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
	129	INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
	130	INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
	131
a6dba20c RK	132	/*
	133	INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
	134	INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
a6dba20c	135	INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
a6dba20c	136	*/
435b6e94	137	INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
a6dba20c RK	138	};
a6dba20c RK	139
a8fa3f0c	140	#ifdef CONFIG_PM
8775420d	141
711be5cc EM	142	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	143	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	144
711be5cc EM	145	/*
	146	* List of global PXA peripheral registers to preserve.
	147	* More ones like CP and general purpose register values are preserved
	148	* with the stack pointer in sleep.S.
	149	*/
	150	enum { SLEEP_SAVE_START = 0,
	151
711be5cc EM	152	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
	153
	154	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	155	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	156	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
	157
	158	SLEEP_SAVE_PSTR,
	159
711be5cc EM	160	SLEEP_SAVE_CKEN,
	161
	162	SLEEP_SAVE_SIZE
	163	};
	164
	165
	166	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	167	{
711be5cc EM	168	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
	169
	170	SAVE(GAFR0_L); SAVE(GAFR0_U);
	171	SAVE(GAFR1_L); SAVE(GAFR1_U);
	172	SAVE(GAFR2_L); SAVE(GAFR2_U);
	173
711be5cc EM	174	SAVE(CKEN);
711be5cc EM	175	SAVE(PSTR);
56b11288 RP	176
	177	/* Clear GPIO transition detect bits */
	178	GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
711be5cc EM	179	}
	180
	181	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	182	{
56b11288 RP	183	/* ensure not to come back here if it wasn't intended */
	184	PSPR = 0;
	185
711be5cc	186	/* restore registers */
711be5cc EM	187	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	188	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	189	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
711be5cc EM	190	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
711be5cc EM	191
56b11288 RP	192	PSSR = PSSR_RDH \| PSSR_PH;
56b11288 RP	193
711be5cc	194	RESTORE(CKEN);
711be5cc EM	195	RESTORE(PSTR);
	196	}
	197
	198	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d	199	{
8775420d TP	200	switch (state) {
	201	case PM_SUSPEND_MEM:
	202	/* set resume return address */
	203	PSPR = virt_to_phys(pxa_cpu_resume);
b750a093	204	pxa25x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	205	break;
	206	}
	207	}
a8fa3f0c	208
711be5cc EM	209	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
711be5cc EM	210	.save_size = SLEEP_SAVE_SIZE,
26398a70	211	.valid = suspend_valid_only_mem,
711be5cc EM	212	.save = pxa25x_cpu_pm_save,
	213	.restore = pxa25x_cpu_pm_restore,
	214	.enter = pxa25x_cpu_pm_enter,
e176bb05	215	};
711be5cc EM	216
	217	static void __init pxa25x_init_pm(void)
	218	{
	219	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	220	}
f79299ca	221	#else
f79299ca	222	static inline void pxa25x_init_pm(void) {}
a8fa3f0c	223	#endif
e176bb05	224
c95530c7	225	/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
	226	*/
	227
	228	static int pxa25x_set_wake(unsigned int irq, unsigned int on)
	229	{
	230	int gpio = IRQ_TO_GPIO(irq);
	231	uint32_t gpio_bit, mask = 0;
	232
	233	if (gpio >= 0 && gpio <= 15) {
	234	gpio_bit = GPIO_bit(gpio);
	235	mask = gpio_bit;
	236	if (on) {
	237	if (GRER(gpio) \| gpio_bit)
	238	PRER \|= gpio_bit;
	239	else
	240	PRER &= ~gpio_bit;
	241
	242	if (GFER(gpio) \| gpio_bit)
	243	PFER \|= gpio_bit;
	244	else
	245	PFER &= ~gpio_bit;
	246	}
	247	goto set_pwer;
	248	}
	249
	250	if (irq == IRQ_RTCAlrm) {
	251	mask = PWER_RTC;
	252	goto set_pwer;
	253	}
	254
	255	return -EINVAL;
	256
	257	set_pwer:
	258	if (on)
	259	PWER \|= mask;
	260	else
	261	PWER &=~mask;
	262
	263	return 0;
	264	}
	265
cd49104d EM	266	void __init pxa25x_init_irq(void)
	267	{
	268	pxa_init_irq_low();
	269	pxa_init_irq_gpio(85);
c95530c7	270	pxa_init_irq_set_wake(pxa25x_set_wake);
cd49104d EM	271	}
cd49104d EM	272
34f3231f	273	static struct platform_device *pxa25x_devices[] __initdata = {
e09d02e1	274	&pxa_device_udc,
e09d02e1 EM	275	&pxa_device_ffuart,
	276	&pxa_device_btuart,
	277	&pxa_device_stuart,
e09d02e1	278	&pxa_device_i2s,
e09d02e1	279	&pxa_device_rtc,
d8e0db11	280	&pxa25x_device_ssp,
	281	&pxa25x_device_nssp,
	282	&pxa25x_device_assp,
34f3231f RK	283	};
34f3231f RK	284
c0165504	285	static struct sys_device pxa25x_sysdev[] = {
	286	{
	287	.cls = &pxa_irq_sysclass,
16dfdbf0	288	}, {
16dfdbf0	289	.cls = &pxa_gpio_sysclass,
c0165504	290	},
	291	};
	292
e176bb05 RK	293	static int __init pxa25x_init(void)
e176bb05 RK	294	{
c0165504	295	int i, ret = 0;
f53f066c	296
e01dbdb4 DB	297	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	298	if (cpu_is_pxa25x())
	299	clks_register(&pxa25x_hwuart_clk, 1);
	300
e176bb05	301	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) {
a6dba20c RK	302	clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
a6dba20c RK	303
f53f066c EM	304	if ((ret = pxa_init_dma(16)))
f53f066c EM	305	return ret;
f79299ca	306
711be5cc	307	pxa25x_init_pm();
f79299ca	308
c0165504	309	for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
	310	ret = sysdev_register(&pxa25x_sysdev[i]);
	311	if (ret)
	312	pr_err("failed to register sysdev[%d]\n", i);
	313	}
	314
34f3231f RK	315	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	316	ARRAY_SIZE(pxa25x_devices));
c0165504	317	if (ret)
c0165504	318	return ret;
e176bb05	319	}
c0165504	320
34f3231f RK	321	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
34f3231f RK	322	if (cpu_is_pxa25x())
e09d02e1	323	ret = platform_device_register(&pxa_device_hwuart);
34f3231f RK	324
34f3231f RK	325	return ret;
e176bb05 RK	326	}
	327
	328	subsys_initcall(pxa25x_init);