projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[ARM] pxa: add keypad support for zylonite
[linux-2.6-block.git] / arch / arm / mach-pxa / littleton.c
CommitLineData
e1d9b953 1/*
2 * linux/arch/arm/mach-pxa/littleton.c
3 *
4 * Support for the Marvell Littleton Development Platform.
5 *
6 * Author: Jason Chagas (largely modified code)
7 * Created: Nov 20, 2006
8 * Copyright: (C) Copyright 2006 Marvell International Ltd.
9 *
10 * 2007-11-22 modified to align with latest kernel
11 * eric miao <eric.miao@marvell.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * publishhed by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23
24#include <asm/types.h>
25#include <asm/setup.h>
26#include <asm/memory.h>
27#include <asm/mach-types.h>
28#include <asm/hardware.h>
29#include <asm/irq.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <asm/arch/pxa-regs.h>
36#include <asm/arch/mfp-pxa300.h>
37#include <asm/arch/gpio.h>
38#include <asm/arch/pxafb.h>
39#include <asm/arch/ssp.h>
40#include <asm/arch/littleton.h>
41
42#include "generic.h"
43
e1d9b953 44/* Littleton MFP configurations */
45static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
46 /* LCD */
47 GPIO54_LCD_LDD_0,
48 GPIO55_LCD_LDD_1,
49 GPIO56_LCD_LDD_2,
50 GPIO57_LCD_LDD_3,
51 GPIO58_LCD_LDD_4,
52 GPIO59_LCD_LDD_5,
53 GPIO60_LCD_LDD_6,
54 GPIO61_LCD_LDD_7,
55 GPIO62_LCD_LDD_8,
56 GPIO63_LCD_LDD_9,
57 GPIO64_LCD_LDD_10,
58 GPIO65_LCD_LDD_11,
59 GPIO66_LCD_LDD_12,
60 GPIO67_LCD_LDD_13,
61 GPIO68_LCD_LDD_14,
62 GPIO69_LCD_LDD_15,
63 GPIO70_LCD_LDD_16,
64 GPIO71_LCD_LDD_17,
65 GPIO72_LCD_FCLK,
66 GPIO73_LCD_LCLK,
67 GPIO74_LCD_PCLK,
68 GPIO75_LCD_BIAS,
69
70 /* SSP2 */
71 GPIO25_SSP2_SCLK,
72 GPIO17_SSP2_FRM,
73 GPIO27_SSP2_TXD,
74
75 /* Debug Ethernet */
76 GPIO90_GPIO,
77};
78
79static struct resource smc91x_resources[] = {
80 [0] = {
81 .start = (LITTLETON_ETH_PHYS + 0x300),
82 .end = (LITTLETON_ETH_PHYS + 0xfffff),
83 .flags = IORESOURCE_MEM,
84 },
85 [1] = {
86 .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
87 .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
e7b3dc7e 88 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
e1d9b953 89 }
90};
91
92static struct platform_device smc91x_device = {
93 .name = "smc91x",
94 .id = 0,
95 .num_resources = ARRAY_SIZE(smc91x_resources),
96 .resource = smc91x_resources,
97};
98
99#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULES)
100/* use bit 30, 31 as the indicator of command parameter number */
101#define CMD0(x) ((0x00000000) | ((x) << 9))
102#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1))
103#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\
104 ((x1) << 9) | 0x100 | (x2))
105
106static uint32_t lcd_panel_reset[] = {
107 CMD0(0x1), /* reset */
108 CMD0(0x0), /* nop */
109 CMD0(0x0), /* nop */
110 CMD0(0x0), /* nop */
111};
112
113static uint32_t lcd_panel_on[] = {
114 CMD0(0x29), /* Display ON */
115 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
116 CMD0(0x11), /* Sleep out */
117 CMD1(0xB0, 0x16), /* Wake */
118};
119
120static uint32_t lcd_panel_off[] = {
121 CMD0(0x28), /* Display OFF */
122 CMD2(0xB8, 0x80, 0x02), /* Output Control */
123 CMD0(0x10), /* Sleep in */
124 CMD1(0xB0, 0x00), /* Deep stand by in */
125};
126
127static uint32_t lcd_vga_pass_through[] = {
128 CMD1(0xB0, 0x16),
129 CMD1(0xBC, 0x80),
130 CMD1(0xE1, 0x00),
131 CMD1(0x36, 0x50),
132 CMD1(0x3B, 0x00),
133};
134
135static uint32_t lcd_qvga_pass_through[] = {
136 CMD1(0xB0, 0x16),
137 CMD1(0xBC, 0x81),
138 CMD1(0xE1, 0x00),
139 CMD1(0x36, 0x50),
140 CMD1(0x3B, 0x22),
141};
142
143static uint32_t lcd_vga_transfer[] = {
144 CMD1(0xcf, 0x02), /* Blanking period control (1) */
145 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
146 CMD1(0xd1, 0x01), /* CKV timing control on/off */
147 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
148 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
149 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
150 CMD1(0xd5, 0x14), /* ASW timing control (2) */
151 CMD0(0x21), /* Invert for normally black display */
152 CMD0(0x29), /* Display on */
153};
154
155static uint32_t lcd_qvga_transfer[] = {
156 CMD1(0xd6, 0x02), /* Blanking period control (1) */
157 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
158 CMD1(0xd8, 0x01), /* CKV timing control on/off */
159 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
160 CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
161 CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
162 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
163 CMD0(0x21), /* Invert for normally black display */
164 CMD0(0x29), /* Display on */
165};
166
167static uint32_t lcd_panel_config[] = {
168 CMD2(0xb8, 0xff, 0xf9), /* Output control */
169 CMD0(0x11), /* sleep out */
170 CMD1(0xba, 0x01), /* Display mode (1) */
171 CMD1(0xbb, 0x00), /* Display mode (2) */
172 CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
173 CMD1(0xbf, 0x10), /* Drive system change control */
174 CMD1(0xb1, 0x56), /* Booster operation setup */
175 CMD1(0xb2, 0x33), /* Booster mode setup */
176 CMD1(0xb3, 0x11), /* Booster frequency setup */
177 CMD1(0xb4, 0x02), /* Op amp/system clock */
178 CMD1(0xb5, 0x35), /* VCS voltage */
179 CMD1(0xb6, 0x40), /* VCOM voltage */
180 CMD1(0xb7, 0x03), /* External display signal */
181 CMD1(0xbd, 0x00), /* ASW slew rate */
182 CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
183 CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
184 CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
185 CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
186 CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
187 CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
188 CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
189 CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
190 CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
191 CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
192 CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
193 CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
194 CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
195};
196
197static void ssp_reconfig(struct ssp_dev *dev, int nparam)
198{
199 static int last_nparam = -1;
200
201 /* check if it is necessary to re-config SSP */
202 if (nparam == last_nparam)
203 return;
204
205 ssp_disable(dev);
206 ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0);
207
208 last_nparam = nparam;
209}
210
211static void ssp_send_cmd(uint32_t *cmd, int num)
212{
213 static int ssp_initialized;
214 static struct ssp_dev ssp2;
215
216 int i;
217
218 if (!ssp_initialized) {
219 ssp_init(&ssp2, 2, SSP_NO_IRQ);
220 ssp_initialized = 1;
221 }
222
223 clk_enable(ssp2.ssp->clk);
224 for (i = 0; i < num; i++, cmd++) {
225 ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3);
226 ssp_write_word(&ssp2, *cmd & 0x3fffffff);
227
228 /* FIXME: ssp_flush() is mandatory here to work */
229 ssp_flush(&ssp2);
230 }
231 clk_disable(ssp2.ssp->clk);
232}
233
234static void littleton_lcd_power(int on, struct fb_var_screeninfo *var)
235{
236 if (on) {
237 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on));
238 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset));
239 if (var->xres > 240) {
240 /* VGA */
241 ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through));
242 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
243 ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer));
244 } else {
245 /* QVGA */
246 ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through));
247 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
248 ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer));
249 }
250 } else
251 ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off));
252}
253
254static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
255 [0] = {
256 /* VGA */
257 .pixclock = 38250,
258 .xres = 480,
259 .yres = 640,
260 .bpp = 16,
261 .hsync_len = 8,
262 .left_margin = 8,
263 .right_margin = 24,
264 .vsync_len = 2,
265 .upper_margin = 2,
266 .lower_margin = 4,
267 .sync = 0,
268 },
269 [1] = {
270 /* QVGA */
271 .pixclock = 153000,
272 .xres = 240,
273 .yres = 320,
274 .bpp = 16,
275 .hsync_len = 8,
276 .left_margin = 8,
277 .right_margin = 88,
278 .vsync_len = 2,
279 .upper_margin = 2,
280 .lower_margin = 2,
281 .sync = 0,
282 },
283};
284
285static struct pxafb_mach_info littleton_lcd_info = {
286 .modes = tpo_tdo24mtea1_modes,
287 .num_modes = 2,
288 .lccr0 = LCCR0_Act,
289 .lccr3 = LCCR3_HSP | LCCR3_VSP,
290 .pxafb_lcd_power = littleton_lcd_power,
291};
292
293static void littleton_init_lcd(void)
294{
295 set_pxa_fb_info(&littleton_lcd_info);
296}
297#else
298static inline void littleton_init_lcd(void) {};
299#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
300
301static void __init littleton_init(void)
302{
303 /* initialize MFP configurations */
304 pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));
305
306 /*
307 * Note: we depend bootloader set the correct
308 * value to MSC register for SMC91x.
309 */
310 platform_device_register(&smc91x_device);
311
312 littleton_init_lcd();
313}
314
315MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
316 .phys_io = 0x40000000,
317 .boot_params = 0xa0000100,
318 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
319 .map_io = pxa_map_io,
320 .init_irq = pxa3xx_init_irq,
321 .timer = &pxa_timer,
322 .init_machine = littleton_init,
323MACHINE_END
Linux 6.x block layer and io_uring tree(s)