Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/irq.c | |
3 | * | |
e3630db1 | 4 | * Generic PXA IRQ handling |
1da177e4 LT |
5 | * |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
c0165504 | 18 | #include <linux/sysdev.h> |
a79a9ad9 HZ |
19 | #include <linux/io.h> |
20 | #include <linux/irq.h> | |
1da177e4 | 21 | |
a09e64fb | 22 | #include <mach/hardware.h> |
a79a9ad9 | 23 | #include <mach/irqs.h> |
a58fbcd8 | 24 | #include <mach/gpio.h> |
1da177e4 LT |
25 | |
26 | #include "generic.h" | |
27 | ||
a79a9ad9 HZ |
28 | #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) |
29 | ||
30 | #define ICIP (0x000) | |
31 | #define ICMR (0x004) | |
32 | #define ICLR (0x008) | |
33 | #define ICFR (0x00c) | |
34 | #define ICPR (0x010) | |
35 | #define ICCR (0x014) | |
36 | #define ICHP (0x018) | |
37 | #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ | |
38 | ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ | |
39 | (0x144 + (((i) - 64) << 2))) | |
40 | #define IPR_VALID (1 << 31) | |
41 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) | |
c482ae4d | 42 | |
a79a9ad9 | 43 | #define MAX_INTERNAL_IRQS 128 |
1da177e4 LT |
44 | |
45 | /* | |
46 | * This is for peripheral IRQs internal to the PXA chip. | |
47 | */ | |
48 | ||
f6fb7af4 | 49 | static int pxa_internal_irq_nr; |
50 | ||
bb71bdd3 HZ |
51 | static inline int cpu_has_ipr(void) |
52 | { | |
53 | return !cpu_is_pxa25x(); | |
54 | } | |
55 | ||
a3f4c927 | 56 | static void pxa_mask_irq(struct irq_data *d) |
1da177e4 | 57 | { |
a3f4c927 | 58 | void __iomem *base = irq_data_get_irq_chip_data(d); |
a79a9ad9 HZ |
59 | uint32_t icmr = __raw_readl(base + ICMR); |
60 | ||
a3f4c927 | 61 | icmr &= ~(1 << IRQ_BIT(d->irq)); |
a79a9ad9 | 62 | __raw_writel(icmr, base + ICMR); |
1da177e4 LT |
63 | } |
64 | ||
a3f4c927 | 65 | static void pxa_unmask_irq(struct irq_data *d) |
1da177e4 | 66 | { |
a3f4c927 | 67 | void __iomem *base = irq_data_get_irq_chip_data(d); |
a79a9ad9 HZ |
68 | uint32_t icmr = __raw_readl(base + ICMR); |
69 | ||
a3f4c927 | 70 | icmr |= 1 << IRQ_BIT(d->irq); |
a79a9ad9 | 71 | __raw_writel(icmr, base + ICMR); |
1da177e4 LT |
72 | } |
73 | ||
f6fb7af4 | 74 | static struct irq_chip pxa_internal_irq_chip = { |
38c677cb | 75 | .name = "SC", |
a3f4c927 LB |
76 | .irq_ack = pxa_mask_irq, |
77 | .irq_mask = pxa_mask_irq, | |
78 | .irq_unmask = pxa_unmask_irq, | |
1da177e4 LT |
79 | }; |
80 | ||
a58fbcd8 EM |
81 | /* |
82 | * GPIO IRQs for GPIO 0 and 1 | |
83 | */ | |
a3f4c927 | 84 | static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) |
a58fbcd8 | 85 | { |
a3f4c927 | 86 | int gpio = d->irq - IRQ_GPIO0; |
a58fbcd8 EM |
87 | |
88 | if (__gpio_is_occupied(gpio)) { | |
89 | pr_err("%s failed: GPIO is configured\n", __func__); | |
90 | return -EINVAL; | |
91 | } | |
92 | ||
93 | if (type & IRQ_TYPE_EDGE_RISING) | |
94 | GRER0 |= GPIO_bit(gpio); | |
95 | else | |
96 | GRER0 &= ~GPIO_bit(gpio); | |
97 | ||
98 | if (type & IRQ_TYPE_EDGE_FALLING) | |
99 | GFER0 |= GPIO_bit(gpio); | |
100 | else | |
101 | GFER0 &= ~GPIO_bit(gpio); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
a3f4c927 | 106 | static void pxa_ack_low_gpio(struct irq_data *d) |
a58fbcd8 | 107 | { |
a3f4c927 | 108 | GEDR0 = (1 << (d->irq - IRQ_GPIO0)); |
a58fbcd8 EM |
109 | } |
110 | ||
a3f4c927 | 111 | static void pxa_mask_low_gpio(struct irq_data *d) |
a58fbcd8 | 112 | { |
a3f4c927 | 113 | struct irq_desc *desc = irq_to_desc(d->irq); |
a79a9ad9 | 114 | |
a3f4c927 | 115 | desc->irq_data.chip->irq_mask(d); |
a58fbcd8 EM |
116 | } |
117 | ||
a3f4c927 | 118 | static void pxa_unmask_low_gpio(struct irq_data *d) |
a58fbcd8 | 119 | { |
a3f4c927 | 120 | struct irq_desc *desc = irq_to_desc(d->irq); |
a79a9ad9 | 121 | |
a3f4c927 | 122 | desc->irq_data.chip->irq_unmask(d); |
a58fbcd8 EM |
123 | } |
124 | ||
125 | static struct irq_chip pxa_low_gpio_chip = { | |
126 | .name = "GPIO-l", | |
a3f4c927 LB |
127 | .irq_ack = pxa_ack_low_gpio, |
128 | .irq_mask = pxa_mask_low_gpio, | |
129 | .irq_unmask = pxa_unmask_low_gpio, | |
130 | .irq_set_type = pxa_set_low_gpio_type, | |
a58fbcd8 EM |
131 | }; |
132 | ||
133 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |
134 | { | |
135 | int irq; | |
136 | ||
137 | /* clear edge detection on GPIO 0 and 1 */ | |
138 | GFER0 &= ~0x3; | |
139 | GRER0 &= ~0x3; | |
140 | GEDR0 = 0x3; | |
141 | ||
142 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | |
143 | set_irq_chip(irq, &pxa_low_gpio_chip); | |
144 | set_irq_handler(irq, handle_edge_irq); | |
145 | set_irq_flags(irq, IRQF_VALID); | |
146 | } | |
147 | ||
a3f4c927 | 148 | pxa_low_gpio_chip.irq_set_wake = fn; |
a58fbcd8 EM |
149 | } |
150 | ||
a79a9ad9 HZ |
151 | static inline void __iomem *irq_base(int i) |
152 | { | |
153 | static unsigned long phys_base[] = { | |
154 | 0x40d00000, | |
155 | 0x40d0009c, | |
156 | 0x40d00130, | |
157 | }; | |
158 | ||
1b624fb6 | 159 | return (void __iomem *)io_p2v(phys_base[i]); |
a79a9ad9 HZ |
160 | } |
161 | ||
b9e25ace | 162 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
53665a50 | 163 | { |
a79a9ad9 | 164 | int irq, i, n; |
53665a50 | 165 | |
c482ae4d HZ |
166 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); |
167 | ||
f6fb7af4 | 168 | pxa_internal_irq_nr = irq_nr; |
53665a50 | 169 | |
a79a9ad9 | 170 | for (n = 0; n < irq_nr; n += 32) { |
1b624fb6 | 171 | void __iomem *base = irq_base(n >> 5); |
a79a9ad9 HZ |
172 | |
173 | __raw_writel(0, base + ICMR); /* disable all IRQs */ | |
174 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | |
175 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { | |
176 | /* initialize interrupt priority */ | |
177 | if (cpu_has_ipr()) | |
178 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); | |
179 | ||
180 | irq = PXA_IRQ(i); | |
181 | set_irq_chip(irq, &pxa_internal_irq_chip); | |
182 | set_irq_chip_data(irq, base); | |
183 | set_irq_handler(irq, handle_level_irq); | |
184 | set_irq_flags(irq, IRQF_VALID); | |
185 | } | |
d2c37068 HZ |
186 | } |
187 | ||
53665a50 | 188 | /* only unmasked interrupts kick us out of idle */ |
a79a9ad9 | 189 | __raw_writel(1, irq_base(0) + ICCR); |
1da177e4 | 190 | |
a3f4c927 | 191 | pxa_internal_irq_chip.irq_set_wake = fn; |
a58fbcd8 | 192 | pxa_init_low_gpio_irq(fn); |
c95530c7 | 193 | } |
c0165504 | 194 | |
195 | #ifdef CONFIG_PM | |
c482ae4d HZ |
196 | static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; |
197 | static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; | |
c0165504 | 198 | |
199 | static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | |
200 | { | |
a79a9ad9 HZ |
201 | int i; |
202 | ||
1b624fb6 | 203 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
a79a9ad9 | 204 | void __iomem *base = irq_base(i); |
f6fb7af4 | 205 | |
a79a9ad9 HZ |
206 | saved_icmr[i] = __raw_readl(base + ICMR); |
207 | __raw_writel(0, base + ICMR); | |
c0165504 | 208 | } |
c70f5a60 | 209 | |
bb71bdd3 | 210 | if (cpu_has_ipr()) { |
c70f5a60 | 211 | for (i = 0; i < pxa_internal_irq_nr; i++) |
a79a9ad9 | 212 | saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); |
c70f5a60 | 213 | } |
c0165504 | 214 | |
215 | return 0; | |
216 | } | |
217 | ||
218 | static int pxa_irq_resume(struct sys_device *dev) | |
219 | { | |
a79a9ad9 | 220 | int i; |
f6fb7af4 | 221 | |
1b624fb6 | 222 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
a79a9ad9 | 223 | void __iomem *base = irq_base(i); |
c70f5a60 | 224 | |
a79a9ad9 HZ |
225 | __raw_writel(saved_icmr[i], base + ICMR); |
226 | __raw_writel(0, base + ICLR); | |
c0165504 | 227 | } |
228 | ||
57879b8c | 229 | if (cpu_has_ipr()) |
a79a9ad9 HZ |
230 | for (i = 0; i < pxa_internal_irq_nr; i++) |
231 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); | |
232 | ||
233 | __raw_writel(1, IRQ_BASE + ICCR); | |
c0165504 | 234 | return 0; |
235 | } | |
236 | #else | |
237 | #define pxa_irq_suspend NULL | |
238 | #define pxa_irq_resume NULL | |
239 | #endif | |
240 | ||
241 | struct sysdev_class pxa_irq_sysclass = { | |
242 | .name = "irq", | |
243 | .suspend = pxa_irq_suspend, | |
244 | .resume = pxa_irq_resume, | |
245 | }; | |
246 | ||
247 | static int __init pxa_irq_init(void) | |
248 | { | |
249 | return sysdev_class_register(&pxa_irq_sysclass); | |
250 | } | |
251 | ||
252 | core_initcall(pxa_irq_init); |