Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/irq.c | |
3 | * | |
e3630db1 | 4 | * Generic PXA IRQ handling |
1da177e4 LT |
5 | * |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/interrupt.h> | |
2eaa03b5 | 17 | #include <linux/syscore_ops.h> |
a79a9ad9 HZ |
18 | #include <linux/io.h> |
19 | #include <linux/irq.h> | |
1da177e4 | 20 | |
5a567d78 JI |
21 | #include <asm/exception.h> |
22 | ||
a09e64fb | 23 | #include <mach/hardware.h> |
a79a9ad9 | 24 | #include <mach/irqs.h> |
f55be1bf | 25 | #include <mach/gpio-pxa.h> |
1da177e4 LT |
26 | |
27 | #include "generic.h" | |
28 | ||
97b09da4 | 29 | #define IRQ_BASE io_p2v(0x40d00000) |
a79a9ad9 HZ |
30 | |
31 | #define ICIP (0x000) | |
32 | #define ICMR (0x004) | |
33 | #define ICLR (0x008) | |
34 | #define ICFR (0x00c) | |
35 | #define ICPR (0x010) | |
36 | #define ICCR (0x014) | |
37 | #define ICHP (0x018) | |
38 | #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ | |
39 | ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ | |
40 | (0x144 + (((i) - 64) << 2))) | |
a551e4f7 EM |
41 | #define ICHP_VAL_IRQ (1 << 31) |
42 | #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) | |
a79a9ad9 HZ |
43 | #define IPR_VALID (1 << 31) |
44 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) | |
c482ae4d | 45 | |
a79a9ad9 | 46 | #define MAX_INTERNAL_IRQS 128 |
1da177e4 LT |
47 | |
48 | /* | |
49 | * This is for peripheral IRQs internal to the PXA chip. | |
50 | */ | |
51 | ||
f6fb7af4 | 52 | static int pxa_internal_irq_nr; |
53 | ||
bb71bdd3 HZ |
54 | static inline int cpu_has_ipr(void) |
55 | { | |
56 | return !cpu_is_pxa25x(); | |
57 | } | |
58 | ||
a1015a15 EM |
59 | static inline void __iomem *irq_base(int i) |
60 | { | |
61 | static unsigned long phys_base[] = { | |
62 | 0x40d00000, | |
63 | 0x40d0009c, | |
64 | 0x40d00130, | |
65 | }; | |
66 | ||
97b09da4 | 67 | return io_p2v(phys_base[i]); |
a1015a15 EM |
68 | } |
69 | ||
5d284e35 | 70 | void pxa_mask_irq(struct irq_data *d) |
1da177e4 | 71 | { |
a3f4c927 | 72 | void __iomem *base = irq_data_get_irq_chip_data(d); |
a79a9ad9 HZ |
73 | uint32_t icmr = __raw_readl(base + ICMR); |
74 | ||
a3f4c927 | 75 | icmr &= ~(1 << IRQ_BIT(d->irq)); |
a79a9ad9 | 76 | __raw_writel(icmr, base + ICMR); |
1da177e4 LT |
77 | } |
78 | ||
5d284e35 | 79 | void pxa_unmask_irq(struct irq_data *d) |
1da177e4 | 80 | { |
a3f4c927 | 81 | void __iomem *base = irq_data_get_irq_chip_data(d); |
a79a9ad9 HZ |
82 | uint32_t icmr = __raw_readl(base + ICMR); |
83 | ||
a3f4c927 | 84 | icmr |= 1 << IRQ_BIT(d->irq); |
a79a9ad9 | 85 | __raw_writel(icmr, base + ICMR); |
1da177e4 LT |
86 | } |
87 | ||
f6fb7af4 | 88 | static struct irq_chip pxa_internal_irq_chip = { |
38c677cb | 89 | .name = "SC", |
a3f4c927 LB |
90 | .irq_ack = pxa_mask_irq, |
91 | .irq_mask = pxa_mask_irq, | |
92 | .irq_unmask = pxa_unmask_irq, | |
1da177e4 LT |
93 | }; |
94 | ||
a58fbcd8 EM |
95 | /* |
96 | * GPIO IRQs for GPIO 0 and 1 | |
97 | */ | |
a3f4c927 | 98 | static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) |
a58fbcd8 | 99 | { |
a3f4c927 | 100 | int gpio = d->irq - IRQ_GPIO0; |
a58fbcd8 EM |
101 | |
102 | if (__gpio_is_occupied(gpio)) { | |
103 | pr_err("%s failed: GPIO is configured\n", __func__); | |
104 | return -EINVAL; | |
105 | } | |
106 | ||
107 | if (type & IRQ_TYPE_EDGE_RISING) | |
108 | GRER0 |= GPIO_bit(gpio); | |
109 | else | |
110 | GRER0 &= ~GPIO_bit(gpio); | |
111 | ||
112 | if (type & IRQ_TYPE_EDGE_FALLING) | |
113 | GFER0 |= GPIO_bit(gpio); | |
114 | else | |
115 | GFER0 &= ~GPIO_bit(gpio); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
a3f4c927 | 120 | static void pxa_ack_low_gpio(struct irq_data *d) |
a58fbcd8 | 121 | { |
a3f4c927 | 122 | GEDR0 = (1 << (d->irq - IRQ_GPIO0)); |
a58fbcd8 EM |
123 | } |
124 | ||
a58fbcd8 EM |
125 | static struct irq_chip pxa_low_gpio_chip = { |
126 | .name = "GPIO-l", | |
a3f4c927 | 127 | .irq_ack = pxa_ack_low_gpio, |
a1015a15 EM |
128 | .irq_mask = pxa_mask_irq, |
129 | .irq_unmask = pxa_unmask_irq, | |
a3f4c927 | 130 | .irq_set_type = pxa_set_low_gpio_type, |
a58fbcd8 EM |
131 | }; |
132 | ||
a551e4f7 EM |
133 | asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) |
134 | { | |
135 | uint32_t icip, icmr, mask; | |
136 | ||
137 | do { | |
138 | icip = __raw_readl(IRQ_BASE + ICIP); | |
139 | icmr = __raw_readl(IRQ_BASE + ICMR); | |
140 | mask = icip & icmr; | |
141 | ||
142 | if (mask == 0) | |
143 | break; | |
144 | ||
145 | handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); | |
146 | } while (1); | |
147 | } | |
148 | ||
149 | asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) | |
150 | { | |
151 | uint32_t ichp; | |
152 | ||
153 | do { | |
154 | __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); | |
155 | ||
156 | if ((ichp & ICHP_VAL_IRQ) == 0) | |
157 | break; | |
158 | ||
159 | handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); | |
160 | } while (1); | |
161 | } | |
162 | ||
a58fbcd8 EM |
163 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) |
164 | { | |
165 | int irq; | |
166 | ||
167 | /* clear edge detection on GPIO 0 and 1 */ | |
168 | GFER0 &= ~0x3; | |
169 | GRER0 &= ~0x3; | |
170 | GEDR0 = 0x3; | |
171 | ||
172 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | |
f38c02f3 TG |
173 | irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, |
174 | handle_edge_irq); | |
9323f261 | 175 | irq_set_chip_data(irq, irq_base(0)); |
a58fbcd8 EM |
176 | set_irq_flags(irq, IRQF_VALID); |
177 | } | |
178 | ||
a3f4c927 | 179 | pxa_low_gpio_chip.irq_set_wake = fn; |
a58fbcd8 EM |
180 | } |
181 | ||
b9e25ace | 182 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
53665a50 | 183 | { |
a79a9ad9 | 184 | int irq, i, n; |
53665a50 | 185 | |
c482ae4d HZ |
186 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); |
187 | ||
f6fb7af4 | 188 | pxa_internal_irq_nr = irq_nr; |
53665a50 | 189 | |
a79a9ad9 | 190 | for (n = 0; n < irq_nr; n += 32) { |
1b624fb6 | 191 | void __iomem *base = irq_base(n >> 5); |
a79a9ad9 HZ |
192 | |
193 | __raw_writel(0, base + ICMR); /* disable all IRQs */ | |
194 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | |
195 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { | |
196 | /* initialize interrupt priority */ | |
197 | if (cpu_has_ipr()) | |
198 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); | |
199 | ||
200 | irq = PXA_IRQ(i); | |
f38c02f3 TG |
201 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, |
202 | handle_level_irq); | |
9323f261 | 203 | irq_set_chip_data(irq, base); |
a79a9ad9 HZ |
204 | set_irq_flags(irq, IRQF_VALID); |
205 | } | |
d2c37068 HZ |
206 | } |
207 | ||
53665a50 | 208 | /* only unmasked interrupts kick us out of idle */ |
a79a9ad9 | 209 | __raw_writel(1, irq_base(0) + ICCR); |
1da177e4 | 210 | |
a3f4c927 | 211 | pxa_internal_irq_chip.irq_set_wake = fn; |
a58fbcd8 | 212 | pxa_init_low_gpio_irq(fn); |
c95530c7 | 213 | } |
c0165504 | 214 | |
215 | #ifdef CONFIG_PM | |
c482ae4d HZ |
216 | static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; |
217 | static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; | |
c0165504 | 218 | |
2eaa03b5 | 219 | static int pxa_irq_suspend(void) |
c0165504 | 220 | { |
a79a9ad9 HZ |
221 | int i; |
222 | ||
1b624fb6 | 223 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
a79a9ad9 | 224 | void __iomem *base = irq_base(i); |
f6fb7af4 | 225 | |
a79a9ad9 HZ |
226 | saved_icmr[i] = __raw_readl(base + ICMR); |
227 | __raw_writel(0, base + ICMR); | |
c0165504 | 228 | } |
c70f5a60 | 229 | |
bb71bdd3 | 230 | if (cpu_has_ipr()) { |
c70f5a60 | 231 | for (i = 0; i < pxa_internal_irq_nr; i++) |
a79a9ad9 | 232 | saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); |
c70f5a60 | 233 | } |
c0165504 | 234 | |
235 | return 0; | |
236 | } | |
237 | ||
2eaa03b5 | 238 | static void pxa_irq_resume(void) |
c0165504 | 239 | { |
a79a9ad9 | 240 | int i; |
f6fb7af4 | 241 | |
1b624fb6 | 242 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
a79a9ad9 | 243 | void __iomem *base = irq_base(i); |
c70f5a60 | 244 | |
a79a9ad9 HZ |
245 | __raw_writel(saved_icmr[i], base + ICMR); |
246 | __raw_writel(0, base + ICLR); | |
c0165504 | 247 | } |
248 | ||
57879b8c | 249 | if (cpu_has_ipr()) |
a79a9ad9 HZ |
250 | for (i = 0; i < pxa_internal_irq_nr; i++) |
251 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); | |
252 | ||
253 | __raw_writel(1, IRQ_BASE + ICCR); | |
c0165504 | 254 | } |
255 | #else | |
256 | #define pxa_irq_suspend NULL | |
257 | #define pxa_irq_resume NULL | |
258 | #endif | |
259 | ||
2eaa03b5 | 260 | struct syscore_ops pxa_irq_syscore_ops = { |
c0165504 | 261 | .suspend = pxa_irq_suspend, |
262 | .resume = pxa_irq_resume, | |
263 | }; |