[linux-2.6-block.git] / arch / arm / mach-pxa / include / mach / pxafb.h

/*
 *  arch/arm/mach-pxa/include/mach/pxafb.h
 *
 *  Support for the xscale frame buffer.
 *
 *  Author:     Jean-Frederic Clere
 *  Created:    Sep 22, 2003
 *  Copyright:  jfclere@sinix.net
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/fb.h>
#include <mach/regs-lcd.h>

/*
 * Supported LCD connections
 *
 * bits 0 - 3: for LCD panel type:
 *
 *   STN  - for passive matrix
 *   DSTN - for dual scan passive matrix
 *   TFT  - for active matrix
 *
 * bits 4 - 9 : for bus width
 * bits 10-17 : for AC Bias Pin Frequency
 * bit     18 : for output enable polarity
 * bit     19 : for pixel clock edge
 * bit     20 : for output pixel format when base is RGBT16
 */
#define LCD_CONN_TYPE(_x)	((_x) & 0x0f)
#define LCD_CONN_WIDTH(_x)	(((_x) >> 4) & 0x1f)

#define LCD_TYPE_MASK		0xf
#define LCD_TYPE_UNKNOWN	0
#define LCD_TYPE_MONO_STN	1
#define LCD_TYPE_MONO_DSTN	2
#define LCD_TYPE_COLOR_STN	3
#define LCD_TYPE_COLOR_DSTN	4
#define LCD_TYPE_COLOR_TFT	5
#define LCD_TYPE_SMART_PANEL	6
#define LCD_TYPE_MAX		7

#define LCD_MONO_STN_4BPP	((4  << 4) | LCD_TYPE_MONO_STN)
#define LCD_MONO_STN_8BPP	((8  << 4) | LCD_TYPE_MONO_STN)
#define LCD_MONO_DSTN_8BPP	((8  << 4) | LCD_TYPE_MONO_DSTN)
#define LCD_COLOR_STN_8BPP	((8  << 4) | LCD_TYPE_COLOR_STN)
#define LCD_COLOR_DSTN_16BPP	((16 << 4) | LCD_TYPE_COLOR_DSTN)
#define LCD_COLOR_TFT_8BPP	((8  << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_COLOR_TFT_16BPP	((16 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_COLOR_TFT_18BPP	((18 << 4) | LCD_TYPE_COLOR_TFT)
#define LCD_SMART_PANEL_8BPP	((8  << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_SMART_PANEL_16BPP	((16 << 4) | LCD_TYPE_SMART_PANEL)
#define LCD_SMART_PANEL_18BPP	((18 << 4) | LCD_TYPE_SMART_PANEL)

#define LCD_AC_BIAS_FREQ(x)	(((x) & 0xff) << 10)
#define LCD_BIAS_ACTIVE_HIGH	(0 << 18)
#define LCD_BIAS_ACTIVE_LOW	(1 << 18)
#define LCD_PCLK_EDGE_RISE	(0 << 19)
#define LCD_PCLK_EDGE_FALL	(1 << 19)
#define LCD_ALTERNATE_MAPPING	(1 << 20)

/*
 * This structure describes the machine which we are running on.
 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
 * of linux/drivers/video/pxafb.c
 */
struct pxafb_mode_info {
	u_long		pixclock;

	u_short		xres;
	u_short		yres;

	u_char		bpp;
	u_int		cmap_greyscale:1,
			depth:8,
			unused:23;

	/* Parallel Mode Timing */
	u_char		hsync_len;
	u_char		left_margin;
	u_char		right_margin;

	u_char		vsync_len;
	u_char		upper_margin;
	u_char		lower_margin;
	u_char		sync;

	/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
	 * Note:
	 * 1. all parameters in nanosecond (ns)
	 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
	 *    in pxa27x and pxa3xx, initialize them to the same value or
	 *    the larger one will be used
	 * 3. same to {rd,wr}_pulse_width
	 *
	 * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
	 * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
	 * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
	 */
	unsigned	a0csrd_set_hld;	/* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
	unsigned	a0cswr_set_hld;	/* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
	unsigned	wr_pulse_width;	/* L_PCLK_WR pulse width */
	unsigned	rd_pulse_width;	/* L_FCLK_RD pulse width */
	unsigned	cmd_inh_time;	/* Command Inhibit time between two writes */
	unsigned	op_hold_time;	/* Output Hold time from L_FCLK_RD negation */
};

struct pxafb_mach_info {
	struct pxafb_mode_info *modes;
	unsigned int num_modes;

	unsigned int	lcd_conn;
	unsigned long	video_mem_size;

	u_int		fixed_modes:1,
			cmap_inverse:1,
			cmap_static:1,
			unused:29;

	/* The following should be defined in LCCR0
	 *      LCCR0_Act or LCCR0_Pas          Active or Passive
	 *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
	 *      LCCR0_Mono or LCCR0_Color       Mono/Color
	 *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
	 *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
	 *
	 * The following should not be defined in LCCR0:
	 *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
	 *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
	 */
	u_int		lccr0;
	/* The following should be defined in LCCR3
	 *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
	 *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
	 *      LCCR3_Acb(X)                    AB Bias pin frequency
	 *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
	 *
	 * The following should not be defined in LCCR3
	 *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
	 */
	u_int		lccr3;
	/* The following should be defined in LCCR4
	 *	LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
	 *
	 * All other bits in LCCR4 should be left alone.
	 */
	u_int		lccr4;
	void (*pxafb_backlight_power)(int);
	void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
	void (*smart_update)(struct fb_info *);
};
void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
void set_pxa_fb_parent(struct device *parent_dev);
unsigned long pxafb_get_hsync_time(struct device *dev);

extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
extern int pxafb_smart_flush(struct fb_info *info);
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/mach-pxa/include/mach/pxafb.h
1da177e4 LT	3	*
	4	* Support for the xscale frame buffer.
	5	*
	6	* Author: Jean-Frederic Clere
	7	* Created: Sep 22, 2003
	8	* Copyright: jfclere@sinix.net
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
d14b272b	15	#include <linux/fb.h>
a09e64fb	16	#include <mach/regs-lcd.h>
d14b272b	17
84f43c30	18	/*
	19	* Supported LCD connections
	20	*
	21	* bits 0 - 3: for LCD panel type:
	22	*
	23	* STN - for passive matrix
	24	* DSTN - for dual scan passive matrix
	25	* TFT - for active matrix
	26	*
	27	* bits 4 - 9 : for bus width
	28	* bits 10-17 : for AC Bias Pin Frequency
	29	* bit 18 : for output enable polarity
	30	* bit 19 : for pixel clock edge
9a1ac7e4	31	* bit 20 : for output pixel format when base is RGBT16
84f43c30	32	*/
	33	#define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
	34	#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
	35
1ec26db1	36	#define LCD_TYPE_MASK 0xf
84f43c30	37	#define LCD_TYPE_UNKNOWN 0
	38	#define LCD_TYPE_MONO_STN 1
	39	#define LCD_TYPE_MONO_DSTN 2
	40	#define LCD_TYPE_COLOR_STN 3
	41	#define LCD_TYPE_COLOR_DSTN 4
	42	#define LCD_TYPE_COLOR_TFT 5
	43	#define LCD_TYPE_SMART_PANEL 6
	44	#define LCD_TYPE_MAX 7
	45
	46	#define LCD_MONO_STN_4BPP ((4 << 4) \| LCD_TYPE_MONO_STN)
	47	#define LCD_MONO_STN_8BPP ((8 << 4) \| LCD_TYPE_MONO_STN)
	48	#define LCD_MONO_DSTN_8BPP ((8 << 4) \| LCD_TYPE_MONO_DSTN)
	49	#define LCD_COLOR_STN_8BPP ((8 << 4) \| LCD_TYPE_COLOR_STN)
	50	#define LCD_COLOR_DSTN_16BPP ((16 << 4) \| LCD_TYPE_COLOR_DSTN)
51633048	51	#define LCD_COLOR_TFT_8BPP ((8 << 4) \| LCD_TYPE_COLOR_TFT)
84f43c30	52	#define LCD_COLOR_TFT_16BPP ((16 << 4) \| LCD_TYPE_COLOR_TFT)
84f43c30	53	#define LCD_COLOR_TFT_18BPP ((18 << 4) \| LCD_TYPE_COLOR_TFT)
3c42a449	54	#define LCD_SMART_PANEL_8BPP ((8 << 4) \| LCD_TYPE_SMART_PANEL)
84f43c30	55	#define LCD_SMART_PANEL_16BPP ((16 << 4) \| LCD_TYPE_SMART_PANEL)
	56	#define LCD_SMART_PANEL_18BPP ((18 << 4) \| LCD_TYPE_SMART_PANEL)
	57
	58	#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
9a1ac7e4 EM	59	#define LCD_BIAS_ACTIVE_HIGH (0 << 18)
	60	#define LCD_BIAS_ACTIVE_LOW (1 << 18)
	61	#define LCD_PCLK_EDGE_RISE (0 << 19)
	62	#define LCD_PCLK_EDGE_FALL (1 << 19)
	63	#define LCD_ALTERNATE_MAPPING (1 << 20)
84f43c30	64
1da177e4 LT	65	/*
	66	* This structure describes the machine which we are running on.
	67	* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
	68	* of linux/drivers/video/pxafb.c
	69	*/
d14b272b	70	struct pxafb_mode_info {
1da177e4 LT	71	u_long pixclock;
	72
	73	u_short xres;
	74	u_short yres;
	75
	76	u_char bpp;
3c42a449	77	u_int cmap_greyscale:1,
c1450f15 SS	78	depth:8,
c1450f15 SS	79	unused:23;
3c42a449 EM	80
3c42a449 EM	81	/* Parallel Mode Timing */
1da177e4 LT	82	u_char hsync_len;
	83	u_char left_margin;
	84	u_char right_margin;
	85
	86	u_char vsync_len;
	87	u_char upper_margin;
	88	u_char lower_margin;
	89	u_char sync;
	90
3c42a449 EM	91	/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
	92	* Note:
	93	* 1. all parameters in nanosecond (ns)
	94	* 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
	95	* in pxa27x and pxa3xx, initialize them to the same value or
	96	* the larger one will be used
	97	* 3. same to {rd,wr}_pulse_width
c1f99c21 EM	98	*
	99	* 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
	100	* 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
	101	* 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
3c42a449 EM	102	*/
	103	unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
	104	unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
	105	unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
	106	unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
	107	unsigned cmd_inh_time; /* Command Inhibit time between two writes */
	108	unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
d14b272b RP	109	};
	110
	111	struct pxafb_mach_info {
	112	struct pxafb_mode_info *modes;
	113	unsigned int num_modes;
	114
84f43c30	115	unsigned int lcd_conn;
77e19675	116	unsigned long video_mem_size;
84f43c30	117
d14b272b	118	u_int fixed_modes:1,
1da177e4 LT	119	cmap_inverse:1,
	120	cmap_static:1,
	121	unused:29;
	122
	123	/* The following should be defined in LCCR0
	124	* LCCR0_Act or LCCR0_Pas Active or Passive
	125	* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
	126	* LCCR0_Mono or LCCR0_Color Mono/Color
	127	* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
	128	* LCCR0_DMADel(Tcpu) (optional) DMA request delay
	129	*
	130	* The following should not be defined in LCCR0:
	131	* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
	132	* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
	133	*/
	134	u_int lccr0;
	135	/* The following should be defined in LCCR3
	136	* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
	137	* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
	138	* LCCR3_Acb(X) AB Bias pin frequency
	139	* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
	140	*
	141	* The following should not be defined in LCCR3
	142	* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
	143	*/
	144	u_int lccr3;
9ffa7396 HK	145	/* The following should be defined in LCCR4
	146	* LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
	147	*
	148	* All other bits in LCCR4 should be left alone.
	149	*/
	150	u_int lccr4;
1da177e4	151	void (*pxafb_backlight_power)(int);
d14b272b	152	void (pxafb_lcd_power)(int, struct fb_var_screeninfo );
3c42a449	153	void (smart_update)(struct fb_info );
1da177e4 LT	154	};
1da177e4 LT	155	void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
cb38c569	156	void set_pxa_fb_parent(struct device *parent_dev);
ba44cd2d	157	unsigned long pxafb_get_hsync_time(struct device *dev);
3c42a449 EM	158
	159	extern int pxafb_smart_queue(struct fb_info info, uint16_t cmds, int);
	160	extern int pxafb_smart_flush(struct fb_info *info);