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1 | #ifndef _ASM_ARCH_PXA25X_UDC_H |
2 | #define _ASM_ARCH_PXA25X_UDC_H | |
3 | ||
4 | #ifdef _ASM_ARCH_PXA27X_UDC_H | |
aafe0ad8 | 5 | #error "You can't include both PXA25x and PXA27x UDC support" |
284d115e RK |
6 | #endif |
7 | ||
8 | #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ | |
9 | #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ | |
10 | #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ | |
11 | ||
12 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | |
13 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | |
14 | #define UDCCR_UDA (1 << 1) /* UDC active */ | |
15 | #define UDCCR_RSM (1 << 2) /* Device resume */ | |
16 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | |
17 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | |
18 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | |
19 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | |
20 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | |
21 | ||
22 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ | |
23 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | |
24 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | |
25 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | |
26 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | |
27 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | |
28 | #define UDCCS0_FST (1 << 5) /* Force stall */ | |
29 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | |
30 | #define UDCCS0_SA (1 << 7) /* Setup active */ | |
31 | ||
32 | /* Bulk IN - Endpoint 1,6,11 */ | |
33 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ | |
34 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ | |
35 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ | |
36 | ||
37 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | |
38 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | |
39 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | |
40 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | |
41 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | |
42 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | |
43 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | |
44 | ||
45 | /* Bulk OUT - Endpoint 2,7,12 */ | |
46 | #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | |
47 | #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | |
48 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ | |
49 | ||
50 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | |
51 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | |
52 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | |
53 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | |
54 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | |
55 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | |
56 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | |
57 | ||
58 | /* Isochronous IN - Endpoint 3,8,13 */ | |
59 | #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | |
60 | #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | |
61 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ | |
62 | ||
63 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | |
64 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | |
65 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | |
66 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | |
67 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | |
68 | ||
69 | /* Isochronous OUT - Endpoint 4,9,14 */ | |
70 | #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | |
71 | #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | |
72 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ | |
73 | ||
74 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | |
75 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | |
76 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ | |
77 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | |
78 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | |
79 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | |
80 | ||
81 | /* Interrupt IN - Endpoint 5,10,15 */ | |
82 | #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | |
83 | #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | |
84 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | |
85 | ||
86 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | |
87 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | |
88 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | |
89 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | |
90 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | |
91 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | |
92 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | |
93 | ||
94 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ | |
95 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ | |
96 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ | |
97 | #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ | |
98 | #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ | |
99 | #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ | |
100 | #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ | |
101 | #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ | |
102 | #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ | |
103 | #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ | |
104 | #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ | |
105 | #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ | |
106 | #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ | |
107 | #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ | |
108 | #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ | |
109 | #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ | |
110 | #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ | |
111 | #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ | |
112 | #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ | |
113 | #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ | |
114 | #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ | |
115 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ | |
116 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ | |
117 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ | |
118 | ||
119 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ | |
120 | ||
121 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | |
122 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | |
123 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | |
124 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | |
125 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | |
126 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | |
127 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | |
128 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | |
129 | ||
130 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ | |
131 | ||
132 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | |
133 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | |
134 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | |
135 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | |
136 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | |
137 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | |
138 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | |
139 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | |
140 | ||
141 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | |
142 | ||
143 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ | |
144 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ | |
145 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ | |
146 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ | |
147 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ | |
148 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ | |
149 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ | |
150 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ | |
151 | ||
152 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | |
153 | ||
154 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ | |
155 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ | |
156 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ | |
157 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ | |
158 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ | |
159 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ | |
160 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ | |
161 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ | |
162 | ||
163 | #endif |