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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/pxa-regs.h |
1da177e4 LT |
3 | * |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __PXA_REGS_H | |
14 | #define __PXA_REGS_H | |
15 | ||
1da177e4 LT |
16 | |
17 | /* | |
18 | * PXA Chip selects | |
19 | */ | |
20 | ||
21 | #define PXA_CS0_PHYS 0x00000000 | |
22 | #define PXA_CS1_PHYS 0x04000000 | |
23 | #define PXA_CS2_PHYS 0x08000000 | |
24 | #define PXA_CS3_PHYS 0x0C000000 | |
25 | #define PXA_CS4_PHYS 0x10000000 | |
26 | #define PXA_CS5_PHYS 0x14000000 | |
27 | ||
28 | ||
29 | /* | |
30 | * Personal Computer Memory Card International Association (PCMCIA) sockets | |
31 | */ | |
32 | ||
33 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | |
34 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | |
35 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | |
36 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | |
37 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | |
38 | ||
39 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | |
40 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | |
41 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | |
42 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | |
43 | ||
44 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | |
45 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | |
46 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | |
47 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | |
48 | ||
49 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | |
50 | (0x20000000 + (Nb)*PCMCIASp) | |
51 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | |
52 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | |
53 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | |
54 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | |
55 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | |
56 | ||
57 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | |
58 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | |
59 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | |
60 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | |
61 | ||
62 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | |
63 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | |
64 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | |
65 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | |
66 | ||
67 | ||
68 | ||
69 | /* | |
70 | * DMA Controller | |
71 | */ | |
1da177e4 LT |
72 | #define DCSR(x) __REG2(0x40000000, (x) << 2) |
73 | ||
74 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | |
75 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | |
76 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | |
cbd18f8e EM |
77 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ |
78 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | |
79 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | |
80 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | |
81 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | |
82 | ||
83 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | |
1da177e4 LT |
84 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ |
85 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | |
86 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | |
87 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | |
88 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | |
89 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | |
127e477e | 90 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ |
1da177e4 | 91 | #endif |
1da177e4 | 92 | |
68477d11 | 93 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ |
1da177e4 LT |
94 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ |
95 | ||
7267d1cc | 96 | #define DRCMR(n) (*(((n) < 64) ? \ |
97 | &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ | |
98 | &__REG2(0x40001100, ((n) & 0x3f) << 2))) | |
99 | ||
1da177e4 LT |
100 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ |
101 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | |
102 | ||
1da177e4 LT |
103 | #define DDADR(x) __REG2(0x40000200, (x) << 4) |
104 | #define DSADR(x) __REG2(0x40000204, (x) << 4) | |
105 | #define DTADR(x) __REG2(0x40000208, (x) << 4) | |
106 | #define DCMD(x) __REG2(0x4000020c, (x) << 4) | |
107 | ||
108 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | |
109 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | |
110 | ||
111 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | |
112 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | |
113 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | |
114 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | |
115 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | |
116 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | |
117 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | |
118 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | |
119 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | |
120 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | |
121 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | |
122 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | |
123 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | |
124 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | |
125 | ||
126 | ||
127 | /* | |
128 | * UARTs | |
129 | */ | |
130 | ||
131 | /* Full Function UART (FFUART) */ | |
132 | #define FFUART FFRBR | |
133 | #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ | |
134 | #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ | |
135 | #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ | |
136 | #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ | |
137 | #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ | |
138 | #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ | |
139 | #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ | |
140 | #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ | |
141 | #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ | |
142 | #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ | |
143 | #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ | |
144 | #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
145 | #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
146 | ||
147 | /* Bluetooth UART (BTUART) */ | |
148 | #define BTUART BTRBR | |
149 | #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ | |
150 | #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ | |
151 | #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ | |
152 | #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ | |
153 | #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ | |
154 | #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ | |
155 | #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ | |
156 | #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ | |
157 | #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ | |
158 | #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ | |
159 | #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ | |
160 | #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
161 | #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
162 | ||
163 | /* Standard UART (STUART) */ | |
164 | #define STUART STRBR | |
165 | #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ | |
166 | #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ | |
167 | #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ | |
168 | #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ | |
169 | #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ | |
170 | #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ | |
171 | #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ | |
172 | #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ | |
173 | #define STMSR __REG(0x40700018) /* Reserved */ | |
174 | #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ | |
175 | #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ | |
176 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
177 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
178 | ||
d9e29649 MR |
179 | /* Hardware UART (HWUART) */ |
180 | #define HWUART HWRBR | |
181 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ | |
182 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ | |
183 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ | |
184 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ | |
185 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ | |
186 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ | |
187 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ | |
188 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ | |
189 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ | |
190 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ | |
191 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ | |
192 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ | |
193 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ | |
194 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ | |
195 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | |
196 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | |
197 | ||
1da177e4 LT |
198 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ |
199 | #define IER_UUE (1 << 6) /* UART Unit Enable */ | |
200 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ | |
201 | #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ | |
202 | #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ | |
203 | #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ | |
204 | #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ | |
205 | #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ | |
206 | ||
207 | #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ | |
208 | #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ | |
209 | #define IIR_TOD (1 << 3) /* Time Out Detected */ | |
210 | #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ | |
211 | #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ | |
212 | #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ | |
213 | ||
214 | #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ | |
215 | #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ | |
216 | #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ | |
217 | #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ | |
218 | #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ | |
219 | #define FCR_ITL_1 (0) | |
220 | #define FCR_ITL_8 (FCR_ITL1) | |
221 | #define FCR_ITL_16 (FCR_ITL2) | |
222 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) | |
223 | ||
224 | #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ | |
225 | #define LCR_SB (1 << 6) /* Set Break */ | |
226 | #define LCR_STKYP (1 << 5) /* Sticky Parity */ | |
227 | #define LCR_EPS (1 << 4) /* Even Parity Select */ | |
228 | #define LCR_PEN (1 << 3) /* Parity Enable */ | |
229 | #define LCR_STB (1 << 2) /* Stop Bit */ | |
230 | #define LCR_WLS1 (1 << 1) /* Word Length Select */ | |
231 | #define LCR_WLS0 (1 << 0) /* Word Length Select */ | |
232 | ||
233 | #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ | |
234 | #define LSR_TEMT (1 << 6) /* Transmitter Empty */ | |
235 | #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ | |
236 | #define LSR_BI (1 << 4) /* Break Interrupt */ | |
237 | #define LSR_FE (1 << 3) /* Framing Error */ | |
238 | #define LSR_PE (1 << 2) /* Parity Error */ | |
239 | #define LSR_OE (1 << 1) /* Overrun Error */ | |
240 | #define LSR_DR (1 << 0) /* Data Ready */ | |
241 | ||
242 | #define MCR_LOOP (1 << 4) | |
243 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ | |
244 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ | |
245 | #define MCR_RTS (1 << 1) /* Request to Send */ | |
246 | #define MCR_DTR (1 << 0) /* Data Terminal Ready */ | |
247 | ||
248 | #define MSR_DCD (1 << 7) /* Data Carrier Detect */ | |
249 | #define MSR_RI (1 << 6) /* Ring Indicator */ | |
250 | #define MSR_DSR (1 << 5) /* Data Set Ready */ | |
251 | #define MSR_CTS (1 << 4) /* Clear To Send */ | |
252 | #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ | |
253 | #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ | |
254 | #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ | |
255 | #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ | |
256 | ||
257 | /* | |
258 | * IrSR (Infrared Selection Register) | |
259 | */ | |
260 | #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ | |
261 | #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ | |
262 | #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ | |
263 | #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ | |
264 | #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ | |
265 | ||
266 | ||
267 | /* | |
283afa06 | 268 | * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c |
1da177e4 LT |
269 | */ |
270 | ||
1da177e4 | 271 | /* |
52358ba3 | 272 | * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c |
1da177e4 LT |
273 | */ |
274 | ||
1da177e4 LT |
275 | /* |
276 | * AC97 Controller registers | |
277 | */ | |
278 | ||
279 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ | |
280 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | |
281 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
282 | ||
283 | #define PICR __REG(0x40500004) /* PCM In Control Register */ | |
284 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | |
285 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
286 | ||
287 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ | |
288 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | |
289 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
290 | ||
291 | #define GCR __REG(0x4050000C) /* Global Control Register */ | |
d862ccc5 MB |
292 | #ifdef CONFIG_PXA3xx |
293 | #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ | |
294 | #endif | |
1da177e4 LT |
295 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ |
296 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ | |
297 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ | |
298 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ | |
299 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ | |
300 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ | |
301 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ | |
302 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ | |
303 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ | |
304 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ | |
305 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ | |
306 | ||
307 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ | |
308 | #define POSR_FIFOE (1 << 4) /* FIFO error */ | |
309 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ | |
310 | ||
311 | #define PISR __REG(0x40500014) /* PCM In Status Register */ | |
312 | #define PISR_FIFOE (1 << 4) /* FIFO error */ | |
313 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | |
314 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ | |
315 | ||
316 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ | |
317 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ | |
318 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | |
319 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ | |
320 | ||
321 | #define GSR __REG(0x4050001C) /* Global Status Register */ | |
322 | #define GSR_CDONE (1 << 19) /* Command Done */ | |
323 | #define GSR_SDONE (1 << 18) /* Status Done */ | |
324 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ | |
325 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ | |
326 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ | |
327 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ | |
328 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ | |
329 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ | |
330 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ | |
331 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ | |
332 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ | |
333 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ | |
334 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ | |
335 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ | |
336 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ | |
337 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ | |
338 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ | |
339 | ||
340 | #define CAR __REG(0x40500020) /* CODEC Access Register */ | |
341 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ | |
342 | ||
343 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ | |
344 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ | |
345 | ||
346 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ | |
347 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ | |
348 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
349 | ||
350 | #define MICR __REG(0x40500108) /* Modem In Control Register */ | |
351 | #define MICR_FEIE (1 << 3) /* FIFO Error */ | |
352 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | |
353 | ||
354 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ | |
355 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ | |
356 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ | |
357 | ||
358 | #define MISR __REG(0x40500118) /* Modem In Status Register */ | |
359 | #define MISR_FIFOE (1 << 4) /* FIFO error */ | |
360 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | |
361 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ | |
362 | ||
363 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ | |
364 | ||
365 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ | |
366 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ | |
367 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ | |
368 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ | |
369 | ||
370 | ||
1da177e4 LT |
371 | /* |
372 | * Fast Infrared Communication Port | |
373 | */ | |
374 | ||
375 | #define FICP __REG(0x40800000) /* Start of FICP area */ | |
376 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ | |
377 | #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ | |
378 | #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ | |
379 | #define ICDR __REG(0x4080000c) /* ICP Data Register */ | |
380 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ | |
381 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ | |
382 | ||
84c07923 | 383 | #define ICCR0_AME (1 << 7) /* Address match enable */ |
1da177e4 LT |
384 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ |
385 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ | |
386 | #define ICCR0_RXE (1 << 4) /* Receive enable */ | |
387 | #define ICCR0_TXE (1 << 3) /* Transmit enable */ | |
388 | #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ | |
389 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ | |
390 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ | |
391 | ||
1da177e4 LT |
392 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ |
393 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ | |
394 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ | |
395 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ | |
396 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ | |
397 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ | |
1da177e4 LT |
398 | |
399 | #ifdef CONFIG_PXA27x | |
400 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ | |
401 | #endif | |
402 | #define ICSR0_FRE (1 << 5) /* Framing error */ | |
403 | #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ | |
404 | #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ | |
405 | #define ICSR0_RAB (1 << 2) /* Receiver abort */ | |
406 | #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ | |
407 | #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ | |
408 | ||
409 | #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ | |
410 | #define ICSR1_CRE (1 << 5) /* CRC error */ | |
411 | #define ICSR1_EOF (1 << 4) /* End of frame */ | |
412 | #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ | |
413 | #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ | |
414 | #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ | |
415 | #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ | |
416 | ||
417 | ||
418 | /* | |
419 | * Real Time Clock | |
420 | */ | |
421 | ||
422 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | |
423 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | |
424 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | |
425 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | |
426 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | |
427 | ||
428 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | |
429 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | |
430 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | |
431 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | |
432 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | |
433 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | |
434 | ||
435 | ||
436 | /* | |
437 | * OS Timer & Match Registers | |
438 | */ | |
439 | ||
440 | #define OSMR0 __REG(0x40A00000) /* */ | |
441 | #define OSMR1 __REG(0x40A00004) /* */ | |
442 | #define OSMR2 __REG(0x40A00008) /* */ | |
443 | #define OSMR3 __REG(0x40A0000C) /* */ | |
444 | #define OSMR4 __REG(0x40A00080) /* */ | |
445 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | |
446 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | |
447 | #define OMCR4 __REG(0x40A000C0) /* */ | |
448 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | |
449 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | |
450 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | |
451 | ||
452 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | |
453 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | |
454 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | |
455 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | |
456 | ||
457 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | |
458 | ||
459 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | |
460 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | |
461 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | |
462 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | |
463 | ||
464 | ||
465 | /* | |
466 | * Pulse Width Modulator | |
467 | */ | |
468 | ||
469 | #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ | |
470 | #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ | |
471 | #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ | |
472 | ||
473 | #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ | |
474 | #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ | |
475 | #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ | |
476 | ||
477 | ||
478 | /* | |
479 | * Interrupt Controller | |
480 | */ | |
481 | ||
482 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | |
483 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | |
484 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | |
485 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | |
486 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | |
487 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | |
488 | ||
f6fb7af4 | 489 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ |
490 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | |
491 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | |
492 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | |
493 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | |
1da177e4 LT |
494 | |
495 | /* | |
496 | * General Purpose I/O | |
497 | */ | |
498 | ||
1c44f5f1 PZ |
499 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) |
500 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | |
501 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | |
502 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | |
503 | ||
504 | #define GPLR_OFFSET 0x00 | |
505 | #define GPDR_OFFSET 0x0C | |
506 | #define GPSR_OFFSET 0x18 | |
507 | #define GPCR_OFFSET 0x24 | |
508 | #define GRER_OFFSET 0x30 | |
509 | #define GFER_OFFSET 0x3C | |
510 | #define GEDR_OFFSET 0x48 | |
511 | ||
1da177e4 LT |
512 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ |
513 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | |
514 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | |
515 | ||
516 | #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ | |
517 | #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ | |
518 | #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ | |
519 | ||
520 | #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ | |
521 | #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ | |
522 | #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ | |
523 | ||
524 | #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ | |
525 | #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ | |
526 | #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ | |
527 | ||
528 | #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ | |
529 | #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ | |
530 | #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ | |
531 | ||
532 | #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ | |
533 | #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ | |
534 | #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ | |
535 | ||
536 | #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ | |
537 | #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ | |
538 | #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ | |
539 | ||
540 | #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ | |
541 | #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ | |
542 | #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ | |
543 | #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ | |
544 | #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ | |
545 | #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ | |
546 | #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ | |
547 | #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ | |
548 | ||
549 | #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ | |
550 | #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ | |
551 | #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ | |
552 | #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ | |
553 | #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ | |
554 | #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ | |
555 | #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ | |
556 | ||
557 | /* More handy macros. The argument is a literal GPIO number. */ | |
558 | ||
559 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | |
560 | ||
2c8086a5 | 561 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
1da177e4 LT |
562 | |
563 | /* Interrupt Controller */ | |
564 | ||
1da177e4 LT |
565 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) |
566 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | |
567 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | |
568 | #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | |
569 | #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | |
570 | #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | |
571 | #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | |
572 | #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | |
573 | ||
574 | #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) | |
575 | #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) | |
576 | #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) | |
577 | #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) | |
578 | #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) | |
579 | #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) | |
580 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | |
581 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | |
582 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | |
583 | #else | |
584 | ||
585 | #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | |
586 | #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | |
587 | #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | |
588 | #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | |
589 | #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | |
590 | #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | |
591 | #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | |
592 | #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | |
593 | ||
594 | #endif | |
595 | ||
1da177e4 | 596 | /* |
0b0a9df6 | 597 | * Power Manager - see pxa2xx-regs.h |
1da177e4 LT |
598 | */ |
599 | ||
1da177e4 | 600 | /* |
a09e64fb | 601 | * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h |
1da177e4 LT |
602 | */ |
603 | ||
1da177e4 | 604 | /* |
7a2b94bc | 605 | * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h |
1da177e4 LT |
606 | */ |
607 | ||
1da177e4 | 608 | /* |
a09e64fb | 609 | * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h |
1da177e4 LT |
610 | */ |
611 | ||
1da177e4 LT |
612 | #ifdef CONFIG_PXA27x |
613 | ||
1da177e4 LT |
614 | /* Camera Interface */ |
615 | #define CICR0 __REG(0x50000000) | |
616 | #define CICR1 __REG(0x50000004) | |
617 | #define CICR2 __REG(0x50000008) | |
618 | #define CICR3 __REG(0x5000000C) | |
619 | #define CICR4 __REG(0x50000010) | |
620 | #define CISR __REG(0x50000014) | |
621 | #define CIFR __REG(0x50000018) | |
622 | #define CITOR __REG(0x5000001C) | |
623 | #define CIBR0 __REG(0x50000028) | |
624 | #define CIBR1 __REG(0x50000030) | |
625 | #define CIBR2 __REG(0x50000038) | |
626 | ||
627 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
628 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
629 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
630 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
631 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
632 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
633 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
634 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
635 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
636 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
637 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
638 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
639 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
640 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
641 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
642 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
643 | ||
644 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
64c1dd3b | 645 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ |
1f4a3931 | 646 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ |
1da177e4 LT |
647 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ |
648 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
649 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
650 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
651 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
652 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
653 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
654 | ||
655 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
656 | wait count mask */ | |
657 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
658 | wait count mask */ | |
659 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
660 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
661 | wait count mask */ | |
662 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
663 | wait count mask */ | |
664 | ||
665 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
666 | wait count mask */ | |
667 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
668 | wait count mask */ | |
669 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
670 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
671 | wait count mask */ | |
1f4a3931 | 672 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ |
1da177e4 LT |
673 | |
674 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
675 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
676 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
677 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
678 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
679 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
680 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
681 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
682 | ||
683 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
684 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
685 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
686 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
687 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
688 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
689 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
690 | #define CISR_EOL (1 << 8) /* End of line */ | |
691 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
692 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
1f4a3931 ES |
693 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ |
694 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
1da177e4 LT |
695 | #define CISR_EOF (1 << 3) /* End of frame */ |
696 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
697 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
698 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
699 | ||
700 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
701 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
702 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
703 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
704 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
705 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
706 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
707 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
708 | ||
709 | #define SRAM_SIZE 0x40000 /* 4x64K */ | |
710 | ||
711 | #define SRAM_MEM_PHYS 0x5C000000 | |
712 | ||
713 | #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ | |
714 | #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ | |
715 | ||
716 | #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ | |
717 | #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ | |
718 | #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ | |
719 | #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ | |
720 | ||
721 | #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ | |
722 | #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ | |
723 | #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ | |
724 | #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ | |
725 | ||
726 | #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ | |
727 | #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ | |
728 | #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ | |
729 | #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ | |
730 | ||
731 | #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ | |
732 | #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ | |
733 | #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ | |
734 | #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ | |
735 | ||
736 | #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ | |
737 | #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ | |
738 | #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ | |
739 | #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ | |
740 | ||
741 | #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ | |
742 | ||
743 | #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ | |
744 | #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ | |
745 | #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ | |
746 | ||
747 | #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ | |
748 | #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ | |
749 | #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ | |
750 | ||
751 | #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ | |
752 | #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ | |
753 | #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ | |
754 | ||
755 | #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ | |
756 | #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ | |
757 | #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ | |
758 | ||
759 | #endif | |
760 | ||
80a18573 TP |
761 | /* PWRMODE register M field values */ |
762 | ||
763 | #define PWRMODE_IDLE 0x1 | |
764 | #define PWRMODE_STANDBY 0x2 | |
765 | #define PWRMODE_SLEEP 0x3 | |
766 | #define PWRMODE_DEEPSLEEP 0x7 | |
767 | ||
1da177e4 | 768 | #endif |