projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/mainstone.h |
| 1da177e4 LT |
3 | * |
| 4 | * Author: Nicolas Pitre | |
| 5 | * Created: Nov 14, 2002 | |
| 6 | * Copyright: MontaVista Software Inc. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef ASM_ARCH_MAINSTONE_H | |
| 14 | #define ASM_ARCH_MAINSTONE_H | |
| 15 | ||
| dc38d826 RH |
16 | #include <mach/irqs.h> |
| 17 | ||
| 1da177e4 LT |
18 | #define MST_ETH_PHYS PXA_CS4_PHYS |
| 19 | ||
| 20 | #define MST_FPGA_PHYS PXA_CS2_PHYS | |
| 21 | #define MST_FPGA_VIRT (0xf0000000) | |
| 22 | #define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) | |
| 23 | #define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) | |
| 24 | ||
| 25 | #ifndef __ASSEMBLY__ | |
| 26 | # define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) | |
| 27 | #else | |
| 28 | # define __MST_REG(x) MST_P2V(x) | |
| 29 | #endif | |
| 30 | ||
| 31 | /* board level registers in the FPGA */ | |
| 32 | ||
| 33 | #define MST_LEDDAT1 __MST_REG(0x08000010) | |
| 34 | #define MST_LEDDAT2 __MST_REG(0x08000014) | |
| 35 | #define MST_LEDCTRL __MST_REG(0x08000040) | |
| 36 | #define MST_GPSWR __MST_REG(0x08000060) | |
| 37 | #define MST_MSCWR1 __MST_REG(0x08000080) | |
| 38 | #define MST_MSCWR2 __MST_REG(0x08000084) | |
| 39 | #define MST_MSCWR3 __MST_REG(0x08000088) | |
| 40 | #define MST_MSCRD __MST_REG(0x08000090) | |
| 41 | #define MST_INTMSKENA __MST_REG(0x080000c0) | |
| 42 | #define MST_INTSETCLR __MST_REG(0x080000d0) | |
| 43 | #define MST_PCMCIA0 __MST_REG(0x080000e0) | |
| 44 | #define MST_PCMCIA1 __MST_REG(0x080000e4) | |
| 45 | ||
| 46 | #define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ | |
| 47 | #define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ | |
| 48 | #define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ | |
| 49 | #define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ | |
| 50 | #define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ | |
| 51 | #define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ | |
| 52 | #define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ | |
| 53 | #define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ | |
| 54 | #define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ | |
| 55 | ||
| 56 | #define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ | |
| 57 | #define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ | |
| 58 | #define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ | |
| 59 | #define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ | |
| 60 | #define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ | |
| 61 | ||
| 62 | #define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ | |
| 63 | #define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ | |
| 64 | #define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ | |
| 65 | #define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ | |
| 66 | #define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ | |
| 67 | ||
| 68 | #define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ | |
| 69 | #define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ | |
| 70 | #define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ | |
| 71 | #define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ | |
| 72 | #define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ | |
| 73 | #define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ | |
| 74 | #define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ | |
| 75 | ||
| 76 | #define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ | |
| 77 | #define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ | |
| 78 | #define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ | |
| 79 | ||
| 80 | #define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ | |
| 81 | #define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ | |
| 82 | #define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ | |
| 83 | #define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ | |
| 84 | #define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ | |
| 85 | #define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ | |
| 86 | #define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ | |
| 87 | #define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ | |
| 88 | #define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ | |
| 89 | #define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ | |
| 90 | ||
| 91 | #define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ | |
| 92 | #define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ | |
| 93 | #define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ | |
| 94 | #define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ | |
| 95 | #define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ | |
| 96 | #define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ | |
| 97 | #define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ | |
| 98 | #define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ | |
| 99 | #define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ | |
| 100 | #define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ | |
| 101 | #define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ | |
| 102 | #define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ | |
| 103 | #define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ | |
| 104 | #define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ | |
| 105 | ||
| 106 | #define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ | |
| 107 | #define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ | |
| 108 | #define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ | |
| 109 | #define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ | |
| 110 | #define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ | |
| 111 | #define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ | |
| 112 | #define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ | |
| 113 | #define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ | |
| 114 | ||
| 115 | #define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ | |
| 116 | #define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ | |
| 117 | #define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ | |
| 118 | #define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ | |
| 119 | #define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ | |
| 120 | #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ | |
| 121 | ||
| 0dc726bb | 122 | /* board specific IRQs */ |
| 27768863 RJ |
123 | #define MAINSTONE_NR_IRQS IRQ_BOARD_START |
| 124 | ||
| 125 | #define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x)) | |
| 0dc726bb EM |
126 | #define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) |
| 127 | #define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) | |
| 128 | #define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) | |
| 129 | #define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) | |
| 130 | #define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) | |
| 131 | #define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) | |
| 132 | #define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) | |
| 133 | #define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) | |
| 134 | #define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) | |
| 135 | #define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) | |
| 136 | #define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) | |
| 137 | #define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) | |
| 138 | #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) | |
| 139 | #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) | |
| 140 | ||
| 1da177e4 | 141 | #endif |