Merge remote-tracking branch 'asoc/topic/rt5670' into asoc-next
[linux-2.6-block.git] / arch / arm / mach-pxa / include / mach / hx4700.h
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1/*
2 * GPIO and IRQ definitions for HP iPAQ hx4700
3 *
4 * Copyright (c) 2008 Philipp Zabel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef _HX4700_H_
13#define _HX4700_H_
14
15#include <linux/gpio.h>
16#include <linux/mfd/asic3.h>
c02b50e9 17#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
d3ca1952 18
1a8d5fab 19#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
d3ca1952 20#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
6ac6b817 21#define HX4700_NR_IRQS (IRQ_BOARD_START + 70)
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22
23/*
24 * PXA GPIOs
25 */
26
27#define GPIO0_HX4700_nKEY_POWER 0
28#define GPIO12_HX4700_ASIC3_IRQ 12
29#define GPIO13_HX4700_W3220_IRQ 13
30#define GPIO14_HX4700_nWLAN_IRQ 14
31#define GPIO18_HX4700_RDY 18
32#define GPIO22_HX4700_LCD_RL 22
33#define GPIO27_HX4700_CODEC_ON 27
34#define GPIO32_HX4700_RS232_ON 32
35#define GPIO52_HX4700_CPU_nBATT_FAULT 52
36#define GPIO58_HX4700_TSC2046_nPENIRQ 58
37#define GPIO59_HX4700_LCD_PC1 59
38#define GPIO60_HX4700_CF_RNB 60
39#define GPIO61_HX4700_W3220_nRESET 61
40#define GPIO62_HX4700_LCD_nRESET 62
41#define GPIO63_HX4700_CPU_SS_nRESET 63
42#define GPIO65_HX4700_TSC2046_PEN_PU 65
43#define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66
44#define GPIO67_HX4700_EUART_PS 67
45#define GPIO70_HX4700_LCD_SLIN1 70
46#define GPIO71_HX4700_ASIC3_nRESET 71
47#define GPIO72_HX4700_BQ24022_nCHARGE_EN 72
48#define GPIO73_HX4700_LCD_UD_1 73
49#define GPIO75_HX4700_EARPHONE_nDET 75
50#define GPIO76_HX4700_USBC_PUEN 76
51#define GPIO81_HX4700_CPU_GP_nRESET 81
52#define GPIO82_HX4700_EUART_RESET 82
53#define GPIO83_HX4700_WLAN_nRESET 83
54#define GPIO84_HX4700_LCD_SQN 84
55#define GPIO85_HX4700_nPCE1 85
56#define GPIO88_HX4700_TSC2046_CS 88
57#define GPIO91_HX4700_FLASH_VPEN 91
58#define GPIO92_HX4700_HP_DRIVER 92
59#define GPIO93_HX4700_EUART_INT 93
60#define GPIO94_HX4700_KEY_MAIL 94
61#define GPIO95_HX4700_BATT_OFF 95
62#define GPIO96_HX4700_BQ24022_ISET2 96
63#define GPIO97_HX4700_nBL_DETECT 97
64#define GPIO99_HX4700_KEY_CONTACTS 99
65#define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */
66#define GPIO102_HX4700_SYNAPTICS_POWER_ON 102
67#define GPIO103_HX4700_SYNAPTICS_INT 103
68#define GPIO105_HX4700_nIR_ON 105
69#define GPIO106_HX4700_CPU_BT_nRESET 106
70#define GPIO107_HX4700_SPK_nSD 107
71#define GPIO109_HX4700_CODEC_nPDN 109
72#define GPIO110_HX4700_LCD_LVDD_3V3_ON 110
73#define GPIO111_HX4700_LCD_AVDD_3V3_ON 111
74#define GPIO112_HX4700_LCD_N2V7_7V3_ON 112
75#define GPIO114_HX4700_CF_RESET 114
76#define GPIO116_HX4700_CPU_HW_nRESET 116
77
78/*
79 * ASIC3 GPIOs
80 */
81
82#define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32)
83#define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48)
84
85#define GPIOC0_LED_RED (GPIOC_BASE + 0)
86#define GPIOC1_LED_GREEN (GPIOC_BASE + 1)
87#define GPIOC2_LED_BLUE (GPIOC_BASE + 2)
88#define GPIOC3_nSD_CS (GPIOC_BASE + 3)
89#define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */
90#define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */
91#define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */
92#define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */
93#define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */
94#define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */
95#define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */
96#define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */
97#define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */
98#define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */
99#define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */
100#define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */
101
102#define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */
103#define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1)
104#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2)
105#define GPIOD3_nKEY_HOME (GPIOD_BASE + 3)
106#define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */
107#define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */
108#define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6)
109#define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7)
110#define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */
111#define GPIOD9_nAC_IN (GPIOD_BASE + 9)
112#define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */
113#define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */
114#define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */
115#define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */
116#define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14)
117#define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */
118
119/*
120 * EGPIOs
121 */
122
123#define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */
124#define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */
125#define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */
126#define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */
127#define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */
128#define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */
129#define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */
130#define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */
131#define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */
132
133#endif /* _HX4700_H_ */