Commit | Line | Data |
---|---|---|
3696a8a4 | 1 | /* |
da591937 | 2 | * linux/arch/arm/mach-pxa/cm-x2xx.c |
3696a8a4 | 3 | * |
4adc5fb6 | 4 | * Copyright (C) 2008 CompuLab, Ltd. |
3696a8a4 MR |
5 | * Mike Rapoport <mike@compulab.co.il> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
3696a8a4 | 12 | #include <linux/platform_device.h> |
2eaa03b5 | 13 | #include <linux/syscore_ops.h> |
2f01a973 MR |
14 | #include <linux/irq.h> |
15 | #include <linux/gpio.h> | |
a927ef89 | 16 | #include <linux/regulator/machine.h> |
3696a8a4 MR |
17 | |
18 | #include <linux/dm9000.h> | |
2f01a973 | 19 | #include <linux/leds.h> |
3696a8a4 MR |
20 | |
21 | #include <asm/mach/arch.h> | |
22 | #include <asm/mach-types.h> | |
23 | #include <asm/mach/map.h> | |
24 | ||
ca0e687c | 25 | #include <mach/pxa25x.h> |
e0347c52 | 26 | #undef GPIO24_SSP1_SFRM |
ca0e687c | 27 | #include <mach/pxa27x.h> |
a09e64fb | 28 | #include <mach/audio.h> |
293b2da1 | 29 | #include <linux/platform_data/video-pxafb.h> |
ad68bb9f | 30 | #include <mach/smemc.h> |
3696a8a4 MR |
31 | |
32 | #include <asm/hardware/it8152.h> | |
33 | ||
34 | #include "generic.h" | |
7d76e3f1 | 35 | #include "cm-x2xx-pci.h" |
3696a8a4 | 36 | |
a7f3f030 | 37 | extern void cmx255_init(void); |
4adc5fb6 MR |
38 | extern void cmx270_init(void); |
39 | ||
6ac6b817 HZ |
40 | /* reserve IRQs for IT8152 */ |
41 | #define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40) | |
42 | ||
2f01a973 | 43 | /* virtual addresses for statically mapped regions */ |
97b09da4 | 44 | #define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000) |
da591937 | 45 | #define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE) |
2f01a973 | 46 | |
4adc5fb6 | 47 | /* physical address if local-bus attached devices */ |
a7f3f030 | 48 | #define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22)) |
da591937 MR |
49 | #define CMX270_DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22)) |
50 | ||
51 | /* leds */ | |
a7f3f030 MR |
52 | #define CMX255_GPIO_RED (27) |
53 | #define CMX255_GPIO_GREEN (32) | |
da591937 MR |
54 | #define CMX270_GPIO_RED (93) |
55 | #define CMX270_GPIO_GREEN (94) | |
3696a8a4 | 56 | |
2f01a973 | 57 | /* GPIO IRQ usage */ |
a7f3f030 | 58 | #define GPIO22_ETHIRQ (22) |
2f01a973 | 59 | #define GPIO10_ETHIRQ (10) |
a7f3f030 | 60 | #define CMX255_GPIO_IT8152_IRQ (0) |
da591937 | 61 | #define CMX270_GPIO_IT8152_IRQ (22) |
2f01a973 | 62 | |
6384fdad HZ |
63 | #define CMX255_ETHIRQ PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ) |
64 | #define CMX270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ) | |
2f01a973 MR |
65 | |
66 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | |
a7f3f030 MR |
67 | static struct resource cmx255_dm9000_resource[] = { |
68 | [0] = { | |
69 | .start = CMX255_DM9000_PHYS_BASE, | |
70 | .end = CMX255_DM9000_PHYS_BASE + 3, | |
71 | .flags = IORESOURCE_MEM, | |
72 | }, | |
73 | [1] = { | |
74 | .start = CMX255_DM9000_PHYS_BASE + 4, | |
75 | .end = CMX255_DM9000_PHYS_BASE + 4 + 500, | |
76 | .flags = IORESOURCE_MEM, | |
77 | }, | |
78 | [2] = { | |
79 | .start = CMX255_ETHIRQ, | |
80 | .end = CMX255_ETHIRQ, | |
81 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | |
82 | } | |
83 | }; | |
84 | ||
2f01a973 | 85 | static struct resource cmx270_dm9000_resource[] = { |
3696a8a4 | 86 | [0] = { |
da591937 MR |
87 | .start = CMX270_DM9000_PHYS_BASE, |
88 | .end = CMX270_DM9000_PHYS_BASE + 3, | |
3696a8a4 MR |
89 | .flags = IORESOURCE_MEM, |
90 | }, | |
91 | [1] = { | |
da591937 MR |
92 | .start = CMX270_DM9000_PHYS_BASE + 8, |
93 | .end = CMX270_DM9000_PHYS_BASE + 8 + 500, | |
3696a8a4 MR |
94 | .flags = IORESOURCE_MEM, |
95 | }, | |
96 | [2] = { | |
97 | .start = CMX270_ETHIRQ, | |
98 | .end = CMX270_ETHIRQ, | |
2f01a973 | 99 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
3696a8a4 MR |
100 | } |
101 | }; | |
102 | ||
2f01a973 | 103 | static struct dm9000_plat_data cmx270_dm9000_platdata = { |
bff22c9b | 104 | .flags = DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM, |
3696a8a4 MR |
105 | }; |
106 | ||
da591937 | 107 | static struct platform_device cmx2xx_dm9000_device = { |
3696a8a4 MR |
108 | .name = "dm9000", |
109 | .id = 0, | |
2f01a973 | 110 | .num_resources = ARRAY_SIZE(cmx270_dm9000_resource), |
3696a8a4 | 111 | .dev = { |
2f01a973 | 112 | .platform_data = &cmx270_dm9000_platdata, |
3696a8a4 MR |
113 | } |
114 | }; | |
115 | ||
da591937 | 116 | static void __init cmx2xx_init_dm9000(void) |
2f01a973 | 117 | { |
a7f3f030 MR |
118 | if (cpu_is_pxa25x()) |
119 | cmx2xx_dm9000_device.resource = cmx255_dm9000_resource; | |
120 | else | |
121 | cmx2xx_dm9000_device.resource = cmx270_dm9000_resource; | |
da591937 | 122 | platform_device_register(&cmx2xx_dm9000_device); |
2f01a973 MR |
123 | } |
124 | #else | |
da591937 | 125 | static inline void cmx2xx_init_dm9000(void) {} |
2f01a973 MR |
126 | #endif |
127 | ||
128 | /* UCB1400 touchscreen controller */ | |
129 | #if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) | |
da591937 | 130 | static struct platform_device cmx2xx_ts_device = { |
50f6bb0a | 131 | .name = "ucb1400_core", |
3696a8a4 MR |
132 | .id = -1, |
133 | }; | |
134 | ||
da591937 | 135 | static void __init cmx2xx_init_touchscreen(void) |
2f01a973 | 136 | { |
da591937 | 137 | platform_device_register(&cmx2xx_ts_device); |
2f01a973 MR |
138 | } |
139 | #else | |
da591937 | 140 | static inline void cmx2xx_init_touchscreen(void) {} |
2f01a973 MR |
141 | #endif |
142 | ||
2f01a973 MR |
143 | /* CM-X270 LEDs */ |
144 | #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) | |
da591937 | 145 | static struct gpio_led cmx2xx_leds[] = { |
2f01a973 | 146 | [0] = { |
da591937 | 147 | .name = "cm-x2xx:red", |
2f01a973 | 148 | .default_trigger = "nand-disk", |
2f01a973 MR |
149 | .active_low = 1, |
150 | }, | |
151 | [1] = { | |
da591937 | 152 | .name = "cm-x2xx:green", |
2f01a973 | 153 | .default_trigger = "heartbeat", |
2f01a973 MR |
154 | .active_low = 1, |
155 | }, | |
156 | }; | |
157 | ||
da591937 MR |
158 | static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = { |
159 | .num_leds = ARRAY_SIZE(cmx2xx_leds), | |
160 | .leds = cmx2xx_leds, | |
2f01a973 MR |
161 | }; |
162 | ||
da591937 | 163 | static struct platform_device cmx2xx_led_device = { |
2f01a973 | 164 | .name = "leds-gpio", |
3696a8a4 | 165 | .id = -1, |
2f01a973 | 166 | .dev = { |
da591937 | 167 | .platform_data = &cmx2xx_gpio_led_pdata, |
2f01a973 | 168 | }, |
3696a8a4 MR |
169 | }; |
170 | ||
da591937 | 171 | static void __init cmx2xx_init_leds(void) |
2f01a973 | 172 | { |
a7f3f030 MR |
173 | if (cpu_is_pxa25x()) { |
174 | cmx2xx_leds[0].gpio = CMX255_GPIO_RED; | |
175 | cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN; | |
176 | } else { | |
177 | cmx2xx_leds[0].gpio = CMX270_GPIO_RED; | |
178 | cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN; | |
179 | } | |
da591937 | 180 | platform_device_register(&cmx2xx_led_device); |
2f01a973 MR |
181 | } |
182 | #else | |
da591937 | 183 | static inline void cmx2xx_init_leds(void) {} |
2f01a973 MR |
184 | #endif |
185 | ||
2f01a973 | 186 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
3696a8a4 MR |
187 | /* |
188 | Display definitions | |
189 | keep these for backwards compatibility, although symbolic names (as | |
190 | e.g. in lpd270.c) looks better | |
191 | */ | |
192 | #define MTYPE_STN320x240 0 | |
193 | #define MTYPE_TFT640x480 1 | |
194 | #define MTYPE_CRT640x480 2 | |
195 | #define MTYPE_CRT800x600 3 | |
196 | #define MTYPE_TFT320x240 6 | |
197 | #define MTYPE_STN640x480 7 | |
198 | ||
199 | static struct pxafb_mode_info generic_stn_320x240_mode = { | |
200 | .pixclock = 76923, | |
201 | .bpp = 8, | |
202 | .xres = 320, | |
203 | .yres = 240, | |
204 | .hsync_len = 3, | |
205 | .vsync_len = 2, | |
206 | .left_margin = 3, | |
207 | .upper_margin = 0, | |
208 | .right_margin = 3, | |
209 | .lower_margin = 0, | |
210 | .sync = (FB_SYNC_HOR_HIGH_ACT | | |
211 | FB_SYNC_VERT_HIGH_ACT), | |
212 | .cmap_greyscale = 0, | |
213 | }; | |
214 | ||
215 | static struct pxafb_mach_info generic_stn_320x240 = { | |
216 | .modes = &generic_stn_320x240_mode, | |
217 | .num_modes = 1, | |
9587319b EM |
218 | .lcd_conn = LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\ |
219 | LCD_AC_BIAS_FREQ(0xff), | |
3696a8a4 MR |
220 | .cmap_inverse = 0, |
221 | .cmap_static = 0, | |
222 | }; | |
223 | ||
224 | static struct pxafb_mode_info generic_tft_640x480_mode = { | |
225 | .pixclock = 38461, | |
226 | .bpp = 8, | |
227 | .xres = 640, | |
228 | .yres = 480, | |
229 | .hsync_len = 60, | |
230 | .vsync_len = 2, | |
231 | .left_margin = 70, | |
232 | .upper_margin = 10, | |
233 | .right_margin = 70, | |
234 | .lower_margin = 5, | |
235 | .sync = 0, | |
236 | .cmap_greyscale = 0, | |
237 | }; | |
238 | ||
239 | static struct pxafb_mach_info generic_tft_640x480 = { | |
240 | .modes = &generic_tft_640x480_mode, | |
241 | .num_modes = 1, | |
9587319b EM |
242 | .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\ |
243 | LCD_AC_BIAS_FREQ(0xff), | |
3696a8a4 MR |
244 | .cmap_inverse = 0, |
245 | .cmap_static = 0, | |
246 | }; | |
247 | ||
248 | static struct pxafb_mode_info generic_crt_640x480_mode = { | |
249 | .pixclock = 38461, | |
250 | .bpp = 8, | |
251 | .xres = 640, | |
252 | .yres = 480, | |
253 | .hsync_len = 63, | |
254 | .vsync_len = 2, | |
255 | .left_margin = 81, | |
256 | .upper_margin = 33, | |
257 | .right_margin = 16, | |
258 | .lower_margin = 10, | |
259 | .sync = (FB_SYNC_HOR_HIGH_ACT | | |
260 | FB_SYNC_VERT_HIGH_ACT), | |
261 | .cmap_greyscale = 0, | |
262 | }; | |
263 | ||
264 | static struct pxafb_mach_info generic_crt_640x480 = { | |
265 | .modes = &generic_crt_640x480_mode, | |
266 | .num_modes = 1, | |
9587319b | 267 | .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff), |
3696a8a4 MR |
268 | .cmap_inverse = 0, |
269 | .cmap_static = 0, | |
270 | }; | |
271 | ||
272 | static struct pxafb_mode_info generic_crt_800x600_mode = { | |
273 | .pixclock = 28846, | |
274 | .bpp = 8, | |
275 | .xres = 800, | |
276 | .yres = 600, | |
277 | .hsync_len = 63, | |
278 | .vsync_len = 2, | |
279 | .left_margin = 26, | |
280 | .upper_margin = 21, | |
281 | .right_margin = 26, | |
282 | .lower_margin = 11, | |
283 | .sync = (FB_SYNC_HOR_HIGH_ACT | | |
284 | FB_SYNC_VERT_HIGH_ACT), | |
285 | .cmap_greyscale = 0, | |
286 | }; | |
287 | ||
288 | static struct pxafb_mach_info generic_crt_800x600 = { | |
289 | .modes = &generic_crt_800x600_mode, | |
290 | .num_modes = 1, | |
9587319b | 291 | .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff), |
3696a8a4 MR |
292 | .cmap_inverse = 0, |
293 | .cmap_static = 0, | |
294 | }; | |
295 | ||
296 | static struct pxafb_mode_info generic_tft_320x240_mode = { | |
297 | .pixclock = 134615, | |
298 | .bpp = 16, | |
299 | .xres = 320, | |
300 | .yres = 240, | |
301 | .hsync_len = 63, | |
302 | .vsync_len = 7, | |
303 | .left_margin = 75, | |
304 | .upper_margin = 0, | |
305 | .right_margin = 15, | |
306 | .lower_margin = 15, | |
307 | .sync = 0, | |
308 | .cmap_greyscale = 0, | |
309 | }; | |
310 | ||
311 | static struct pxafb_mach_info generic_tft_320x240 = { | |
312 | .modes = &generic_tft_320x240_mode, | |
313 | .num_modes = 1, | |
9587319b | 314 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff), |
3696a8a4 MR |
315 | .cmap_inverse = 0, |
316 | .cmap_static = 0, | |
317 | }; | |
318 | ||
319 | static struct pxafb_mode_info generic_stn_640x480_mode = { | |
320 | .pixclock = 57692, | |
321 | .bpp = 8, | |
322 | .xres = 640, | |
323 | .yres = 480, | |
324 | .hsync_len = 4, | |
325 | .vsync_len = 2, | |
326 | .left_margin = 10, | |
327 | .upper_margin = 5, | |
328 | .right_margin = 10, | |
329 | .lower_margin = 5, | |
330 | .sync = (FB_SYNC_HOR_HIGH_ACT | | |
331 | FB_SYNC_VERT_HIGH_ACT), | |
332 | .cmap_greyscale = 0, | |
333 | }; | |
334 | ||
335 | static struct pxafb_mach_info generic_stn_640x480 = { | |
336 | .modes = &generic_stn_640x480_mode, | |
337 | .num_modes = 1, | |
9587319b | 338 | .lcd_conn = LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff), |
3696a8a4 MR |
339 | .cmap_inverse = 0, |
340 | .cmap_static = 0, | |
341 | }; | |
342 | ||
da591937 | 343 | static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480; |
3696a8a4 | 344 | |
da591937 | 345 | static int __init cmx2xx_set_display(char *str) |
3696a8a4 MR |
346 | { |
347 | int disp_type = simple_strtol(str, NULL, 0); | |
348 | switch (disp_type) { | |
349 | case MTYPE_STN320x240: | |
da591937 | 350 | cmx2xx_display = &generic_stn_320x240; |
3696a8a4 MR |
351 | break; |
352 | case MTYPE_TFT640x480: | |
da591937 | 353 | cmx2xx_display = &generic_tft_640x480; |
3696a8a4 MR |
354 | break; |
355 | case MTYPE_CRT640x480: | |
da591937 | 356 | cmx2xx_display = &generic_crt_640x480; |
3696a8a4 MR |
357 | break; |
358 | case MTYPE_CRT800x600: | |
da591937 | 359 | cmx2xx_display = &generic_crt_800x600; |
3696a8a4 MR |
360 | break; |
361 | case MTYPE_TFT320x240: | |
da591937 | 362 | cmx2xx_display = &generic_tft_320x240; |
3696a8a4 MR |
363 | break; |
364 | case MTYPE_STN640x480: | |
da591937 | 365 | cmx2xx_display = &generic_stn_640x480; |
3696a8a4 MR |
366 | break; |
367 | default: /* fallback to CRT 640x480 */ | |
da591937 | 368 | cmx2xx_display = &generic_crt_640x480; |
3696a8a4 MR |
369 | break; |
370 | } | |
371 | return 1; | |
372 | } | |
373 | ||
374 | /* | |
375 | This should be done really early to get proper configuration for | |
376 | frame buffer. | |
da591937 | 377 | Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader |
3696a8a4 MR |
378 | has limitied line length for kernel command line, and also it will |
379 | break compatibitlty with proprietary releases already in field. | |
380 | */ | |
da591937 | 381 | __setup("monitor=", cmx2xx_set_display); |
3696a8a4 | 382 | |
da591937 | 383 | static void __init cmx2xx_init_display(void) |
2f01a973 | 384 | { |
4321e1a1 | 385 | pxa_set_fb_info(NULL, cmx2xx_display); |
2f01a973 MR |
386 | } |
387 | #else | |
da591937 | 388 | static inline void cmx2xx_init_display(void) {} |
2f01a973 MR |
389 | #endif |
390 | ||
3696a8a4 MR |
391 | #ifdef CONFIG_PM |
392 | static unsigned long sleep_save_msc[10]; | |
393 | ||
2eaa03b5 | 394 | static int cmx2xx_suspend(void) |
3696a8a4 | 395 | { |
da591937 | 396 | cmx2xx_pci_suspend(); |
3696a8a4 MR |
397 | |
398 | /* save MSC registers */ | |
ad68bb9f MV |
399 | sleep_save_msc[0] = __raw_readl(MSC0); |
400 | sleep_save_msc[1] = __raw_readl(MSC1); | |
401 | sleep_save_msc[2] = __raw_readl(MSC2); | |
3696a8a4 MR |
402 | |
403 | /* setup power saving mode registers */ | |
404 | PCFR = 0x0; | |
405 | PSLR = 0xff400000; | |
406 | PMCR = 0x00000005; | |
407 | PWER = 0x80000000; | |
408 | PFER = 0x00000000; | |
409 | PRER = 0x00000000; | |
410 | PGSR0 = 0xC0018800; | |
411 | PGSR1 = 0x004F0002; | |
412 | PGSR2 = 0x6021C000; | |
413 | PGSR3 = 0x00020000; | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
2eaa03b5 | 418 | static void cmx2xx_resume(void) |
3696a8a4 | 419 | { |
da591937 | 420 | cmx2xx_pci_resume(); |
3696a8a4 MR |
421 | |
422 | /* restore MSC registers */ | |
ad68bb9f MV |
423 | __raw_writel(sleep_save_msc[0], MSC0); |
424 | __raw_writel(sleep_save_msc[1], MSC1); | |
425 | __raw_writel(sleep_save_msc[2], MSC2); | |
3696a8a4 MR |
426 | } |
427 | ||
2eaa03b5 | 428 | static struct syscore_ops cmx2xx_pm_syscore_ops = { |
da591937 MR |
429 | .resume = cmx2xx_resume, |
430 | .suspend = cmx2xx_suspend, | |
3696a8a4 MR |
431 | }; |
432 | ||
da591937 | 433 | static int __init cmx2xx_pm_init(void) |
3696a8a4 | 434 | { |
2eaa03b5 RW |
435 | register_syscore_ops(&cmx2xx_pm_syscore_ops); |
436 | ||
437 | return 0; | |
3696a8a4 MR |
438 | } |
439 | #else | |
da591937 | 440 | static int __init cmx2xx_pm_init(void) { return 0; } |
3696a8a4 MR |
441 | #endif |
442 | ||
2f01a973 | 443 | #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) |
da591937 | 444 | static void __init cmx2xx_init_ac97(void) |
3696a8a4 | 445 | { |
9f19d638 | 446 | pxa_set_ac97_info(NULL); |
2f01a973 MR |
447 | } |
448 | #else | |
da591937 | 449 | static inline void cmx2xx_init_ac97(void) {} |
2f01a973 | 450 | #endif |
3696a8a4 | 451 | |
da591937 MR |
452 | static void __init cmx2xx_init(void) |
453 | { | |
cc155c6f RK |
454 | pxa_set_ffuart_info(NULL); |
455 | pxa_set_btuart_info(NULL); | |
456 | pxa_set_stuart_info(NULL); | |
457 | ||
da591937 MR |
458 | cmx2xx_pm_init(); |
459 | ||
a7f3f030 MR |
460 | if (cpu_is_pxa25x()) |
461 | cmx255_init(); | |
462 | else | |
463 | cmx270_init(); | |
da591937 MR |
464 | |
465 | cmx2xx_init_dm9000(); | |
466 | cmx2xx_init_display(); | |
467 | cmx2xx_init_ac97(); | |
468 | cmx2xx_init_touchscreen(); | |
469 | cmx2xx_init_leds(); | |
a927ef89 RJ |
470 | |
471 | regulator_has_full_constraints(); | |
da591937 MR |
472 | } |
473 | ||
474 | static void __init cmx2xx_init_irq(void) | |
3696a8a4 | 475 | { |
a7f3f030 MR |
476 | if (cpu_is_pxa25x()) { |
477 | pxa25x_init_irq(); | |
478 | cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ); | |
479 | } else { | |
480 | pxa27x_init_irq(); | |
481 | cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ); | |
482 | } | |
2f01a973 | 483 | } |
3696a8a4 | 484 | |
2f01a973 MR |
485 | #ifdef CONFIG_PCI |
486 | /* Map PCI companion statically */ | |
da591937 | 487 | static struct map_desc cmx2xx_io_desc[] __initdata = { |
2f01a973 | 488 | [0] = { /* PCI bridge */ |
97b09da4 | 489 | .virtual = (unsigned long)CMX2XX_IT8152_VIRT, |
2f01a973 MR |
490 | .pfn = __phys_to_pfn(PXA_CS4_PHYS), |
491 | .length = SZ_64M, | |
492 | .type = MT_DEVICE | |
493 | }, | |
494 | }; | |
3696a8a4 | 495 | |
da591937 | 496 | static void __init cmx2xx_map_io(void) |
2f01a973 | 497 | { |
851982c1 MV |
498 | if (cpu_is_pxa25x()) |
499 | pxa25x_map_io(); | |
500 | ||
501 | if (cpu_is_pxa27x()) | |
502 | pxa27x_map_io(); | |
503 | ||
da591937 | 504 | iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc)); |
3696a8a4 | 505 | |
da591937 | 506 | it8152_base_address = CMX2XX_IT8152_VIRT; |
3696a8a4 | 507 | } |
2f01a973 | 508 | #else |
da591937 | 509 | static void __init cmx2xx_map_io(void) |
3696a8a4 | 510 | { |
851982c1 MV |
511 | if (cpu_is_pxa25x()) |
512 | pxa25x_map_io(); | |
513 | ||
514 | if (cpu_is_pxa27x()) | |
515 | pxa27x_map_io(); | |
3696a8a4 | 516 | } |
2f01a973 | 517 | #endif |
3696a8a4 | 518 | |
da591937 | 519 | MACHINE_START(ARMCORE, "Compulab CM-X2XX") |
7375aba6 | 520 | .atag_offset = 0x100, |
da591937 | 521 | .map_io = cmx2xx_map_io, |
6ac6b817 | 522 | .nr_irqs = CMX2XX_NR_IRQS, |
da591937 | 523 | .init_irq = cmx2xx_init_irq, |
8a97ae2f EM |
524 | /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */ |
525 | .handle_irq = pxa25x_handle_irq, | |
6bb27d73 | 526 | .init_time = pxa_timer_init, |
da591937 | 527 | .init_machine = cmx2xx_init, |
805e88dc NP |
528 | #ifdef CONFIG_PCI |
529 | .dma_zone_size = SZ_64M, | |
530 | #endif | |
271a74fc | 531 | .restart = pxa_restart, |
3696a8a4 | 532 | MACHINE_END |