Commit | Line | Data |
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2558bd99 RY |
1 | /* |
2 | * power management entry for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/suspend.h> | |
11 | #include <linux/slab.h> | |
b2dcb872 | 12 | #include <linux/module.h> |
2558bd99 RY |
13 | #include <linux/of.h> |
14 | #include <linux/of_address.h> | |
15 | #include <linux/of_device.h> | |
16 | #include <linux/of_platform.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/rtc/sirfsoc_rtciobrg.h> | |
19 | #include <asm/suspend.h> | |
20 | #include <asm/hardware/cache-l2x0.h> | |
21 | ||
22 | #include "pm.h" | |
23 | ||
24 | /* | |
25 | * suspend asm codes will access these to make DRAM become self-refresh and | |
26 | * system sleep | |
27 | */ | |
28 | u32 sirfsoc_pwrc_base; | |
29 | void __iomem *sirfsoc_memc_base; | |
30 | ||
31 | static void sirfsoc_set_wakeup_source(void) | |
32 | { | |
33 | u32 pwr_trigger_en_reg; | |
34 | pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + | |
35 | SIRFSOC_PWRC_TRIGGER_EN); | |
36 | #define X_ON_KEY_B (1 << 0) | |
37 | sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B, | |
38 | sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); | |
39 | } | |
40 | ||
41 | static void sirfsoc_set_sleep_mode(u32 mode) | |
42 | { | |
43 | u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + | |
44 | SIRFSOC_PWRC_PDN_CTRL); | |
45 | sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1); | |
46 | sleep_mode |= mode << 1; | |
47 | sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base + | |
48 | SIRFSOC_PWRC_PDN_CTRL); | |
49 | } | |
50 | ||
51 | static int sirfsoc_pre_suspend_power_off(void) | |
52 | { | |
53 | u32 wakeup_entry = virt_to_phys(cpu_resume); | |
54 | ||
55 | sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base + | |
56 | SIRFSOC_PWRC_SCRATCH_PAD1); | |
57 | ||
58 | sirfsoc_set_wakeup_source(); | |
59 | ||
60 | sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE); | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
65 | static int sirfsoc_pm_enter(suspend_state_t state) | |
66 | { | |
67 | switch (state) { | |
68 | case PM_SUSPEND_MEM: | |
69 | sirfsoc_pre_suspend_power_off(); | |
70 | ||
71 | outer_flush_all(); | |
72 | outer_disable(); | |
73 | /* go zzz */ | |
74 | cpu_suspend(0, sirfsoc_finish_suspend); | |
24469df4 | 75 | outer_resume(); |
2558bd99 RY |
76 | break; |
77 | default: | |
78 | return -EINVAL; | |
79 | } | |
80 | return 0; | |
81 | } | |
82 | ||
83 | static const struct platform_suspend_ops sirfsoc_pm_ops = { | |
84 | .enter = sirfsoc_pm_enter, | |
85 | .valid = suspend_valid_only_mem, | |
86 | }; | |
87 | ||
a4b4674e | 88 | int __init sirfsoc_pm_init(void) |
2558bd99 RY |
89 | { |
90 | suspend_set_ops(&sirfsoc_pm_ops); | |
91 | return 0; | |
92 | } | |
2558bd99 RY |
93 | |
94 | static const struct of_device_id pwrc_ids[] = { | |
95 | { .compatible = "sirf,prima2-pwrc" }, | |
96 | {} | |
97 | }; | |
98 | ||
99 | static int __init sirfsoc_of_pwrc_init(void) | |
100 | { | |
101 | struct device_node *np; | |
102 | ||
103 | np = of_find_matching_node(NULL, pwrc_ids); | |
104 | if (!np) | |
105 | panic("unable to find compatible pwrc node in dtb\n"); | |
106 | ||
107 | /* | |
108 | * pwrc behind rtciobrg is not located in memory space | |
109 | * though the property is named reg. reg only means base | |
110 | * offset for pwrc. then of_iomap is not suitable here. | |
111 | */ | |
112 | if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base)) | |
113 | panic("unable to find base address of pwrc node in dtb\n"); | |
114 | ||
115 | of_node_put(np); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | postcore_initcall(sirfsoc_of_pwrc_init); | |
120 | ||
121 | static const struct of_device_id memc_ids[] = { | |
122 | { .compatible = "sirf,prima2-memc" }, | |
123 | {} | |
124 | }; | |
125 | ||
351a102d | 126 | static int sirfsoc_memc_probe(struct platform_device *op) |
2558bd99 RY |
127 | { |
128 | struct device_node *np = op->dev.of_node; | |
129 | ||
130 | sirfsoc_memc_base = of_iomap(np, 0); | |
131 | if (!sirfsoc_memc_base) | |
132 | panic("unable to map memc registers\n"); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static struct platform_driver sirfsoc_memc_driver = { | |
138 | .probe = sirfsoc_memc_probe, | |
139 | .driver = { | |
140 | .name = "sirfsoc-memc", | |
141 | .owner = THIS_MODULE, | |
142 | .of_match_table = memc_ids, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static int __init sirfsoc_memc_init(void) | |
147 | { | |
148 | return platform_driver_register(&sirfsoc_memc_driver); | |
149 | } | |
150 | postcore_initcall(sirfsoc_memc_init); |