Commit | Line | Data |
---|---|---|
cf82e0e4 AB |
1 | config ARCH_SIRF |
2 | bool "CSR SiRF" if ARCH_MULTI_V7 | |
3 | select ARCH_REQUIRE_GPIOLIB | |
4 | select GENERIC_CLOCKEVENTS | |
5 | select GENERIC_IRQ_CHIP | |
6 | select MIGHT_HAVE_CACHE_L2X0 | |
7 | select NO_IOPORT | |
8 | select PINCTRL | |
9 | select PINCTRL_SIRF | |
10 | help | |
11 | Support for CSR SiRFprimaII/Marco/Polo platforms | |
12 | ||
156a0997 BS |
13 | if ARCH_SIRF |
14 | ||
d4fe49e5 BS |
15 | menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" |
16 | ||
17 | config ARCH_ATLAS6 | |
18 | bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" | |
19 | default y | |
20 | select CPU_V7 | |
21 | select SIRF_IRQ | |
22 | help | |
23 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
156a0997 BS |
24 | |
25 | config ARCH_PRIMA2 | |
26 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | |
27 | default y | |
28 | select CPU_V7 | |
c1e3c119 | 29 | select SIRF_IRQ |
b1b3f49c | 30 | select ZONE_DMA |
156a0997 BS |
31 | help |
32 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
33 | ||
4898de3d BS |
34 | config ARCH_MARCO |
35 | bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform" | |
36 | default y | |
37 | select ARM_GIC | |
38 | select CPU_V7 | |
4c3ffffd | 39 | select HAVE_ARM_SCU if SMP |
4898de3d | 40 | select HAVE_SMP |
cb0c480a | 41 | select SMP_ON_UP if SMP |
4898de3d BS |
42 | help |
43 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
44 | ||
156a0997 BS |
45 | endmenu |
46 | ||
c1e3c119 BS |
47 | config SIRF_IRQ |
48 | bool | |
49 | ||
156a0997 | 50 | endif |