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78818e47 VW |
1 | /* |
2 | * arch/arm/mach-pnx4008/time.c | |
3 | * | |
4 | * PNX4008 Timers | |
5 | * | |
6 | * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com> | |
7 | * | |
8 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | |
9 | * the terms of the GNU General Public License version 2. This program | |
10 | * is licensed "as is" without any warranty of any kind, whether express | |
11 | * or implied. | |
12 | */ | |
13 | ||
78818e47 VW |
14 | #include <linux/kernel.h> |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/kallsyms.h> | |
5904a7f9 VW |
22 | #include <linux/time.h> |
23 | #include <linux/timex.h> | |
24 | #include <linux/irq.h> | |
78818e47 VW |
25 | |
26 | #include <asm/system.h> | |
27 | #include <asm/hardware.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/leds.h> | |
78818e47 | 30 | #include <asm/mach/time.h> |
78818e47 VW |
31 | #include <asm/errno.h> |
32 | ||
33 | /*! Note: all timers are UPCOUNTING */ | |
34 | ||
35 | /*! | |
36 | * Returns number of us since last clock interrupt. Note that interrupts | |
37 | * will have been disabled by do_gettimeoffset() | |
38 | */ | |
39 | static unsigned long pnx4008_gettimeoffset(void) | |
40 | { | |
41 | u32 ticks_to_match = | |
42 | __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER); | |
43 | u32 elapsed = LATCH - ticks_to_match; | |
44 | return (elapsed * (tick_nsec / 1000)) / LATCH; | |
45 | } | |
46 | ||
47 | /*! | |
48 | * IRQ handler for the timer | |
49 | */ | |
50 | static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id, | |
51 | struct pt_regs *regs) | |
52 | { | |
53 | if (__raw_readl(HSTIM_INT) & MATCH0_INT) { | |
54 | ||
55 | write_seqlock(&xtime_lock); | |
56 | ||
57 | do { | |
58 | timer_tick(regs); | |
59 | ||
60 | /* | |
61 | * this algorithm takes care of possible delay | |
62 | * for this interrupt handling longer than a normal | |
63 | * timer period | |
64 | */ | |
65 | __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH, | |
66 | HSTIM_MATCH0); | |
67 | __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */ | |
68 | ||
69 | /* | |
70 | * The goal is to keep incrementing HSTIM_MATCH0 | |
71 | * register until HSTIM_MATCH0 indicates time after | |
72 | * what HSTIM_COUNTER indicates. | |
73 | */ | |
74 | } while ((signed) | |
75 | (__raw_readl(HSTIM_MATCH0) - | |
76 | __raw_readl(HSTIM_COUNTER)) < 0); | |
77 | ||
78 | write_sequnlock(&xtime_lock); | |
79 | } | |
80 | ||
81 | return IRQ_HANDLED; | |
82 | } | |
83 | ||
84 | static struct irqaction pnx4008_timer_irq = { | |
85 | .name = "PNX4008 Tick Timer", | |
52e405ea | 86 | .flags = IRQF_DISABLED | IRQF_TIMER, |
78818e47 VW |
87 | .handler = pnx4008_timer_interrupt |
88 | }; | |
89 | ||
90 | /*! | |
91 | * Set up timer and timer interrupt. | |
92 | */ | |
93 | static __init void pnx4008_setup_timer(void) | |
94 | { | |
95 | __raw_writel(RESET_COUNT, MSTIM_CTRL); | |
96 | while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */ | |
97 | __raw_writel(0, MSTIM_CTRL); /* stop the timer */ | |
98 | __raw_writel(0, MSTIM_MCTRL); | |
99 | ||
100 | __raw_writel(RESET_COUNT, HSTIM_CTRL); | |
101 | while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */ | |
102 | __raw_writel(0, HSTIM_CTRL); | |
103 | __raw_writel(0, HSTIM_MCTRL); | |
104 | __raw_writel(0, HSTIM_CCR); | |
105 | __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */ | |
106 | __raw_writel(LATCH, HSTIM_MATCH0); | |
107 | __raw_writel(MR0_INT, HSTIM_MCTRL); | |
108 | ||
109 | setup_irq(HSTIMER_INT, &pnx4008_timer_irq); | |
110 | ||
111 | __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */ | |
112 | } | |
113 | ||
114 | /* Timer Clock Control in PM register */ | |
115 | #define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC)) | |
116 | #define WATCHDOG_CLK_EN 1 | |
117 | #define TIMER_CLK_EN 2 /* HS and MS timers? */ | |
118 | ||
119 | static u32 timclk_ctrl_reg_save; | |
120 | ||
121 | void pnx4008_timer_suspend(void) | |
122 | { | |
123 | timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG); | |
124 | __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */ | |
125 | } | |
126 | ||
127 | void pnx4008_timer_resume(void) | |
128 | { | |
129 | __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */ | |
130 | } | |
131 | ||
132 | struct sys_timer pnx4008_timer = { | |
133 | .init = pnx4008_setup_timer, | |
134 | .offset = pnx4008_gettimeoffset, | |
135 | .suspend = pnx4008_timer_suspend, | |
136 | .resume = pnx4008_timer_resume, | |
137 | }; | |
138 |