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fdd8b079 NP |
1 | /* |
2 | * arch/arm/mach-orion5x/include/mach/bridge-regs.h | |
3 | * | |
4 | * Orion CPU Bridge Registers | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | |
12 | #define __ASM_ARCH_BRIDGE_REGS_H | |
13 | ||
14 | #include <mach/orion5x.h> | |
15 | ||
16 | #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) | |
17 | ||
18 | #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) | |
19 | ||
6462c616 TR |
20 | #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) |
21 | #define WDT_RESET_OUT_EN 0x0002 | |
fdd8b079 NP |
22 | |
23 | #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) | |
24 | ||
25 | #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) | |
26 | ||
27 | #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) | |
28 | #define WDT_INT_REQ 0x0008 | |
29 | ||
30 | #define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114) | |
31 | #define BRIDGE_INT_TIMER0 0x0002 | |
32 | #define BRIDGE_INT_TIMER1 0x0004 | |
33 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | |
34 | ||
35 | #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) | |
36 | ||
37 | #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) | |
38 | ||
39 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) | |
40 | ||
41 | #endif |