Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 | 15 | #include <linux/platform_device.h> |
ee962723 | 16 | #include <linux/dma-mapping.h> |
ca26f7d3 | 17 | #include <linux/serial_8250.h> |
144aa3db | 18 | #include <linux/mv643xx_i2c.h> |
15a32632 | 19 | #include <linux/ata_platform.h> |
764cbcc2 | 20 | #include <linux/delay.h> |
dcf1cece | 21 | #include <net/dsa.h> |
585cf175 | 22 | #include <asm/page.h> |
be73a347 | 23 | #include <asm/setup.h> |
c67de5b3 | 24 | #include <asm/timex.h> |
be73a347 | 25 | #include <asm/mach/arch.h> |
585cf175 | 26 | #include <asm/mach/map.h> |
2bac1de2 | 27 | #include <asm/mach/time.h> |
4ee1f6b5 | 28 | #include <mach/bridge-regs.h> |
a09e64fb RK |
29 | #include <mach/hardware.h> |
30 | #include <mach/orion5x.h> | |
6f088f1d LB |
31 | #include <plat/orion_nand.h> |
32 | #include <plat/time.h> | |
28a2b450 | 33 | #include <plat/common.h> |
45173d5e | 34 | #include <plat/addr-map.h> |
585cf175 TP |
35 | #include "common.h" |
36 | ||
37 | /***************************************************************************** | |
38 | * I/O Address Mapping | |
39 | ****************************************************************************/ | |
9dd0b194 | 40 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 41 | { |
9dd0b194 LB |
42 | .virtual = ORION5X_REGS_VIRT_BASE, |
43 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
44 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
45 | .type = MT_DEVICE, |
46 | }, { | |
9dd0b194 LB |
47 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
48 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
49 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
50 | .type = MT_DEVICE, |
51 | }, { | |
9dd0b194 LB |
52 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
53 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
54 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
55 | .type = MT_DEVICE, |
56 | }, { | |
9dd0b194 LB |
57 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
58 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
59 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 60 | .type = MT_DEVICE, |
585cf175 TP |
61 | }, |
62 | }; | |
63 | ||
9dd0b194 | 64 | void __init orion5x_map_io(void) |
585cf175 | 65 | { |
9dd0b194 | 66 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 67 | } |
c67de5b3 | 68 | |
044f6c7c | 69 | |
044f6c7c LB |
70 | /***************************************************************************** |
71 | * EHCI0 | |
72 | ****************************************************************************/ | |
044f6c7c LB |
73 | void __init orion5x_ehci0_init(void) |
74 | { | |
db33f4de | 75 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); |
044f6c7c LB |
76 | } |
77 | ||
78 | ||
79 | /***************************************************************************** | |
80 | * EHCI1 | |
81 | ****************************************************************************/ | |
044f6c7c LB |
82 | void __init orion5x_ehci1_init(void) |
83 | { | |
db33f4de | 84 | orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); |
044f6c7c LB |
85 | } |
86 | ||
87 | ||
e07c9d85 | 88 | /***************************************************************************** |
5c602551 | 89 | * GE00 |
e07c9d85 | 90 | ****************************************************************************/ |
9dd0b194 | 91 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 92 | { |
db33f4de | 93 | orion_ge00_init(eth_data, |
7e3819d8 AL |
94 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
95 | IRQ_ORION5X_ETH_ERR, orion5x_tclk); | |
e07c9d85 TP |
96 | } |
97 | ||
044f6c7c | 98 | |
dcf1cece LB |
99 | /***************************************************************************** |
100 | * Ethernet switch | |
101 | ****************************************************************************/ | |
dcf1cece LB |
102 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
103 | { | |
7e3819d8 | 104 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
105 | } |
106 | ||
107 | ||
144aa3db | 108 | /***************************************************************************** |
044f6c7c | 109 | * I2C |
144aa3db | 110 | ****************************************************************************/ |
044f6c7c LB |
111 | void __init orion5x_i2c_init(void) |
112 | { | |
aac7ffa3 AL |
113 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
114 | ||
044f6c7c LB |
115 | } |
116 | ||
117 | ||
f244baa3 | 118 | /***************************************************************************** |
044f6c7c | 119 | * SATA |
f244baa3 | 120 | ****************************************************************************/ |
9dd0b194 | 121 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 122 | { |
db33f4de | 123 | orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); |
f244baa3 SB |
124 | } |
125 | ||
044f6c7c | 126 | |
d323ade1 LB |
127 | /***************************************************************************** |
128 | * SPI | |
129 | ****************************************************************************/ | |
d323ade1 LB |
130 | void __init orion5x_spi_init() |
131 | { | |
980f9f60 | 132 | orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); |
d323ade1 LB |
133 | } |
134 | ||
135 | ||
2bac1de2 | 136 | /***************************************************************************** |
044f6c7c LB |
137 | * UART0 |
138 | ****************************************************************************/ | |
044f6c7c LB |
139 | void __init orion5x_uart0_init(void) |
140 | { | |
28a2b450 AL |
141 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
142 | IRQ_ORION5X_UART0, orion5x_tclk); | |
044f6c7c LB |
143 | } |
144 | ||
044f6c7c LB |
145 | /***************************************************************************** |
146 | * UART1 | |
2bac1de2 | 147 | ****************************************************************************/ |
044f6c7c LB |
148 | void __init orion5x_uart1_init(void) |
149 | { | |
28a2b450 AL |
150 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
151 | IRQ_ORION5X_UART1, orion5x_tclk); | |
044f6c7c | 152 | } |
2bac1de2 | 153 | |
1d5a1a6e SB |
154 | /***************************************************************************** |
155 | * XOR engine | |
156 | ****************************************************************************/ | |
1d5a1a6e SB |
157 | void __init orion5x_xor_init(void) |
158 | { | |
db33f4de | 159 | orion_xor0_init(ORION5X_XOR_PHYS_BASE, |
ee962723 AL |
160 | ORION5X_XOR_PHYS_BASE + 0x200, |
161 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | |
1d5a1a6e SB |
162 | } |
163 | ||
44350061 AL |
164 | /***************************************************************************** |
165 | * Cryptographic Engines and Security Accelerator (CESA) | |
166 | ****************************************************************************/ | |
167 | static void __init orion5x_crypto_init(void) | |
3a8f7441 | 168 | { |
b6d1c33a | 169 | orion5x_setup_sram_win(); |
44350061 AL |
170 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
171 | SZ_8K, IRQ_ORION5X_CESA); | |
3a8f7441 | 172 | } |
1d5a1a6e | 173 | |
9e058d4f TR |
174 | /***************************************************************************** |
175 | * Watchdog | |
176 | ****************************************************************************/ | |
9e058d4f TR |
177 | void __init orion5x_wdt_init(void) |
178 | { | |
5e00d378 | 179 | orion_wdt_init(orion5x_tclk); |
9e058d4f TR |
180 | } |
181 | ||
182 | ||
044f6c7c LB |
183 | /***************************************************************************** |
184 | * Time handling | |
185 | ****************************************************************************/ | |
4ee1f6b5 LB |
186 | void __init orion5x_init_early(void) |
187 | { | |
188 | orion_time_set_base(TIMER_VIRT_BASE); | |
189 | } | |
190 | ||
ebe35aff LB |
191 | int orion5x_tclk; |
192 | ||
193 | int __init orion5x_find_tclk(void) | |
194 | { | |
d323ade1 LB |
195 | u32 dev, rev; |
196 | ||
197 | orion5x_pcie_id(&dev, &rev); | |
198 | if (dev == MV88F6183_DEV_ID && | |
199 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
200 | return 133333333; | |
201 | ||
ebe35aff LB |
202 | return 166666667; |
203 | } | |
204 | ||
9dd0b194 | 205 | static void orion5x_timer_init(void) |
2bac1de2 | 206 | { |
ebe35aff | 207 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
208 | |
209 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
210 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
211 | } |
212 | ||
9dd0b194 | 213 | struct sys_timer orion5x_timer = { |
e7068ad3 | 214 | .init = orion5x_timer_init, |
2bac1de2 LB |
215 | }; |
216 | ||
044f6c7c | 217 | |
c67de5b3 TP |
218 | /***************************************************************************** |
219 | * General | |
220 | ****************************************************************************/ | |
c67de5b3 | 221 | /* |
b46926bb | 222 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 223 | */ |
9dd0b194 | 224 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 225 | { |
9dd0b194 | 226 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
227 | |
228 | if (*dev == MV88F5281_DEV_ID) { | |
229 | if (*rev == MV88F5281_REV_D2) { | |
230 | *dev_name = "MV88F5281-D2"; | |
231 | } else if (*rev == MV88F5281_REV_D1) { | |
232 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
233 | } else if (*rev == MV88F5281_REV_D0) { |
234 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
235 | } else { |
236 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
237 | } | |
238 | } else if (*dev == MV88F5182_DEV_ID) { | |
239 | if (*rev == MV88F5182_REV_A2) { | |
240 | *dev_name = "MV88F5182-A2"; | |
241 | } else { | |
242 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
243 | } | |
c9e3de94 HVR |
244 | } else if (*dev == MV88F5181_DEV_ID) { |
245 | if (*rev == MV88F5181_REV_B1) { | |
246 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
247 | } else if (*rev == MV88F5181L_REV_A1) { |
248 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 249 | } else { |
d2b2a6bb | 250 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 251 | } |
d323ade1 LB |
252 | } else if (*dev == MV88F6183_DEV_ID) { |
253 | if (*rev == MV88F6183_REV_B0) { | |
254 | *dev_name = "MV88F6183-Rev-B0"; | |
255 | } else { | |
256 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
257 | } | |
c67de5b3 TP |
258 | } else { |
259 | *dev_name = "Device-Unknown"; | |
260 | } | |
261 | } | |
262 | ||
9dd0b194 | 263 | void __init orion5x_init(void) |
c67de5b3 TP |
264 | { |
265 | char *dev_name; | |
266 | u32 dev, rev; | |
267 | ||
9dd0b194 | 268 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
269 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
270 | ||
c67de5b3 TP |
271 | /* |
272 | * Setup Orion address map | |
273 | */ | |
9dd0b194 | 274 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e LB |
275 | |
276 | /* | |
277 | * Don't issue "Wait for Interrupt" instruction if we are | |
278 | * running on D0 5281 silicon. | |
279 | */ | |
280 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
281 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
282 | disable_hlt(); | |
283 | } | |
9e058d4f | 284 | |
3fade49b NP |
285 | /* |
286 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
287 | * while 5180n/5181/5281 don't have crypto. | |
288 | */ | |
289 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
290 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
291 | orion5x_crypto_init(); | |
292 | ||
9e058d4f TR |
293 | /* |
294 | * Register watchdog driver | |
295 | */ | |
296 | orion5x_wdt_init(); | |
c67de5b3 | 297 | } |
be73a347 | 298 | |
764cbcc2 RK |
299 | void orion5x_restart(char mode, const char *cmd) |
300 | { | |
301 | /* | |
302 | * Enable and issue soft reset | |
303 | */ | |
304 | orion5x_setbits(RSTOUTn_MASK, (1 << 2)); | |
305 | orion5x_setbits(CPU_SOFT_RESET, 1); | |
306 | mdelay(200); | |
307 | orion5x_clrbits(CPU_SOFT_RESET, 1); | |
308 | } | |
309 | ||
be73a347 GL |
310 | /* |
311 | * Many orion-based systems have buggy bootloader implementations. | |
312 | * This is a common fixup for bogus memory tags. | |
313 | */ | |
0744a3ee RK |
314 | void __init tag_fixup_mem32(struct tag *t, char **from, |
315 | struct meminfo *meminfo) | |
be73a347 GL |
316 | { |
317 | for (; t->hdr.size; t = tag_next(t)) | |
318 | if (t->hdr.tag == ATAG_MEM && | |
319 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
320 | t->u.mem.start & ~PAGE_MASK)) { | |
321 | printk(KERN_WARNING | |
322 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
323 | t->u.mem.size / 1024, t->u.mem.start); | |
324 | t->hdr.tag = 0; | |
325 | } | |
326 | } |