Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 TP |
15 | #include <linux/platform_device.h> |
16 | #include <linux/serial_8250.h> | |
83b6d822 | 17 | #include <linux/mbus.h> |
e07c9d85 | 18 | #include <linux/mv643xx_eth.h> |
144aa3db | 19 | #include <linux/mv643xx_i2c.h> |
15a32632 | 20 | #include <linux/ata_platform.h> |
d323ade1 | 21 | #include <linux/spi/orion_spi.h> |
dcf1cece | 22 | #include <net/dsa.h> |
585cf175 | 23 | #include <asm/page.h> |
be73a347 | 24 | #include <asm/setup.h> |
c67de5b3 | 25 | #include <asm/timex.h> |
be73a347 | 26 | #include <asm/mach/arch.h> |
585cf175 | 27 | #include <asm/mach/map.h> |
2bac1de2 | 28 | #include <asm/mach/time.h> |
a09e64fb RK |
29 | #include <mach/hardware.h> |
30 | #include <mach/orion5x.h> | |
6f088f1d | 31 | #include <plat/ehci-orion.h> |
1d5a1a6e | 32 | #include <plat/mv_xor.h> |
6f088f1d | 33 | #include <plat/orion_nand.h> |
3b937a7d | 34 | #include <plat/orion_wdt.h> |
6f088f1d | 35 | #include <plat/time.h> |
585cf175 TP |
36 | #include "common.h" |
37 | ||
38 | /***************************************************************************** | |
39 | * I/O Address Mapping | |
40 | ****************************************************************************/ | |
9dd0b194 | 41 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 42 | { |
9dd0b194 LB |
43 | .virtual = ORION5X_REGS_VIRT_BASE, |
44 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
45 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
46 | .type = MT_DEVICE, |
47 | }, { | |
9dd0b194 LB |
48 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
49 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
50 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
51 | .type = MT_DEVICE, |
52 | }, { | |
9dd0b194 LB |
53 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
54 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
55 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
56 | .type = MT_DEVICE, |
57 | }, { | |
9dd0b194 LB |
58 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
59 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
60 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 61 | .type = MT_DEVICE, |
585cf175 TP |
62 | }, |
63 | }; | |
64 | ||
9dd0b194 | 65 | void __init orion5x_map_io(void) |
585cf175 | 66 | { |
9dd0b194 | 67 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 68 | } |
c67de5b3 | 69 | |
044f6c7c | 70 | |
ca26f7d3 | 71 | /***************************************************************************** |
044f6c7c | 72 | * EHCI |
ca26f7d3 | 73 | ****************************************************************************/ |
044f6c7c LB |
74 | static struct orion_ehci_data orion5x_ehci_data = { |
75 | .dram = &orion5x_mbus_dram_info, | |
fb6f5529 | 76 | .phy_version = EHCI_PHY_ORION, |
ca26f7d3 TP |
77 | }; |
78 | ||
044f6c7c | 79 | static u64 ehci_dmamask = 0xffffffffUL; |
ca26f7d3 | 80 | |
ca26f7d3 | 81 | |
044f6c7c LB |
82 | /***************************************************************************** |
83 | * EHCI0 | |
84 | ****************************************************************************/ | |
9dd0b194 | 85 | static struct resource orion5x_ehci0_resources[] = { |
ca26f7d3 | 86 | { |
9dd0b194 | 87 | .start = ORION5X_USB0_PHYS_BASE, |
994cab84 | 88 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, |
ca26f7d3 | 89 | .flags = IORESOURCE_MEM, |
e7068ad3 | 90 | }, { |
9dd0b194 LB |
91 | .start = IRQ_ORION5X_USB0_CTRL, |
92 | .end = IRQ_ORION5X_USB0_CTRL, | |
ca26f7d3 TP |
93 | .flags = IORESOURCE_IRQ, |
94 | }, | |
95 | }; | |
96 | ||
9dd0b194 | 97 | static struct platform_device orion5x_ehci0 = { |
ca26f7d3 TP |
98 | .name = "orion-ehci", |
99 | .id = 0, | |
100 | .dev = { | |
101 | .dma_mask = &ehci_dmamask, | |
102 | .coherent_dma_mask = 0xffffffff, | |
9dd0b194 | 103 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 104 | }, |
9dd0b194 LB |
105 | .resource = orion5x_ehci0_resources, |
106 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), | |
ca26f7d3 TP |
107 | }; |
108 | ||
044f6c7c LB |
109 | void __init orion5x_ehci0_init(void) |
110 | { | |
111 | platform_device_register(&orion5x_ehci0); | |
112 | } | |
113 | ||
114 | ||
115 | /***************************************************************************** | |
116 | * EHCI1 | |
117 | ****************************************************************************/ | |
118 | static struct resource orion5x_ehci1_resources[] = { | |
119 | { | |
120 | .start = ORION5X_USB1_PHYS_BASE, | |
121 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, | |
122 | .flags = IORESOURCE_MEM, | |
123 | }, { | |
124 | .start = IRQ_ORION5X_USB1_CTRL, | |
125 | .end = IRQ_ORION5X_USB1_CTRL, | |
126 | .flags = IORESOURCE_IRQ, | |
127 | }, | |
128 | }; | |
129 | ||
9dd0b194 | 130 | static struct platform_device orion5x_ehci1 = { |
ca26f7d3 TP |
131 | .name = "orion-ehci", |
132 | .id = 1, | |
133 | .dev = { | |
134 | .dma_mask = &ehci_dmamask, | |
135 | .coherent_dma_mask = 0xffffffff, | |
9dd0b194 | 136 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 137 | }, |
9dd0b194 LB |
138 | .resource = orion5x_ehci1_resources, |
139 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), | |
ca26f7d3 TP |
140 | }; |
141 | ||
044f6c7c LB |
142 | void __init orion5x_ehci1_init(void) |
143 | { | |
144 | platform_device_register(&orion5x_ehci1); | |
145 | } | |
146 | ||
147 | ||
e07c9d85 | 148 | /***************************************************************************** |
044f6c7c | 149 | * GigE |
e07c9d85 | 150 | ****************************************************************************/ |
d236f5a5 LB |
151 | struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { |
152 | .dram = &orion5x_mbus_dram_info, | |
153 | }; | |
154 | ||
9dd0b194 | 155 | static struct resource orion5x_eth_shared_resources[] = { |
e07c9d85 | 156 | { |
9dd0b194 LB |
157 | .start = ORION5X_ETH_PHYS_BASE + 0x2000, |
158 | .end = ORION5X_ETH_PHYS_BASE + 0x3fff, | |
e07c9d85 | 159 | .flags = IORESOURCE_MEM, |
eeff6d86 LB |
160 | }, { |
161 | .start = IRQ_ORION5X_ETH_ERR, | |
162 | .end = IRQ_ORION5X_ETH_ERR, | |
163 | .flags = IORESOURCE_IRQ, | |
e07c9d85 TP |
164 | }, |
165 | }; | |
166 | ||
9dd0b194 | 167 | static struct platform_device orion5x_eth_shared = { |
e07c9d85 TP |
168 | .name = MV643XX_ETH_SHARED_NAME, |
169 | .id = 0, | |
d236f5a5 LB |
170 | .dev = { |
171 | .platform_data = &orion5x_eth_shared_data, | |
172 | }, | |
eeff6d86 | 173 | .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources), |
9dd0b194 | 174 | .resource = orion5x_eth_shared_resources, |
e07c9d85 TP |
175 | }; |
176 | ||
9dd0b194 | 177 | static struct resource orion5x_eth_resources[] = { |
e07c9d85 TP |
178 | { |
179 | .name = "eth irq", | |
9dd0b194 LB |
180 | .start = IRQ_ORION5X_ETH_SUM, |
181 | .end = IRQ_ORION5X_ETH_SUM, | |
e07c9d85 | 182 | .flags = IORESOURCE_IRQ, |
e7068ad3 | 183 | }, |
e07c9d85 TP |
184 | }; |
185 | ||
9dd0b194 | 186 | static struct platform_device orion5x_eth = { |
e07c9d85 TP |
187 | .name = MV643XX_ETH_NAME, |
188 | .id = 0, | |
189 | .num_resources = 1, | |
9dd0b194 | 190 | .resource = orion5x_eth_resources, |
a49a018a NP |
191 | .dev = { |
192 | .coherent_dma_mask = 0xffffffff, | |
193 | }, | |
e07c9d85 TP |
194 | }; |
195 | ||
9dd0b194 | 196 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 197 | { |
fa3959f4 | 198 | eth_data->shared = &orion5x_eth_shared; |
9dd0b194 | 199 | orion5x_eth.dev.platform_data = eth_data; |
fa3959f4 | 200 | |
9dd0b194 LB |
201 | platform_device_register(&orion5x_eth_shared); |
202 | platform_device_register(&orion5x_eth); | |
e07c9d85 TP |
203 | } |
204 | ||
044f6c7c | 205 | |
dcf1cece LB |
206 | /***************************************************************************** |
207 | * Ethernet switch | |
208 | ****************************************************************************/ | |
209 | static struct resource orion5x_switch_resources[] = { | |
210 | { | |
211 | .start = 0, | |
212 | .end = 0, | |
213 | .flags = IORESOURCE_IRQ, | |
214 | }, | |
215 | }; | |
216 | ||
217 | static struct platform_device orion5x_switch_device = { | |
218 | .name = "dsa", | |
219 | .id = 0, | |
220 | .num_resources = 0, | |
221 | .resource = orion5x_switch_resources, | |
222 | }; | |
223 | ||
224 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) | |
225 | { | |
e84665c9 LB |
226 | int i; |
227 | ||
dcf1cece LB |
228 | if (irq != NO_IRQ) { |
229 | orion5x_switch_resources[0].start = irq; | |
230 | orion5x_switch_resources[0].end = irq; | |
231 | orion5x_switch_device.num_resources = 1; | |
232 | } | |
233 | ||
dcf1cece | 234 | d->netdev = &orion5x_eth.dev; |
e84665c9 LB |
235 | for (i = 0; i < d->nr_chips; i++) |
236 | d->chip[i].mii_bus = &orion5x_eth_shared.dev; | |
dcf1cece LB |
237 | orion5x_switch_device.dev.platform_data = d; |
238 | ||
239 | platform_device_register(&orion5x_switch_device); | |
240 | } | |
241 | ||
242 | ||
144aa3db | 243 | /***************************************************************************** |
044f6c7c | 244 | * I2C |
144aa3db | 245 | ****************************************************************************/ |
9dd0b194 | 246 | static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { |
144aa3db HVR |
247 | .freq_m = 8, /* assumes 166 MHz TCLK */ |
248 | .freq_n = 3, | |
249 | .timeout = 1000, /* Default timeout of 1 second */ | |
250 | }; | |
251 | ||
9dd0b194 | 252 | static struct resource orion5x_i2c_resources[] = { |
144aa3db | 253 | { |
e7068ad3 | 254 | .start = I2C_PHYS_BASE, |
044f6c7c | 255 | .end = I2C_PHYS_BASE + 0x1f, |
e7068ad3 LB |
256 | .flags = IORESOURCE_MEM, |
257 | }, { | |
e7068ad3 LB |
258 | .start = IRQ_ORION5X_I2C, |
259 | .end = IRQ_ORION5X_I2C, | |
260 | .flags = IORESOURCE_IRQ, | |
144aa3db HVR |
261 | }, |
262 | }; | |
263 | ||
9dd0b194 | 264 | static struct platform_device orion5x_i2c = { |
144aa3db HVR |
265 | .name = MV64XXX_I2C_CTLR_NAME, |
266 | .id = 0, | |
9dd0b194 LB |
267 | .num_resources = ARRAY_SIZE(orion5x_i2c_resources), |
268 | .resource = orion5x_i2c_resources, | |
144aa3db | 269 | .dev = { |
e7068ad3 | 270 | .platform_data = &orion5x_i2c_pdata, |
144aa3db HVR |
271 | }, |
272 | }; | |
273 | ||
044f6c7c LB |
274 | void __init orion5x_i2c_init(void) |
275 | { | |
276 | platform_device_register(&orion5x_i2c); | |
277 | } | |
278 | ||
279 | ||
f244baa3 | 280 | /***************************************************************************** |
044f6c7c | 281 | * SATA |
f244baa3 | 282 | ****************************************************************************/ |
9dd0b194 | 283 | static struct resource orion5x_sata_resources[] = { |
f244baa3 | 284 | { |
e7068ad3 LB |
285 | .name = "sata base", |
286 | .start = ORION5X_SATA_PHYS_BASE, | |
287 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, | |
288 | .flags = IORESOURCE_MEM, | |
289 | }, { | |
290 | .name = "sata irq", | |
291 | .start = IRQ_ORION5X_SATA, | |
292 | .end = IRQ_ORION5X_SATA, | |
293 | .flags = IORESOURCE_IRQ, | |
294 | }, | |
f244baa3 SB |
295 | }; |
296 | ||
9dd0b194 | 297 | static struct platform_device orion5x_sata = { |
e7068ad3 LB |
298 | .name = "sata_mv", |
299 | .id = 0, | |
f244baa3 SB |
300 | .dev = { |
301 | .coherent_dma_mask = 0xffffffff, | |
302 | }, | |
e7068ad3 LB |
303 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
304 | .resource = orion5x_sata_resources, | |
f244baa3 SB |
305 | }; |
306 | ||
9dd0b194 | 307 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 308 | { |
9dd0b194 LB |
309 | sata_data->dram = &orion5x_mbus_dram_info; |
310 | orion5x_sata.dev.platform_data = sata_data; | |
311 | platform_device_register(&orion5x_sata); | |
f244baa3 SB |
312 | } |
313 | ||
044f6c7c | 314 | |
d323ade1 LB |
315 | /***************************************************************************** |
316 | * SPI | |
317 | ****************************************************************************/ | |
318 | static struct orion_spi_info orion5x_spi_plat_data = { | |
c0e19363 NP |
319 | .tclk = 0, |
320 | .enable_clock_fix = 1, | |
d323ade1 LB |
321 | }; |
322 | ||
323 | static struct resource orion5x_spi_resources[] = { | |
324 | { | |
325 | .name = "spi base", | |
326 | .start = SPI_PHYS_BASE, | |
327 | .end = SPI_PHYS_BASE + 0x1f, | |
328 | .flags = IORESOURCE_MEM, | |
329 | }, | |
330 | }; | |
331 | ||
332 | static struct platform_device orion5x_spi = { | |
333 | .name = "orion_spi", | |
334 | .id = 0, | |
335 | .dev = { | |
336 | .platform_data = &orion5x_spi_plat_data, | |
337 | }, | |
338 | .num_resources = ARRAY_SIZE(orion5x_spi_resources), | |
339 | .resource = orion5x_spi_resources, | |
340 | }; | |
341 | ||
342 | void __init orion5x_spi_init() | |
343 | { | |
344 | platform_device_register(&orion5x_spi); | |
345 | } | |
346 | ||
347 | ||
2bac1de2 | 348 | /***************************************************************************** |
044f6c7c LB |
349 | * UART0 |
350 | ****************************************************************************/ | |
351 | static struct plat_serial8250_port orion5x_uart0_data[] = { | |
352 | { | |
353 | .mapbase = UART0_PHYS_BASE, | |
354 | .membase = (char *)UART0_VIRT_BASE, | |
355 | .irq = IRQ_ORION5X_UART0, | |
356 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | |
357 | .iotype = UPIO_MEM, | |
358 | .regshift = 2, | |
ebe35aff | 359 | .uartclk = 0, |
044f6c7c LB |
360 | }, { |
361 | }, | |
362 | }; | |
363 | ||
364 | static struct resource orion5x_uart0_resources[] = { | |
365 | { | |
366 | .start = UART0_PHYS_BASE, | |
367 | .end = UART0_PHYS_BASE + 0xff, | |
368 | .flags = IORESOURCE_MEM, | |
369 | }, { | |
370 | .start = IRQ_ORION5X_UART0, | |
371 | .end = IRQ_ORION5X_UART0, | |
372 | .flags = IORESOURCE_IRQ, | |
373 | }, | |
374 | }; | |
375 | ||
376 | static struct platform_device orion5x_uart0 = { | |
377 | .name = "serial8250", | |
378 | .id = PLAT8250_DEV_PLATFORM, | |
379 | .dev = { | |
380 | .platform_data = orion5x_uart0_data, | |
381 | }, | |
382 | .resource = orion5x_uart0_resources, | |
383 | .num_resources = ARRAY_SIZE(orion5x_uart0_resources), | |
384 | }; | |
385 | ||
386 | void __init orion5x_uart0_init(void) | |
387 | { | |
388 | platform_device_register(&orion5x_uart0); | |
389 | } | |
390 | ||
391 | ||
392 | /***************************************************************************** | |
393 | * UART1 | |
2bac1de2 | 394 | ****************************************************************************/ |
044f6c7c LB |
395 | static struct plat_serial8250_port orion5x_uart1_data[] = { |
396 | { | |
397 | .mapbase = UART1_PHYS_BASE, | |
398 | .membase = (char *)UART1_VIRT_BASE, | |
399 | .irq = IRQ_ORION5X_UART1, | |
400 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | |
401 | .iotype = UPIO_MEM, | |
402 | .regshift = 2, | |
ebe35aff | 403 | .uartclk = 0, |
044f6c7c LB |
404 | }, { |
405 | }, | |
406 | }; | |
407 | ||
408 | static struct resource orion5x_uart1_resources[] = { | |
409 | { | |
410 | .start = UART1_PHYS_BASE, | |
411 | .end = UART1_PHYS_BASE + 0xff, | |
412 | .flags = IORESOURCE_MEM, | |
413 | }, { | |
414 | .start = IRQ_ORION5X_UART1, | |
415 | .end = IRQ_ORION5X_UART1, | |
416 | .flags = IORESOURCE_IRQ, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static struct platform_device orion5x_uart1 = { | |
421 | .name = "serial8250", | |
422 | .id = PLAT8250_DEV_PLATFORM1, | |
423 | .dev = { | |
424 | .platform_data = orion5x_uart1_data, | |
425 | }, | |
426 | .resource = orion5x_uart1_resources, | |
427 | .num_resources = ARRAY_SIZE(orion5x_uart1_resources), | |
428 | }; | |
429 | ||
430 | void __init orion5x_uart1_init(void) | |
431 | { | |
432 | platform_device_register(&orion5x_uart1); | |
433 | } | |
2bac1de2 | 434 | |
044f6c7c | 435 | |
1d5a1a6e SB |
436 | /***************************************************************************** |
437 | * XOR engine | |
438 | ****************************************************************************/ | |
f45964ed SB |
439 | struct mv_xor_platform_shared_data orion5x_xor_shared_data = { |
440 | .dram = &orion5x_mbus_dram_info, | |
441 | }; | |
442 | ||
1d5a1a6e SB |
443 | static struct resource orion5x_xor_shared_resources[] = { |
444 | { | |
445 | .name = "xor low", | |
446 | .start = ORION5X_XOR_PHYS_BASE, | |
447 | .end = ORION5X_XOR_PHYS_BASE + 0xff, | |
448 | .flags = IORESOURCE_MEM, | |
449 | }, { | |
450 | .name = "xor high", | |
451 | .start = ORION5X_XOR_PHYS_BASE + 0x200, | |
452 | .end = ORION5X_XOR_PHYS_BASE + 0x2ff, | |
453 | .flags = IORESOURCE_MEM, | |
454 | }, | |
455 | }; | |
456 | ||
457 | static struct platform_device orion5x_xor_shared = { | |
458 | .name = MV_XOR_SHARED_NAME, | |
459 | .id = 0, | |
f45964ed SB |
460 | .dev = { |
461 | .platform_data = &orion5x_xor_shared_data, | |
462 | }, | |
1d5a1a6e SB |
463 | .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), |
464 | .resource = orion5x_xor_shared_resources, | |
465 | }; | |
466 | ||
284901a9 | 467 | static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32); |
1d5a1a6e SB |
468 | |
469 | static struct resource orion5x_xor0_resources[] = { | |
470 | [0] = { | |
471 | .start = IRQ_ORION5X_XOR0, | |
472 | .end = IRQ_ORION5X_XOR0, | |
473 | .flags = IORESOURCE_IRQ, | |
474 | }, | |
475 | }; | |
476 | ||
477 | static struct mv_xor_platform_data orion5x_xor0_data = { | |
478 | .shared = &orion5x_xor_shared, | |
479 | .hw_id = 0, | |
480 | .pool_size = PAGE_SIZE, | |
481 | }; | |
482 | ||
483 | static struct platform_device orion5x_xor0_channel = { | |
484 | .name = MV_XOR_NAME, | |
485 | .id = 0, | |
486 | .num_resources = ARRAY_SIZE(orion5x_xor0_resources), | |
487 | .resource = orion5x_xor0_resources, | |
488 | .dev = { | |
489 | .dma_mask = &orion5x_xor_dmamask, | |
6a35528a | 490 | .coherent_dma_mask = DMA_BIT_MASK(64), |
1d5a1a6e SB |
491 | .platform_data = (void *)&orion5x_xor0_data, |
492 | }, | |
493 | }; | |
494 | ||
495 | static struct resource orion5x_xor1_resources[] = { | |
496 | [0] = { | |
497 | .start = IRQ_ORION5X_XOR1, | |
498 | .end = IRQ_ORION5X_XOR1, | |
499 | .flags = IORESOURCE_IRQ, | |
500 | }, | |
501 | }; | |
502 | ||
503 | static struct mv_xor_platform_data orion5x_xor1_data = { | |
504 | .shared = &orion5x_xor_shared, | |
505 | .hw_id = 1, | |
506 | .pool_size = PAGE_SIZE, | |
507 | }; | |
508 | ||
509 | static struct platform_device orion5x_xor1_channel = { | |
510 | .name = MV_XOR_NAME, | |
511 | .id = 1, | |
512 | .num_resources = ARRAY_SIZE(orion5x_xor1_resources), | |
513 | .resource = orion5x_xor1_resources, | |
514 | .dev = { | |
515 | .dma_mask = &orion5x_xor_dmamask, | |
6a35528a | 516 | .coherent_dma_mask = DMA_BIT_MASK(64), |
1d5a1a6e SB |
517 | .platform_data = (void *)&orion5x_xor1_data, |
518 | }, | |
519 | }; | |
520 | ||
521 | void __init orion5x_xor_init(void) | |
522 | { | |
523 | platform_device_register(&orion5x_xor_shared); | |
524 | ||
525 | /* | |
526 | * two engines can't do memset simultaneously, this limitation | |
527 | * satisfied by removing memset support from one of the engines. | |
528 | */ | |
529 | dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask); | |
530 | dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask); | |
531 | platform_device_register(&orion5x_xor0_channel); | |
532 | ||
533 | dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask); | |
534 | dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask); | |
535 | dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask); | |
536 | platform_device_register(&orion5x_xor1_channel); | |
537 | } | |
538 | ||
3a8f7441 SAS |
539 | static struct resource orion5x_crypto_res[] = { |
540 | { | |
541 | .name = "regs", | |
542 | .start = ORION5X_CRYPTO_PHYS_BASE, | |
543 | .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, | |
544 | .flags = IORESOURCE_MEM, | |
545 | }, { | |
546 | .name = "sram", | |
547 | .start = ORION5X_SRAM_PHYS_BASE, | |
548 | .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, | |
549 | .flags = IORESOURCE_MEM, | |
550 | }, { | |
551 | .name = "crypto interrupt", | |
552 | .start = IRQ_ORION5X_CESA, | |
553 | .end = IRQ_ORION5X_CESA, | |
554 | .flags = IORESOURCE_IRQ, | |
555 | }, | |
556 | }; | |
557 | ||
558 | static struct platform_device orion5x_crypto_device = { | |
559 | .name = "mv_crypto", | |
560 | .id = -1, | |
561 | .num_resources = ARRAY_SIZE(orion5x_crypto_res), | |
562 | .resource = orion5x_crypto_res, | |
563 | }; | |
564 | ||
565 | int __init orion5x_crypto_init(void) | |
566 | { | |
567 | int ret; | |
568 | ||
569 | ret = orion5x_setup_sram_win(); | |
570 | if (ret) | |
571 | return ret; | |
572 | ||
573 | return platform_device_register(&orion5x_crypto_device); | |
574 | } | |
1d5a1a6e | 575 | |
9e058d4f TR |
576 | /***************************************************************************** |
577 | * Watchdog | |
578 | ****************************************************************************/ | |
3b937a7d | 579 | static struct orion_wdt_platform_data orion5x_wdt_data = { |
9e058d4f TR |
580 | .tclk = 0, |
581 | }; | |
582 | ||
583 | static struct platform_device orion5x_wdt_device = { | |
3b937a7d | 584 | .name = "orion_wdt", |
9e058d4f TR |
585 | .id = -1, |
586 | .dev = { | |
587 | .platform_data = &orion5x_wdt_data, | |
588 | }, | |
589 | .num_resources = 0, | |
590 | }; | |
591 | ||
592 | void __init orion5x_wdt_init(void) | |
593 | { | |
594 | orion5x_wdt_data.tclk = orion5x_tclk; | |
595 | platform_device_register(&orion5x_wdt_device); | |
596 | } | |
597 | ||
598 | ||
044f6c7c LB |
599 | /***************************************************************************** |
600 | * Time handling | |
601 | ****************************************************************************/ | |
ebe35aff LB |
602 | int orion5x_tclk; |
603 | ||
604 | int __init orion5x_find_tclk(void) | |
605 | { | |
d323ade1 LB |
606 | u32 dev, rev; |
607 | ||
608 | orion5x_pcie_id(&dev, &rev); | |
609 | if (dev == MV88F6183_DEV_ID && | |
610 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
611 | return 133333333; | |
612 | ||
ebe35aff LB |
613 | return 166666667; |
614 | } | |
615 | ||
9dd0b194 | 616 | static void orion5x_timer_init(void) |
2bac1de2 | 617 | { |
ebe35aff LB |
618 | orion5x_tclk = orion5x_find_tclk(); |
619 | orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
620 | } |
621 | ||
9dd0b194 | 622 | struct sys_timer orion5x_timer = { |
e7068ad3 | 623 | .init = orion5x_timer_init, |
2bac1de2 LB |
624 | }; |
625 | ||
044f6c7c | 626 | |
c67de5b3 TP |
627 | /***************************************************************************** |
628 | * General | |
629 | ****************************************************************************/ | |
c67de5b3 | 630 | /* |
b46926bb | 631 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 632 | */ |
9dd0b194 | 633 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 634 | { |
9dd0b194 | 635 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
636 | |
637 | if (*dev == MV88F5281_DEV_ID) { | |
638 | if (*rev == MV88F5281_REV_D2) { | |
639 | *dev_name = "MV88F5281-D2"; | |
640 | } else if (*rev == MV88F5281_REV_D1) { | |
641 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
642 | } else if (*rev == MV88F5281_REV_D0) { |
643 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
644 | } else { |
645 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
646 | } | |
647 | } else if (*dev == MV88F5182_DEV_ID) { | |
648 | if (*rev == MV88F5182_REV_A2) { | |
649 | *dev_name = "MV88F5182-A2"; | |
650 | } else { | |
651 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
652 | } | |
c9e3de94 HVR |
653 | } else if (*dev == MV88F5181_DEV_ID) { |
654 | if (*rev == MV88F5181_REV_B1) { | |
655 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
656 | } else if (*rev == MV88F5181L_REV_A1) { |
657 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 658 | } else { |
d2b2a6bb | 659 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 660 | } |
d323ade1 LB |
661 | } else if (*dev == MV88F6183_DEV_ID) { |
662 | if (*rev == MV88F6183_REV_B0) { | |
663 | *dev_name = "MV88F6183-Rev-B0"; | |
664 | } else { | |
665 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
666 | } | |
c67de5b3 TP |
667 | } else { |
668 | *dev_name = "Device-Unknown"; | |
669 | } | |
670 | } | |
671 | ||
9dd0b194 | 672 | void __init orion5x_init(void) |
c67de5b3 TP |
673 | { |
674 | char *dev_name; | |
675 | u32 dev, rev; | |
676 | ||
9dd0b194 | 677 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
678 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
679 | ||
680 | orion5x_eth_shared_data.t_clk = orion5x_tclk; | |
d323ade1 | 681 | orion5x_spi_plat_data.tclk = orion5x_tclk; |
ebe35aff LB |
682 | orion5x_uart0_data[0].uartclk = orion5x_tclk; |
683 | orion5x_uart1_data[0].uartclk = orion5x_tclk; | |
c67de5b3 TP |
684 | |
685 | /* | |
686 | * Setup Orion address map | |
687 | */ | |
9dd0b194 | 688 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e LB |
689 | |
690 | /* | |
691 | * Don't issue "Wait for Interrupt" instruction if we are | |
692 | * running on D0 5281 silicon. | |
693 | */ | |
694 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
695 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
696 | disable_hlt(); | |
697 | } | |
9e058d4f TR |
698 | |
699 | /* | |
700 | * Register watchdog driver | |
701 | */ | |
702 | orion5x_wdt_init(); | |
c67de5b3 | 703 | } |
be73a347 GL |
704 | |
705 | /* | |
706 | * Many orion-based systems have buggy bootloader implementations. | |
707 | * This is a common fixup for bogus memory tags. | |
708 | */ | |
709 | void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, | |
710 | char **from, struct meminfo *meminfo) | |
711 | { | |
712 | for (; t->hdr.size; t = tag_next(t)) | |
713 | if (t->hdr.tag == ATAG_MEM && | |
714 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
715 | t->u.mem.start & ~PAGE_MASK)) { | |
716 | printk(KERN_WARNING | |
717 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
718 | t->u.mem.size / 1024, t->u.mem.start); | |
719 | t->hdr.tag = 0; | |
720 | } | |
721 | } |