Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 | 15 | #include <linux/platform_device.h> |
ee962723 | 16 | #include <linux/dma-mapping.h> |
ca26f7d3 | 17 | #include <linux/serial_8250.h> |
144aa3db | 18 | #include <linux/mv643xx_i2c.h> |
15a32632 | 19 | #include <linux/ata_platform.h> |
764cbcc2 | 20 | #include <linux/delay.h> |
2f129bf4 | 21 | #include <linux/clk-provider.h> |
dcf1cece | 22 | #include <net/dsa.h> |
585cf175 | 23 | #include <asm/page.h> |
be73a347 | 24 | #include <asm/setup.h> |
9f97da78 | 25 | #include <asm/system_misc.h> |
c67de5b3 | 26 | #include <asm/timex.h> |
be73a347 | 27 | #include <asm/mach/arch.h> |
585cf175 | 28 | #include <asm/mach/map.h> |
2bac1de2 | 29 | #include <asm/mach/time.h> |
4ee1f6b5 | 30 | #include <mach/bridge-regs.h> |
a09e64fb RK |
31 | #include <mach/hardware.h> |
32 | #include <mach/orion5x.h> | |
6f088f1d | 33 | #include <plat/orion_nand.h> |
72053353 | 34 | #include <plat/ehci-orion.h> |
6f088f1d | 35 | #include <plat/time.h> |
28a2b450 | 36 | #include <plat/common.h> |
45173d5e | 37 | #include <plat/addr-map.h> |
585cf175 TP |
38 | #include "common.h" |
39 | ||
40 | /***************************************************************************** | |
41 | * I/O Address Mapping | |
42 | ****************************************************************************/ | |
9dd0b194 | 43 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 44 | { |
9dd0b194 LB |
45 | .virtual = ORION5X_REGS_VIRT_BASE, |
46 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
47 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
48 | .type = MT_DEVICE, |
49 | }, { | |
9dd0b194 LB |
50 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
51 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
52 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
53 | .type = MT_DEVICE, |
54 | }, { | |
9dd0b194 LB |
55 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
56 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
57 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
58 | .type = MT_DEVICE, |
59 | }, { | |
9dd0b194 LB |
60 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
61 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
62 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 63 | .type = MT_DEVICE, |
585cf175 TP |
64 | }, |
65 | }; | |
66 | ||
9dd0b194 | 67 | void __init orion5x_map_io(void) |
585cf175 | 68 | { |
9dd0b194 | 69 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 70 | } |
c67de5b3 | 71 | |
044f6c7c | 72 | |
2f129bf4 AL |
73 | /***************************************************************************** |
74 | * CLK tree | |
75 | ****************************************************************************/ | |
76 | static struct clk *tclk; | |
77 | ||
78 | static void __init clk_init(void) | |
79 | { | |
80 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, | |
81 | orion5x_tclk); | |
4574b886 AL |
82 | |
83 | orion_clkdev_init(tclk); | |
2f129bf4 AL |
84 | } |
85 | ||
044f6c7c LB |
86 | /***************************************************************************** |
87 | * EHCI0 | |
88 | ****************************************************************************/ | |
044f6c7c LB |
89 | void __init orion5x_ehci0_init(void) |
90 | { | |
72053353 AL |
91 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, |
92 | EHCI_PHY_ORION); | |
044f6c7c LB |
93 | } |
94 | ||
95 | ||
96 | /***************************************************************************** | |
97 | * EHCI1 | |
98 | ****************************************************************************/ | |
044f6c7c LB |
99 | void __init orion5x_ehci1_init(void) |
100 | { | |
db33f4de | 101 | orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); |
044f6c7c LB |
102 | } |
103 | ||
104 | ||
e07c9d85 | 105 | /***************************************************************************** |
5c602551 | 106 | * GE00 |
e07c9d85 | 107 | ****************************************************************************/ |
9dd0b194 | 108 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 109 | { |
db33f4de | 110 | orion_ge00_init(eth_data, |
7e3819d8 | 111 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
58569aee APR |
112 | IRQ_ORION5X_ETH_ERR, |
113 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | |
e07c9d85 TP |
114 | } |
115 | ||
044f6c7c | 116 | |
dcf1cece LB |
117 | /***************************************************************************** |
118 | * Ethernet switch | |
119 | ****************************************************************************/ | |
dcf1cece LB |
120 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
121 | { | |
7e3819d8 | 122 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
123 | } |
124 | ||
125 | ||
144aa3db | 126 | /***************************************************************************** |
044f6c7c | 127 | * I2C |
144aa3db | 128 | ****************************************************************************/ |
044f6c7c LB |
129 | void __init orion5x_i2c_init(void) |
130 | { | |
aac7ffa3 AL |
131 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
132 | ||
044f6c7c LB |
133 | } |
134 | ||
135 | ||
f244baa3 | 136 | /***************************************************************************** |
044f6c7c | 137 | * SATA |
f244baa3 | 138 | ****************************************************************************/ |
9dd0b194 | 139 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 140 | { |
db33f4de | 141 | orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); |
f244baa3 SB |
142 | } |
143 | ||
044f6c7c | 144 | |
d323ade1 LB |
145 | /***************************************************************************** |
146 | * SPI | |
147 | ****************************************************************************/ | |
d323ade1 LB |
148 | void __init orion5x_spi_init() |
149 | { | |
4574b886 | 150 | orion_spi_init(SPI_PHYS_BASE); |
d323ade1 LB |
151 | } |
152 | ||
153 | ||
2bac1de2 | 154 | /***************************************************************************** |
044f6c7c LB |
155 | * UART0 |
156 | ****************************************************************************/ | |
044f6c7c LB |
157 | void __init orion5x_uart0_init(void) |
158 | { | |
28a2b450 | 159 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 160 | IRQ_ORION5X_UART0, tclk); |
044f6c7c LB |
161 | } |
162 | ||
044f6c7c LB |
163 | /***************************************************************************** |
164 | * UART1 | |
2bac1de2 | 165 | ****************************************************************************/ |
044f6c7c LB |
166 | void __init orion5x_uart1_init(void) |
167 | { | |
28a2b450 | 168 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 169 | IRQ_ORION5X_UART1, tclk); |
044f6c7c | 170 | } |
2bac1de2 | 171 | |
1d5a1a6e SB |
172 | /***************************************************************************** |
173 | * XOR engine | |
174 | ****************************************************************************/ | |
1d5a1a6e SB |
175 | void __init orion5x_xor_init(void) |
176 | { | |
db33f4de | 177 | orion_xor0_init(ORION5X_XOR_PHYS_BASE, |
ee962723 AL |
178 | ORION5X_XOR_PHYS_BASE + 0x200, |
179 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | |
1d5a1a6e SB |
180 | } |
181 | ||
44350061 AL |
182 | /***************************************************************************** |
183 | * Cryptographic Engines and Security Accelerator (CESA) | |
184 | ****************************************************************************/ | |
185 | static void __init orion5x_crypto_init(void) | |
3a8f7441 | 186 | { |
b6d1c33a | 187 | orion5x_setup_sram_win(); |
44350061 AL |
188 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
189 | SZ_8K, IRQ_ORION5X_CESA); | |
3a8f7441 | 190 | } |
1d5a1a6e | 191 | |
9e058d4f TR |
192 | /***************************************************************************** |
193 | * Watchdog | |
194 | ****************************************************************************/ | |
9e058d4f TR |
195 | void __init orion5x_wdt_init(void) |
196 | { | |
4f04be62 | 197 | orion_wdt_init(); |
9e058d4f TR |
198 | } |
199 | ||
200 | ||
044f6c7c LB |
201 | /***************************************************************************** |
202 | * Time handling | |
203 | ****************************************************************************/ | |
4ee1f6b5 LB |
204 | void __init orion5x_init_early(void) |
205 | { | |
206 | orion_time_set_base(TIMER_VIRT_BASE); | |
207 | } | |
208 | ||
ebe35aff LB |
209 | int orion5x_tclk; |
210 | ||
211 | int __init orion5x_find_tclk(void) | |
212 | { | |
d323ade1 LB |
213 | u32 dev, rev; |
214 | ||
215 | orion5x_pcie_id(&dev, &rev); | |
216 | if (dev == MV88F6183_DEV_ID && | |
217 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
218 | return 133333333; | |
219 | ||
ebe35aff LB |
220 | return 166666667; |
221 | } | |
222 | ||
d2621b82 | 223 | static void __init orion5x_timer_init(void) |
2bac1de2 | 224 | { |
ebe35aff | 225 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
226 | |
227 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
228 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
229 | } |
230 | ||
9dd0b194 | 231 | struct sys_timer orion5x_timer = { |
e7068ad3 | 232 | .init = orion5x_timer_init, |
2bac1de2 LB |
233 | }; |
234 | ||
044f6c7c | 235 | |
c67de5b3 TP |
236 | /***************************************************************************** |
237 | * General | |
238 | ****************************************************************************/ | |
c67de5b3 | 239 | /* |
b46926bb | 240 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 241 | */ |
9dd0b194 | 242 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 243 | { |
9dd0b194 | 244 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
245 | |
246 | if (*dev == MV88F5281_DEV_ID) { | |
247 | if (*rev == MV88F5281_REV_D2) { | |
248 | *dev_name = "MV88F5281-D2"; | |
249 | } else if (*rev == MV88F5281_REV_D1) { | |
250 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
251 | } else if (*rev == MV88F5281_REV_D0) { |
252 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
253 | } else { |
254 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
255 | } | |
256 | } else if (*dev == MV88F5182_DEV_ID) { | |
257 | if (*rev == MV88F5182_REV_A2) { | |
258 | *dev_name = "MV88F5182-A2"; | |
259 | } else { | |
260 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
261 | } | |
c9e3de94 HVR |
262 | } else if (*dev == MV88F5181_DEV_ID) { |
263 | if (*rev == MV88F5181_REV_B1) { | |
264 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
265 | } else if (*rev == MV88F5181L_REV_A1) { |
266 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 267 | } else { |
d2b2a6bb | 268 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 269 | } |
d323ade1 LB |
270 | } else if (*dev == MV88F6183_DEV_ID) { |
271 | if (*rev == MV88F6183_REV_B0) { | |
272 | *dev_name = "MV88F6183-Rev-B0"; | |
273 | } else { | |
274 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
275 | } | |
c67de5b3 TP |
276 | } else { |
277 | *dev_name = "Device-Unknown"; | |
278 | } | |
279 | } | |
280 | ||
9dd0b194 | 281 | void __init orion5x_init(void) |
c67de5b3 TP |
282 | { |
283 | char *dev_name; | |
284 | u32 dev, rev; | |
285 | ||
9dd0b194 | 286 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
287 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
288 | ||
c67de5b3 TP |
289 | /* |
290 | * Setup Orion address map | |
291 | */ | |
9dd0b194 | 292 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e | 293 | |
2f129bf4 AL |
294 | /* Setup root of clk tree */ |
295 | clk_init(); | |
296 | ||
ce72e36e LB |
297 | /* |
298 | * Don't issue "Wait for Interrupt" instruction if we are | |
299 | * running on D0 5281 silicon. | |
300 | */ | |
301 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
302 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
303 | disable_hlt(); | |
304 | } | |
9e058d4f | 305 | |
3fade49b NP |
306 | /* |
307 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
308 | * while 5180n/5181/5281 don't have crypto. | |
309 | */ | |
310 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
311 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
312 | orion5x_crypto_init(); | |
313 | ||
9e058d4f TR |
314 | /* |
315 | * Register watchdog driver | |
316 | */ | |
317 | orion5x_wdt_init(); | |
c67de5b3 | 318 | } |
be73a347 | 319 | |
764cbcc2 RK |
320 | void orion5x_restart(char mode, const char *cmd) |
321 | { | |
322 | /* | |
323 | * Enable and issue soft reset | |
324 | */ | |
325 | orion5x_setbits(RSTOUTn_MASK, (1 << 2)); | |
326 | orion5x_setbits(CPU_SOFT_RESET, 1); | |
327 | mdelay(200); | |
328 | orion5x_clrbits(CPU_SOFT_RESET, 1); | |
329 | } | |
330 | ||
be73a347 GL |
331 | /* |
332 | * Many orion-based systems have buggy bootloader implementations. | |
333 | * This is a common fixup for bogus memory tags. | |
334 | */ | |
0744a3ee RK |
335 | void __init tag_fixup_mem32(struct tag *t, char **from, |
336 | struct meminfo *meminfo) | |
be73a347 GL |
337 | { |
338 | for (; t->hdr.size; t = tag_next(t)) | |
339 | if (t->hdr.tag == ATAG_MEM && | |
340 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
341 | t->u.mem.start & ~PAGE_MASK)) { | |
342 | printk(KERN_WARNING | |
343 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
344 | t->u.mem.size / 1024, t->u.mem.start); | |
345 | t->hdr.tag = 0; | |
346 | } | |
347 | } |