projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| fdd8b079 | 1 | /* |
| fdd8b079 NP |
2 | * Orion CPU Bridge Registers |
| 3 | * | |
| 4 | * This file is licensed under the terms of the GNU General Public | |
| 5 | * License version 2. This program is licensed "as is" without any | |
| 6 | * warranty of any kind, whether express or implied. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | |
| 10 | #define __ASM_ARCH_BRIDGE_REGS_H | |
| 11 | ||
| c22c2c60 | 12 | #include "orion5x.h" |
| fdd8b079 | 13 | |
| 2332656a | 14 | #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) |
| fdd8b079 | 15 | |
| 2332656a | 16 | #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) |
| fdd8b079 | 17 | |
| 2332656a | 18 | #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) |
| 868eb616 | 19 | #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) |
| fdd8b079 | 20 | |
| 2332656a | 21 | #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) |
| fdd8b079 | 22 | |
| 2332656a | 23 | #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) |
| 4ee1f6b5 | 24 | |
| 2332656a | 25 | #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) |
| fdd8b079 | 26 | |
| fdd8b079 NP |
27 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 28 | ||
| 2332656a | 29 | #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) |
| fdd8b079 | 30 | |
| 2332656a | 31 | #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) |
| fdd8b079 | 32 | |
| 2332656a TP |
33 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) |
| 34 | #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) | |
| fdd8b079 | 35 | #endif |