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81fbc5ef PW |
1 | /* |
2 | * OMAP2+ MPU WD_TIMER-specific code | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/err.h> | |
13 | ||
14 | #include <plat/omap_hwmod.h> | |
15 | ||
16 | /* | |
17 | * In order to avoid any assumptions from bootloader regarding WDT | |
18 | * settings, WDT module is reset during init. This enables the watchdog | |
19 | * timer. Hence it is required to disable the watchdog after the WDT reset | |
20 | * during init. Otherwise the system would reboot as per the default | |
21 | * watchdog timer registers settings. | |
22 | */ | |
23 | #define OMAP_WDT_WPS 0x34 | |
24 | #define OMAP_WDT_SPR 0x48 | |
25 | ||
26 | ||
27 | int omap2_wd_timer_disable(struct omap_hwmod *oh) | |
28 | { | |
29 | void __iomem *base; | |
81fbc5ef PW |
30 | |
31 | if (!oh) { | |
32 | pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); | |
33 | return -EINVAL; | |
34 | } | |
35 | ||
36 | base = omap_hwmod_get_mpu_rt_va(oh); | |
37 | if (!base) { | |
38 | pr_err("%s: Could not get the base address for %s\n", | |
39 | oh->name, __func__); | |
40 | return -EINVAL; | |
41 | } | |
42 | ||
81fbc5ef PW |
43 | /* sequence required to disable watchdog */ |
44 | __raw_writel(0xAAAA, base + OMAP_WDT_SPR); | |
45 | while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) | |
46 | cpu_relax(); | |
47 | ||
48 | __raw_writel(0x5555, base + OMAP_WDT_SPR); | |
49 | while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) | |
50 | cpu_relax(); | |
51 | ||
ff2516fb | 52 | return 0; |
81fbc5ef PW |
53 | } |
54 |