Commit | Line | Data |
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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
f8ce2547 | 39 | |
1dbae815 | 40 | #include <asm/mach/time.h> |
ce491cf8 | 41 | #include <plat/dmtimer.h> |
a45c983f | 42 | #include <asm/smp_twd.h> |
cbc94380 | 43 | #include <asm/sched_clock.h> |
4e65331c | 44 | #include "common.h" |
38698bef | 45 | #include <plat/omap_hwmod.h> |
c345c8b0 | 46 | #include <plat/omap_device.h> |
b481113a TKD |
47 | #include <plat/omap-pm.h> |
48 | ||
49 | #include "powerdomain.h" | |
1dbae815 | 50 | |
aa561889 TL |
51 | /* Parent clocks, eventually these will come from the clock framework */ |
52 | ||
53 | #define OMAP2_MPU_SOURCE "sys_ck" | |
54 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
55 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
56 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
57 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
58 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
59 | ||
60 | #ifdef CONFIG_OMAP_32K_TIMER | |
61 | #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE | |
62 | #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE | |
63 | #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE | |
64 | #define OMAP3_SECURE_TIMER 12 | |
65 | #else | |
66 | #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE | |
67 | #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE | |
68 | #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE | |
69 | #define OMAP3_SECURE_TIMER 1 | |
70 | #endif | |
d8328f3b | 71 | |
fa6d79d2 SS |
72 | #define REALTIME_COUNTER_BASE 0x48243200 |
73 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
74 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
75 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
76 | ||
aa561889 TL |
77 | /* Clockevent code */ |
78 | ||
79 | static struct omap_dm_timer clkev; | |
5a3a388f | 80 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 81 | |
0cd61b68 | 82 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 83 | { |
5a3a388f KH |
84 | struct clock_event_device *evt = &clockevent_gpt; |
85 | ||
ee17f114 | 86 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 87 | |
5a3a388f | 88 | evt->event_handler(evt); |
1dbae815 TL |
89 | return IRQ_HANDLED; |
90 | } | |
91 | ||
92 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 93 | .name = "gp_timer", |
b30fabad | 94 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
95 | .handler = omap2_gp_timer_interrupt, |
96 | }; | |
97 | ||
5a3a388f KH |
98 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
99 | struct clock_event_device *evt) | |
1dbae815 | 100 | { |
ee17f114 | 101 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
aa561889 | 102 | 0xffffffff - cycles, 1); |
5a3a388f KH |
103 | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
108 | struct clock_event_device *evt) | |
109 | { | |
110 | u32 period; | |
111 | ||
ee17f114 | 112 | __omap_dm_timer_stop(&clkev, 1, clkev.rate); |
5a3a388f KH |
113 | |
114 | switch (mode) { | |
115 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 116 | period = clkev.rate / HZ; |
5a3a388f | 117 | period -= 1; |
aa561889 | 118 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 119 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
aa561889 | 120 | 0xffffffff - period, 1); |
ee17f114 | 121 | __omap_dm_timer_load_start(&clkev, |
aa561889 TL |
122 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
123 | 0xffffffff - period, 1); | |
5a3a388f KH |
124 | break; |
125 | case CLOCK_EVT_MODE_ONESHOT: | |
126 | break; | |
127 | case CLOCK_EVT_MODE_UNUSED: | |
128 | case CLOCK_EVT_MODE_SHUTDOWN: | |
129 | case CLOCK_EVT_MODE_RESUME: | |
130 | break; | |
131 | } | |
132 | } | |
133 | ||
134 | static struct clock_event_device clockevent_gpt = { | |
f36921be | 135 | .name = "gp_timer", |
5a3a388f KH |
136 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
137 | .shift = 32, | |
11d6ec2e | 138 | .rating = 300, |
5a3a388f KH |
139 | .set_next_event = omap2_gp_timer_set_next_event, |
140 | .set_mode = omap2_gp_timer_set_mode, | |
141 | }; | |
142 | ||
aa561889 TL |
143 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
144 | int gptimer_id, | |
145 | const char *fck_source) | |
5a3a388f | 146 | { |
aa561889 TL |
147 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
148 | struct omap_hwmod *oh; | |
6c0c27fd | 149 | struct resource irq_rsrc, mem_rsrc; |
aa561889 TL |
150 | size_t size; |
151 | int res = 0; | |
6c0c27fd | 152 | int r; |
aa561889 TL |
153 | |
154 | sprintf(name, "timer%d", gptimer_id); | |
155 | omap_hwmod_setup_one(name); | |
156 | oh = omap_hwmod_lookup(name); | |
157 | if (!oh) | |
158 | return -ENODEV; | |
159 | ||
6c0c27fd PW |
160 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); |
161 | if (r) | |
162 | return -ENXIO; | |
163 | timer->irq = irq_rsrc.start; | |
164 | ||
165 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); | |
166 | if (r) | |
167 | return -ENXIO; | |
168 | timer->phys_base = mem_rsrc.start; | |
169 | size = mem_rsrc.end - mem_rsrc.start; | |
aa561889 TL |
170 | |
171 | /* Static mapping, never released */ | |
172 | timer->io_base = ioremap(timer->phys_base, size); | |
173 | if (!timer->io_base) | |
174 | return -ENXIO; | |
175 | ||
176 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 177 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 TL |
178 | if (IS_ERR(timer->fclk)) |
179 | return -ENODEV; | |
180 | ||
aa561889 TL |
181 | omap_hwmod_enable(oh); |
182 | ||
b7b4ff76 JH |
183 | if (omap_dm_timer_reserve_systimer(gptimer_id)) |
184 | return -ENODEV; | |
11a0186f | 185 | |
aa561889 TL |
186 | if (gptimer_id != 12) { |
187 | struct clk *src; | |
188 | ||
189 | src = clk_get(NULL, fck_source); | |
190 | if (IS_ERR(src)) { | |
191 | res = -EINVAL; | |
192 | } else { | |
193 | res = __omap_dm_timer_set_source(timer->fclk, src); | |
194 | if (IS_ERR_VALUE(res)) | |
195 | pr_warning("%s: timer%i cannot set source\n", | |
196 | __func__, gptimer_id); | |
197 | clk_put(src); | |
198 | } | |
199 | } | |
ee17f114 TL |
200 | __omap_dm_timer_init_regs(timer); |
201 | __omap_dm_timer_reset(timer, 1, 1); | |
aa561889 TL |
202 | timer->posted = 1; |
203 | ||
204 | timer->rate = clk_get_rate(timer->fclk); | |
1dbae815 | 205 | |
aa561889 | 206 | timer->reserved = 1; |
38698bef | 207 | |
aa561889 TL |
208 | return res; |
209 | } | |
f248076c | 210 | |
aa561889 TL |
211 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
212 | const char *fck_source) | |
213 | { | |
214 | int res; | |
f248076c | 215 | |
aa561889 TL |
216 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); |
217 | BUG_ON(res); | |
f248076c | 218 | |
98e182a2 | 219 | omap2_gp_timer_irq.dev_id = (void *)&clkev; |
aa561889 | 220 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 221 | |
ee17f114 | 222 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
223 | |
224 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
225 | clockevent_gpt.shift); |
226 | clockevent_gpt.max_delta_ns = | |
227 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
228 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
229 | clockevent_delta2ns(3, &clockevent_gpt); |
230 | /* Timer internal resynch latency. */ | |
5a3a388f | 231 | |
11d6ec2e SS |
232 | clockevent_gpt.cpumask = cpu_possible_mask; |
233 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
5a3a388f | 234 | clockevents_register_device(&clockevent_gpt); |
aa561889 TL |
235 | |
236 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
237 | gptimer_id, clkev.rate); | |
5a3a388f KH |
238 | } |
239 | ||
f248076c | 240 | /* Clocksource code */ |
3d05a3e8 | 241 | static struct omap_dm_timer clksrc; |
1fe97c8f | 242 | static bool use_gptimer_clksrc; |
3d05a3e8 | 243 | |
5a3a388f KH |
244 | /* |
245 | * clocksource | |
246 | */ | |
8e19608e | 247 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 248 | { |
ee17f114 | 249 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f KH |
250 | } |
251 | ||
252 | static struct clocksource clocksource_gpt = { | |
f36921be | 253 | .name = "gp_timer", |
5a3a388f KH |
254 | .rating = 300, |
255 | .read = clocksource_read_cycles, | |
256 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
257 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
258 | }; | |
259 | ||
2f0778af | 260 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 261 | { |
3d05a3e8 | 262 | if (clksrc.reserved) |
dbc3982a | 263 | return __omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f | 264 | |
2f0778af | 265 | return 0; |
3d05a3e8 TL |
266 | } |
267 | ||
45caae74 | 268 | #ifdef CONFIG_OMAP_32K_TIMER |
3d05a3e8 | 269 | /* Setup free-running counter for clocksource */ |
1fe97c8f VH |
270 | static int __init omap2_sync32k_clocksource_init(void) |
271 | { | |
272 | int ret; | |
273 | struct omap_hwmod *oh; | |
274 | void __iomem *vbase; | |
275 | const char *oh_name = "counter_32k"; | |
276 | ||
277 | /* | |
278 | * First check hwmod data is available for sync32k counter | |
279 | */ | |
280 | oh = omap_hwmod_lookup(oh_name); | |
281 | if (!oh || oh->slaves_cnt == 0) | |
282 | return -ENODEV; | |
283 | ||
284 | omap_hwmod_setup_one(oh_name); | |
285 | ||
286 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
287 | if (!vbase) { | |
288 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
289 | return -ENXIO; | |
290 | } | |
291 | ||
292 | ret = omap_hwmod_enable(oh); | |
293 | if (ret) { | |
294 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
295 | __func__, ret); | |
296 | return ret; | |
297 | } | |
298 | ||
299 | ret = omap_init_clocksource_32k(vbase); | |
300 | if (ret) { | |
301 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
302 | __func__, ret); | |
303 | omap_hwmod_idle(oh); | |
304 | } | |
305 | ||
306 | return ret; | |
307 | } | |
45caae74 IG |
308 | #else |
309 | static inline int omap2_sync32k_clocksource_init(void) | |
310 | { | |
311 | return -ENODEV; | |
312 | } | |
313 | #endif | |
1fe97c8f VH |
314 | |
315 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
3d05a3e8 TL |
316 | const char *fck_source) |
317 | { | |
318 | int res; | |
319 | ||
320 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); | |
321 | BUG_ON(res); | |
5a3a388f | 322 | |
ee17f114 | 323 | __omap_dm_timer_load_start(&clksrc, |
e9d0b97e | 324 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); |
2f0778af | 325 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 326 | |
3d05a3e8 TL |
327 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
328 | pr_err("Could not register clocksource %s\n", | |
329 | clocksource_gpt.name); | |
1fe97c8f VH |
330 | else |
331 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | |
332 | gptimer_id, clksrc.rate); | |
333 | } | |
334 | ||
335 | static void __init omap2_clocksource_init(int gptimer_id, | |
336 | const char *fck_source) | |
337 | { | |
338 | /* | |
339 | * First give preference to kernel parameter configuration | |
340 | * by user (clocksource="gp_timer"). | |
341 | * | |
342 | * In case of missing kernel parameter for clocksource, | |
343 | * first check for availability for 32k-sync timer, in case | |
344 | * of failure in finding 32k_counter module or registering | |
345 | * it as clocksource, execution will fallback to gp-timer. | |
346 | */ | |
347 | if (use_gptimer_clksrc == true) | |
348 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
349 | else if (omap2_sync32k_clocksource_init()) | |
350 | /* Fall back to gp-timer code */ | |
351 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
5a3a388f | 352 | } |
5a3a388f | 353 | |
fa6d79d2 SS |
354 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
355 | /* | |
356 | * The realtime counter also called master counter, is a free-running | |
357 | * counter, which is related to real time. It produces the count used | |
358 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
359 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
360 | * in different power modes, the master counter shifts operation between | |
361 | * clocks, adjusting the increment per clock in hardware accordingly to | |
362 | * maintain a constant count rate. | |
363 | */ | |
364 | static void __init realtime_counter_init(void) | |
365 | { | |
366 | void __iomem *base; | |
367 | static struct clk *sys_clk; | |
368 | unsigned long rate; | |
369 | unsigned int reg, num, den; | |
370 | ||
371 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
372 | if (!base) { | |
373 | pr_err("%s: ioremap failed\n", __func__); | |
374 | return; | |
375 | } | |
376 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
377 | if (!sys_clk) { | |
378 | pr_err("%s: failed to get system clock handle\n", __func__); | |
379 | iounmap(base); | |
380 | return; | |
381 | } | |
382 | ||
383 | rate = clk_get_rate(sys_clk); | |
384 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
385 | switch (rate) { | |
386 | case 1200000: | |
387 | num = 64; | |
388 | den = 125; | |
389 | break; | |
390 | case 1300000: | |
391 | num = 768; | |
392 | den = 1625; | |
393 | break; | |
394 | case 19200000: | |
395 | num = 8; | |
396 | den = 25; | |
397 | break; | |
398 | case 2600000: | |
399 | num = 384; | |
400 | den = 1625; | |
401 | break; | |
402 | case 2700000: | |
403 | num = 256; | |
404 | den = 1125; | |
405 | break; | |
406 | case 38400000: | |
407 | default: | |
408 | /* Program it for 38.4 MHz */ | |
409 | num = 4; | |
410 | den = 25; | |
411 | break; | |
412 | } | |
413 | ||
414 | /* Program numerator and denumerator registers */ | |
415 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
416 | NUMERATOR_DENUMERATOR_MASK; | |
417 | reg |= num; | |
418 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
419 | ||
420 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
421 | NUMERATOR_DENUMERATOR_MASK; | |
422 | reg |= den; | |
423 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
424 | ||
425 | iounmap(base); | |
426 | } | |
427 | #else | |
428 | static inline void __init realtime_counter_init(void) | |
429 | {} | |
430 | #endif | |
431 | ||
3d05a3e8 TL |
432 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ |
433 | clksrc_nr, clksrc_src) \ | |
e74984e4 TL |
434 | static void __init omap##name##_timer_init(void) \ |
435 | { \ | |
aa561889 | 436 | omap2_gp_clockevent_init((clkev_nr), clkev_src); \ |
1fe97c8f | 437 | omap2_clocksource_init((clksrc_nr), clksrc_src); \ |
e74984e4 TL |
438 | } |
439 | ||
440 | #define OMAP_SYS_TIMER(name) \ | |
441 | struct sys_timer omap##name##_timer = { \ | |
442 | .init = omap##name##_timer_init, \ | |
443 | }; | |
444 | ||
445 | #ifdef CONFIG_ARCH_OMAP2 | |
3d05a3e8 | 446 | OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) |
e74984e4 TL |
447 | OMAP_SYS_TIMER(2) |
448 | #endif | |
449 | ||
450 | #ifdef CONFIG_ARCH_OMAP3 | |
3d05a3e8 | 451 | OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) |
e74984e4 | 452 | OMAP_SYS_TIMER(3) |
3d05a3e8 TL |
453 | OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, |
454 | 2, OMAP3_MPU_SOURCE) | |
e74984e4 TL |
455 | OMAP_SYS_TIMER(3_secure) |
456 | #endif | |
457 | ||
08f30989 AM |
458 | #ifdef CONFIG_SOC_AM33XX |
459 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) | |
460 | OMAP_SYS_TIMER(3_am33xx) | |
461 | #endif | |
462 | ||
e74984e4 | 463 | #ifdef CONFIG_ARCH_OMAP4 |
39e1d4c1 | 464 | #ifdef CONFIG_LOCAL_TIMERS |
a45c983f MZ |
465 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
466 | OMAP44XX_LOCAL_TWD_BASE, | |
467 | OMAP44XX_IRQ_LOCALTIMER); | |
39e1d4c1 | 468 | #endif |
a45c983f MZ |
469 | |
470 | static void __init omap4_timer_init(void) | |
471 | { | |
aa561889 | 472 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); |
1fe97c8f | 473 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
a45c983f MZ |
474 | #ifdef CONFIG_LOCAL_TIMERS |
475 | /* Local timers are not supprted on OMAP4430 ES1.0 */ | |
476 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
477 | int err; | |
478 | ||
479 | err = twd_local_timer_register(&twd_local_timer); | |
480 | if (err) | |
481 | pr_err("twd_local_timer_register failed %d\n", err); | |
482 | } | |
483 | #endif | |
1dbae815 | 484 | } |
e74984e4 TL |
485 | OMAP_SYS_TIMER(4) |
486 | #endif | |
c345c8b0 | 487 | |
37b3280d | 488 | #ifdef CONFIG_SOC_OMAP5 |
fa6d79d2 SS |
489 | static void __init omap5_timer_init(void) |
490 | { | |
491 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); | |
492 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); | |
493 | realtime_counter_init(); | |
494 | } | |
37b3280d S |
495 | OMAP_SYS_TIMER(5) |
496 | #endif | |
497 | ||
c345c8b0 TKD |
498 | /** |
499 | * omap_timer_init - build and register timer device with an | |
500 | * associated timer hwmod | |
501 | * @oh: timer hwmod pointer to be used to build timer device | |
502 | * @user: parameter that can be passed from calling hwmod API | |
503 | * | |
504 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
505 | * devices present in the system. The number of timer devices is known | |
506 | * by parsing through the hwmod database for a given class name. At the | |
507 | * end of function call memory is allocated for timer device and it is | |
508 | * registered to the framework ready to be proved by the driver. | |
509 | */ | |
510 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
511 | { | |
512 | int id; | |
513 | int ret = 0; | |
514 | char *name = "omap_timer"; | |
515 | struct dmtimer_platform_data *pdata; | |
c541c15f | 516 | struct platform_device *pdev; |
c345c8b0 TKD |
517 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
518 | ||
519 | pr_debug("%s: %s\n", __func__, oh->name); | |
520 | ||
521 | /* on secure device, do not register secure timer */ | |
522 | timer_dev_attr = oh->dev_attr; | |
523 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
524 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
525 | return ret; | |
526 | ||
527 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
528 | if (!pdata) { | |
529 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
530 | return -ENOMEM; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Extract the IDs from name field in hwmod database | |
535 | * and use the same for constructing ids' for the | |
536 | * timer devices. In a way, we are avoiding usage of | |
537 | * static variable witin the function to do the same. | |
538 | * CAUTION: We have to be careful and make sure the | |
539 | * name in hwmod database does not change in which case | |
540 | * we might either make corresponding change here or | |
541 | * switch back static variable mechanism. | |
542 | */ | |
543 | sscanf(oh->name, "timer%2d", &id); | |
544 | ||
d1c1691b JH |
545 | if (timer_dev_attr) |
546 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 547 | |
c541c15f | 548 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 549 | NULL, 0, 0); |
c345c8b0 | 550 | |
c541c15f | 551 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
552 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
553 | __func__, name, oh->name); | |
554 | ret = -EINVAL; | |
555 | } | |
556 | ||
557 | kfree(pdata); | |
558 | ||
559 | return ret; | |
560 | } | |
3392cdd3 TKD |
561 | |
562 | /** | |
563 | * omap2_dm_timer_init - top level regular device initialization | |
564 | * | |
565 | * Uses dedicated hwmod api to parse through hwmod database for | |
566 | * given class name and then build and register the timer device. | |
567 | */ | |
568 | static int __init omap2_dm_timer_init(void) | |
569 | { | |
570 | int ret; | |
571 | ||
572 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); | |
573 | if (unlikely(ret)) { | |
574 | pr_err("%s: device registration failed.\n", __func__); | |
575 | return -EINVAL; | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | arch_initcall(omap2_dm_timer_init); | |
1fe97c8f VH |
581 | |
582 | /** | |
583 | * omap2_override_clocksource - clocksource override with user configuration | |
584 | * | |
585 | * Allows user to override default clocksource, using kernel parameter | |
586 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
587 | * | |
588 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
589 | * and not introducing any OMAP specific interface. | |
590 | */ | |
591 | static int __init omap2_override_clocksource(char *str) | |
592 | { | |
593 | if (!str) | |
594 | return 0; | |
595 | /* | |
596 | * For OMAP architecture, we only have two options | |
597 | * - sync_32k (default) | |
598 | * - gp_timer (sys_clk based) | |
599 | */ | |
600 | if (!strcmp(str, "gp_timer")) | |
601 | use_gptimer_clksrc = true; | |
602 | ||
603 | return 0; | |
604 | } | |
605 | early_param("clocksource", omap2_override_clocksource); |