[linux-2.6-block.git] / arch / arm / mach-omap2 / timer.c

/*
 * linux/arch/arm/mach-omap2/timer.c
 *
 * OMAP2 GP timer support.
 *
 * Copyright (C) 2009 Nokia Corporation
 *
 * Update to use new clocksource/clockevent layers
 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
 * Copyright (C) 2007 MontaVista Software, Inc.
 *
 * Original driver:
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *         Juha Yrjölä <juha.yrjola@nokia.com>
 * OMAP Dual-mode timer framework support by Timo Teras
 *
 * Some parts based off of TI's 24xx code:
 *
 * Copyright (C) 2004-2009 Texas Instruments, Inc.
 *
 * Roughly modelled after the OMAP1 MPU timer code.
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/slab.h>

#include <asm/mach/time.h>
#include <plat/dmtimer.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>
#include <plat/common.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>

/* Parent clocks, eventually these will come from the clock framework */

#define OMAP2_MPU_SOURCE	"sys_ck"
#define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
#define OMAP4_MPU_SOURCE	"sys_clkin_ck"
#define OMAP2_32K_SOURCE	"func_32k_ck"
#define OMAP3_32K_SOURCE	"omap_32k_fck"
#define OMAP4_32K_SOURCE	"sys_32k_ck"

#ifdef CONFIG_OMAP_32K_TIMER
#define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER	12
#else
#define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER	1
#endif

/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
#define MAX_GPTIMER_ID		12

u32 sys_timer_reserved;

/* Clockevent code */

static struct omap_dm_timer clkev;
static struct clock_event_device clockevent_gpt;

static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_gpt;

	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction omap2_gp_timer_irq = {
	.name		= "gp timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= omap2_gp_timer_interrupt,
};

static int omap2_gp_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
						0xffffffff - cycles, 1);

	return 0;
}

static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 period;

	__omap_dm_timer_stop(&clkev, 1, clkev.rate);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		period = clkev.rate / HZ;
		period -= 1;
		/* Looks like we need to first set the load value separately */
		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
					0xffffffff - period, 1);
		__omap_dm_timer_load_start(&clkev,
					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
						0xffffffff - period, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device clockevent_gpt = {
	.name		= "gp timer",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_next_event	= omap2_gp_timer_set_next_event,
	.set_mode	= omap2_gp_timer_set_mode,
};

static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
						int gptimer_id,
						const char *fck_source)
{
	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
	struct omap_hwmod *oh;
	size_t size;
	int res = 0;

	sprintf(name, "timer%d", gptimer_id);
	omap_hwmod_setup_one(name);
	oh = omap_hwmod_lookup(name);
	if (!oh)
		return -ENODEV;

	timer->irq = oh->mpu_irqs[0].irq;
	timer->phys_base = oh->slaves[0]->addr->pa_start;
	size = oh->slaves[0]->addr->pa_end - timer->phys_base;

	/* Static mapping, never released */
	timer->io_base = ioremap(timer->phys_base, size);
	if (!timer->io_base)
		return -ENXIO;

	/* After the dmtimer is using hwmod these clocks won't be needed */
	sprintf(name, "gpt%d_fck", gptimer_id);
	timer->fclk = clk_get(NULL, name);
	if (IS_ERR(timer->fclk))
		return -ENODEV;

	sprintf(name, "gpt%d_ick", gptimer_id);
	timer->iclk = clk_get(NULL, name);
	if (IS_ERR(timer->iclk)) {
		clk_put(timer->fclk);
		return -ENODEV;
	}

	omap_hwmod_enable(oh);

	sys_timer_reserved |= (1 << (gptimer_id - 1));

	if (gptimer_id != 12) {
		struct clk *src;

		src = clk_get(NULL, fck_source);
		if (IS_ERR(src)) {
			res = -EINVAL;
		} else {
			res = __omap_dm_timer_set_source(timer->fclk, src);
			if (IS_ERR_VALUE(res))
				pr_warning("%s: timer%i cannot set source\n",
						__func__, gptimer_id);
			clk_put(src);
		}
	}
	__omap_dm_timer_init_regs(timer);
	__omap_dm_timer_reset(timer, 1, 1);
	timer->posted = 1;

	timer->rate = clk_get_rate(timer->fclk);

	timer->reserved = 1;

	return res;
}

static void __init omap2_gp_clockevent_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
	BUG_ON(res);

	omap2_gp_timer_irq.dev_id = (void *)&clkev;
	setup_irq(clkev.irq, &omap2_gp_timer_irq);

	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);

	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
				     clockevent_gpt.shift);
	clockevent_gpt.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	clockevent_gpt.min_delta_ns =
		clockevent_delta2ns(3, &clockevent_gpt);
		/* Timer internal resynch latency. */

	clockevent_gpt.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_gpt);

	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
		gptimer_id, clkev.rate);
}

/* Clocksource code */

#ifdef CONFIG_OMAP_32K_TIMER
/*
 * When 32k-timer is enabled, don't use GPTimer for clocksource
 * instead, just leave default clocksource which uses the 32k
 * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 */

static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
{
	omap_init_clocksource_32k();
}

#else

static struct omap_dm_timer clksrc;

/*
 * clocksource
 */
static DEFINE_CLOCK_DATA(cd);
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
}

static struct clocksource clocksource_gpt = {
	.name		= "gp timer",
	.rating		= 300,
	.read		= clocksource_read_cycles,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void notrace dmtimer_update_sched_clock(void)
{
	u32 cyc;

	cyc = __omap_dm_timer_read_counter(&clksrc, 1);

	update_sched_clock(&cd, cyc, (u32)~0);
}

unsigned long long notrace sched_clock(void)
{
	u32 cyc = 0;

	if (clksrc.reserved)
		cyc = __omap_dm_timer_read_counter(&clksrc, 1);

	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}

/* Setup free-running counter for clocksource */
static void __init omap2_gp_clocksource_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	BUG_ON(res);

	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
		gptimer_id, clksrc.rate);

	__omap_dm_timer_load_start(&clksrc,
			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
	init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);

	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
		pr_err("Could not register clocksource %s\n",
			clocksource_gpt.name);
}
#endif

#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
				clksrc_nr, clksrc_src)			\
static void __init omap##name##_timer_init(void)			\
{									\
	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
	omap2_gp_clocksource_init((clksrc_nr), clksrc_src);		\
}

#define OMAP_SYS_TIMER(name)						\
struct sys_timer omap##name##_timer = {					\
	.init	= omap##name##_timer_init,				\
};

#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER(2)
#endif

#ifdef CONFIG_ARCH_OMAP3
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
			2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3_secure)
#endif

#ifdef CONFIG_ARCH_OMAP4
static void __init omap4_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
	BUG_ON(!twd_base);
#endif
	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
	omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
}
OMAP_SYS_TIMER(4)
#endif

/**
 * omap2_dm_timer_set_src - change the timer input clock source
 * @pdev:	timer platform device pointer
 * @source:	array index of parent clock source
 */
static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
{
	int ret;
	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
	struct clk *fclk, *parent;
	char *parent_name = NULL;

	fclk = clk_get(&pdev->dev, "fck");
	if (IS_ERR_OR_NULL(fclk)) {
		dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
				__func__, __LINE__);
		return -EINVAL;
	}

	switch (source) {
	case OMAP_TIMER_SRC_SYS_CLK:
		parent_name = "sys_ck";
		break;

	case OMAP_TIMER_SRC_32_KHZ:
		parent_name = "32k_ck";
		break;

	case OMAP_TIMER_SRC_EXT_CLK:
		if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
			parent_name = "alt_ck";
			break;
		}
		dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
			__func__, __LINE__);
		clk_put(fclk);
		return -EINVAL;
	}

	parent = clk_get(&pdev->dev, parent_name);
	if (IS_ERR_OR_NULL(parent)) {
		dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
			__func__, __LINE__, parent_name);
		clk_put(fclk);
		return -EINVAL;
	}

	ret = clk_set_parent(fclk, parent);
	if (IS_ERR_VALUE(ret)) {
		dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
			__func__, parent_name);
		ret = -EINVAL;
	}

	clk_put(parent);
	clk_put(fclk);

	return ret;
}

struct omap_device_pm_latency omap2_dmtimer_latency[] = {
	{
		.deactivate_func = omap_device_idle_hwmods,
		.activate_func   = omap_device_enable_hwmods,
		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
	},
};

/**
 * omap_timer_init - build and register timer device with an
 * associated timer hwmod
 * @oh:	timer hwmod pointer to be used to build timer device
 * @user:	parameter that can be passed from calling hwmod API
 *
 * Called by omap_hwmod_for_each_by_class to register each of the timer
 * devices present in the system. The number of timer devices is known
 * by parsing through the hwmod database for a given class name. At the
 * end of function call memory is allocated for timer device and it is
 * registered to the framework ready to be proved by the driver.
 */
static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
{
	int id;
	int ret = 0;
	char *name = "omap_timer";
	struct dmtimer_platform_data *pdata;
	struct omap_device *od;
	struct omap_timer_capability_dev_attr *timer_dev_attr;

	pr_debug("%s: %s\n", __func__, oh->name);

	/* on secure device, do not register secure timer */
	timer_dev_attr = oh->dev_attr;
	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
			return ret;

	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	if (!pdata) {
		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
		return -ENOMEM;
	}

	/*
	 * Extract the IDs from name field in hwmod database
	 * and use the same for constructing ids' for the
	 * timer devices. In a way, we are avoiding usage of
	 * static variable witin the function to do the same.
	 * CAUTION: We have to be careful and make sure the
	 * name in hwmod database does not change in which case
	 * we might either make corresponding change here or
	 * switch back static variable mechanism.
	 */
	sscanf(oh->name, "timer%2d", &id);

	pdata->set_timer_src = omap2_dm_timer_set_src;
	pdata->timer_ip_version = oh->class->rev;

	od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
			omap2_dmtimer_latency,
			ARRAY_SIZE(omap2_dmtimer_latency),
			0);

	if (IS_ERR(od)) {
		pr_err("%s: Can't build omap_device for %s: %s.\n",
			__func__, name, oh->name);
		ret = -EINVAL;
	}

	kfree(pdata);

	return ret;
}
Commit	Line	Data
1dbae815	1	/*
0f622e8c	2	* linux/arch/arm/mach-omap2/timer.c
1dbae815 TL	3	*
	4	* OMAP2 GP timer support.
	5	*
f248076c PW	6	* Copyright (C) 2009 Nokia Corporation
f248076c PW	7	*
5a3a388f KH	8	* Update to use new clocksource/clockevent layers
	9	* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
	10	* Copyright (C) 2007 MontaVista Software, Inc.
	11	*
	12	* Original driver:
1dbae815 TL	13	* Copyright (C) 2005 Nokia Corporation
1dbae815 TL	14	* Author: Paul Mundt <paul.mundt@nokia.com>
96de0e25	15	* Juha Yrjölä <juha.yrjola@nokia.com>
77900a2f	16	* OMAP Dual-mode timer framework support by Timo Teras
1dbae815 TL	17	*
	18	* Some parts based off of TI's 24xx code:
	19	*
44169075	20	* Copyright (C) 2004-2009 Texas Instruments, Inc.
1dbae815 TL	21	*
1dbae815 TL	22	* Roughly modelled after the OMAP1 MPU timer code.
44169075	23	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 TL	24	*
	25	* This file is subject to the terms and conditions of the GNU General Public
	26	* License. See the file "COPYING" in the main directory of this archive
	27	* for more details.
	28	*/
	29	#include <linux/init.h>
	30	#include <linux/time.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/err.h>
f8ce2547	33	#include <linux/clk.h>
77900a2f	34	#include <linux/delay.h>
e6687290	35	#include <linux/irq.h>
5a3a388f KH	36	#include <linux/clocksource.h>
5a3a388f KH	37	#include <linux/clockchips.h>
c345c8b0	38	#include <linux/slab.h>
f8ce2547	39
1dbae815	40	#include <asm/mach/time.h>
ce491cf8	41	#include <plat/dmtimer.h>
39e1d4c1	42	#include <asm/localtimer.h>
cbc94380	43	#include <asm/sched_clock.h>
38698bef PW	44	#include <plat/common.h>
38698bef PW	45	#include <plat/omap_hwmod.h>
c345c8b0	46	#include <plat/omap_device.h>
1dbae815	47
aa561889 TL	48	/* Parent clocks, eventually these will come from the clock framework */
	49
	50	#define OMAP2_MPU_SOURCE "sys_ck"
	51	#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
	52	#define OMAP4_MPU_SOURCE "sys_clkin_ck"
	53	#define OMAP2_32K_SOURCE "func_32k_ck"
	54	#define OMAP3_32K_SOURCE "omap_32k_fck"
	55	#define OMAP4_32K_SOURCE "sys_32k_ck"
	56
	57	#ifdef CONFIG_OMAP_32K_TIMER
	58	#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
	59	#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
	60	#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
	61	#define OMAP3_SECURE_TIMER 12
	62	#else
	63	#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
	64	#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
	65	#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
	66	#define OMAP3_SECURE_TIMER 1
	67	#endif
d8328f3b	68
f248076c PW	69	/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
	70	#define MAX_GPTIMER_ID 12
	71
11a0186f TL	72	u32 sys_timer_reserved;
11a0186f TL	73
aa561889 TL	74	/* Clockevent code */
	75
	76	static struct omap_dm_timer clkev;
5a3a388f	77	static struct clock_event_device clockevent_gpt;
1dbae815	78
0cd61b68	79	static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
1dbae815	80	{
5a3a388f KH	81	struct clock_event_device *evt = &clockevent_gpt;
5a3a388f KH	82
ee17f114	83	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
1dbae815	84
5a3a388f	85	evt->event_handler(evt);
1dbae815 TL	86	return IRQ_HANDLED;
	87	}
	88
	89	static struct irqaction omap2_gp_timer_irq = {
	90	.name = "gp timer",
b30fabad	91	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
1dbae815 TL	92	.handler = omap2_gp_timer_interrupt,
	93	};
	94
5a3a388f KH	95	static int omap2_gp_timer_set_next_event(unsigned long cycles,
5a3a388f KH	96	struct clock_event_device *evt)
1dbae815	97	{
ee17f114	98	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
aa561889	99	0xffffffff - cycles, 1);
5a3a388f KH	100
	101	return 0;
	102	}
	103
	104	static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
	105	struct clock_event_device *evt)
	106	{
	107	u32 period;
	108
ee17f114	109	__omap_dm_timer_stop(&clkev, 1, clkev.rate);
5a3a388f KH	110
	111	switch (mode) {
	112	case CLOCK_EVT_MODE_PERIODIC:
aa561889	113	period = clkev.rate / HZ;
5a3a388f	114	period -= 1;
aa561889	115	/* Looks like we need to first set the load value separately */
ee17f114	116	__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
aa561889	117	0xffffffff - period, 1);
ee17f114	118	__omap_dm_timer_load_start(&clkev,
aa561889 TL	119	OMAP_TIMER_CTRL_AR \| OMAP_TIMER_CTRL_ST,
aa561889 TL	120	0xffffffff - period, 1);
5a3a388f KH	121	break;
	122	case CLOCK_EVT_MODE_ONESHOT:
	123	break;
	124	case CLOCK_EVT_MODE_UNUSED:
	125	case CLOCK_EVT_MODE_SHUTDOWN:
	126	case CLOCK_EVT_MODE_RESUME:
	127	break;
	128	}
	129	}
	130
	131	static struct clock_event_device clockevent_gpt = {
	132	.name = "gp timer",
	133	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	134	.shift = 32,
	135	.set_next_event = omap2_gp_timer_set_next_event,
	136	.set_mode = omap2_gp_timer_set_mode,
	137	};
	138
aa561889 TL	139	static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
	140	int gptimer_id,
	141	const char *fck_source)
5a3a388f	142	{
aa561889 TL	143	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
	144	struct omap_hwmod *oh;
	145	size_t size;
	146	int res = 0;
	147
	148	sprintf(name, "timer%d", gptimer_id);
	149	omap_hwmod_setup_one(name);
	150	oh = omap_hwmod_lookup(name);
	151	if (!oh)
	152	return -ENODEV;
	153
	154	timer->irq = oh->mpu_irqs[0].irq;
	155	timer->phys_base = oh->slaves[0]->addr->pa_start;
	156	size = oh->slaves[0]->addr->pa_end - timer->phys_base;
	157
	158	/* Static mapping, never released */
	159	timer->io_base = ioremap(timer->phys_base, size);
	160	if (!timer->io_base)
	161	return -ENXIO;
	162
	163	/* After the dmtimer is using hwmod these clocks won't be needed */
	164	sprintf(name, "gpt%d_fck", gptimer_id);
	165	timer->fclk = clk_get(NULL, name);
	166	if (IS_ERR(timer->fclk))
	167	return -ENODEV;
	168
	169	sprintf(name, "gpt%d_ick", gptimer_id);
	170	timer->iclk = clk_get(NULL, name);
	171	if (IS_ERR(timer->iclk)) {
	172	clk_put(timer->fclk);
	173	return -ENODEV;
	174	}
f248076c	175
aa561889 TL	176	omap_hwmod_enable(oh);
aa561889 TL	177
11a0186f TL	178	sys_timer_reserved \|= (1 << (gptimer_id - 1));
11a0186f TL	179
aa561889 TL	180	if (gptimer_id != 12) {
	181	struct clk *src;
	182
	183	src = clk_get(NULL, fck_source);
	184	if (IS_ERR(src)) {
	185	res = -EINVAL;
	186	} else {
	187	res = __omap_dm_timer_set_source(timer->fclk, src);
	188	if (IS_ERR_VALUE(res))
	189	pr_warning("%s: timer%i cannot set source\n",
	190	__func__, gptimer_id);
	191	clk_put(src);
	192	}
	193	}
ee17f114 TL	194	__omap_dm_timer_init_regs(timer);
ee17f114 TL	195	__omap_dm_timer_reset(timer, 1, 1);
aa561889 TL	196	timer->posted = 1;
	197
	198	timer->rate = clk_get_rate(timer->fclk);
1dbae815	199
aa561889	200	timer->reserved = 1;
38698bef	201
aa561889 TL	202	return res;
aa561889 TL	203	}
f248076c	204
aa561889 TL	205	static void __init omap2_gp_clockevent_init(int gptimer_id,
	206	const char *fck_source)
	207	{
	208	int res;
f248076c	209
aa561889 TL	210	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
aa561889 TL	211	BUG_ON(res);
f248076c	212
98e182a2	213	omap2_gp_timer_irq.dev_id = (void *)&clkev;
aa561889	214	setup_irq(clkev.irq, &omap2_gp_timer_irq);
5a3a388f	215
ee17f114	216	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
aa561889 TL	217
aa561889 TL	218	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
5a3a388f KH	219	clockevent_gpt.shift);
	220	clockevent_gpt.max_delta_ns =
	221	clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	222	clockevent_gpt.min_delta_ns =
df88acbb AK	223	clockevent_delta2ns(3, &clockevent_gpt);
df88acbb AK	224	/* Timer internal resynch latency. */
5a3a388f	225
320ab2b0	226	clockevent_gpt.cpumask = cpumask_of(0);
5a3a388f	227	clockevents_register_device(&clockevent_gpt);
aa561889 TL	228
	229	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
	230	gptimer_id, clkev.rate);
5a3a388f KH	231	}
5a3a388f KH	232
f248076c PW	233	/* Clocksource code */
f248076c PW	234
5a3a388f	235	#ifdef CONFIG_OMAP_32K_TIMER
0f622e8c	236	/*
5a3a388f KH	237	* When 32k-timer is enabled, don't use GPTimer for clocksource
5a3a388f KH	238	* instead, just leave default clocksource which uses the 32k
d8328f3b	239	* sync counter. See clocksource setup in plat-omap/counter_32k.c
5a3a388f KH	240	*/
5a3a388f KH	241
3d05a3e8	242	static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
d8328f3b PW	243	{
	244	omap_init_clocksource_32k();
	245	}
	246
5a3a388f	247	#else
3d05a3e8 TL	248
	249	static struct omap_dm_timer clksrc;
	250
5a3a388f KH	251	/*
	252	* clocksource
	253	*/
cbc94380	254	static DEFINE_CLOCK_DATA(cd);
8e19608e	255	static cycle_t clocksource_read_cycles(struct clocksource *cs)
5a3a388f	256	{
ee17f114	257	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
5a3a388f KH	258	}
	259
	260	static struct clocksource clocksource_gpt = {
	261	.name = "gp timer",
	262	.rating = 300,
	263	.read = clocksource_read_cycles,
	264	.mask = CLOCKSOURCE_MASK(32),
5a3a388f KH	265	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	266	};
	267
cbc94380 PW	268	static void notrace dmtimer_update_sched_clock(void)
	269	{
	270	u32 cyc;
	271
ee17f114	272	cyc = __omap_dm_timer_read_counter(&clksrc, 1);
cbc94380 PW	273
	274	update_sched_clock(&cd, cyc, (u32)~0);
	275	}
	276
3d05a3e8	277	unsigned long long notrace sched_clock(void)
5a3a388f	278	{
3d05a3e8	279	u32 cyc = 0;
5a3a388f	280
3d05a3e8	281	if (clksrc.reserved)
ee17f114	282	cyc = __omap_dm_timer_read_counter(&clksrc, 1);
5a3a388f	283
3d05a3e8 TL	284	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
	285	}
	286
	287	/* Setup free-running counter for clocksource */
	288	static void __init omap2_gp_clocksource_init(int gptimer_id,
	289	const char *fck_source)
	290	{
	291	int res;
	292
	293	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	294	BUG_ON(res);
5a3a388f	295
3d05a3e8 TL	296	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
3d05a3e8 TL	297	gptimer_id, clksrc.rate);
5a3a388f	298
ee17f114	299	__omap_dm_timer_load_start(&clksrc,
e9d0b97e	300	OMAP_TIMER_CTRL_ST \| OMAP_TIMER_CTRL_AR, 0, 1);
3d05a3e8	301	init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
cbc94380	302
3d05a3e8 TL	303	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
	304	pr_err("Could not register clocksource %s\n",
	305	clocksource_gpt.name);
5a3a388f KH	306	}
	307	#endif
	308
3d05a3e8 TL	309	#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
3d05a3e8 TL	310	clksrc_nr, clksrc_src) \
e74984e4 TL	311	static void __init omap##name##_timer_init(void) \
e74984e4 TL	312	{ \
aa561889	313	omap2_gp_clockevent_init((clkev_nr), clkev_src); \
3d05a3e8	314	omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
e74984e4 TL	315	}
	316
	317	#define OMAP_SYS_TIMER(name) \
	318	struct sys_timer omap##name##_timer = { \
	319	.init = omap##name##_timer_init, \
	320	};
	321
	322	#ifdef CONFIG_ARCH_OMAP2
3d05a3e8	323	OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
e74984e4 TL	324	OMAP_SYS_TIMER(2)
	325	#endif
	326
	327	#ifdef CONFIG_ARCH_OMAP3
3d05a3e8	328	OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
e74984e4	329	OMAP_SYS_TIMER(3)
3d05a3e8 TL	330	OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
3d05a3e8 TL	331	2, OMAP3_MPU_SOURCE)
e74984e4 TL	332	OMAP_SYS_TIMER(3_secure)
	333	#endif
	334
	335	#ifdef CONFIG_ARCH_OMAP4
	336	static void __init omap4_timer_init(void)
5a3a388f	337	{
39e1d4c1	338	#ifdef CONFIG_LOCAL_TIMERS
e74984e4 TL	339	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
e74984e4 TL	340	BUG_ON(!twd_base);
39e1d4c1	341	#endif
aa561889	342	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
3d05a3e8	343	omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
1dbae815	344	}
e74984e4 TL	345	OMAP_SYS_TIMER(4)
e74984e4 TL	346	#endif
c345c8b0 TKD	347
	348	/**
	349	* omap2_dm_timer_set_src - change the timer input clock source
	350	* @pdev: timer platform device pointer
	351	* @source: array index of parent clock source
	352	*/
	353	static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
	354	{
	355	int ret;
	356	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
	357	struct clk fclk, parent;
	358	char *parent_name = NULL;
	359
	360	fclk = clk_get(&pdev->dev, "fck");
	361	if (IS_ERR_OR_NULL(fclk)) {
	362	dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
	363	__func__, __LINE__);
	364	return -EINVAL;
	365	}
	366
	367	switch (source) {
	368	case OMAP_TIMER_SRC_SYS_CLK:
	369	parent_name = "sys_ck";
	370	break;
	371
	372	case OMAP_TIMER_SRC_32_KHZ:
	373	parent_name = "32k_ck";
	374	break;
	375
	376	case OMAP_TIMER_SRC_EXT_CLK:
	377	if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
	378	parent_name = "alt_ck";
	379	break;
	380	}
	381	dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
	382	__func__, __LINE__);
	383	clk_put(fclk);
	384	return -EINVAL;
	385	}
	386
	387	parent = clk_get(&pdev->dev, parent_name);
	388	if (IS_ERR_OR_NULL(parent)) {
	389	dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
	390	__func__, __LINE__, parent_name);
	391	clk_put(fclk);
	392	return -EINVAL;
	393	}
	394
	395	ret = clk_set_parent(fclk, parent);
	396	if (IS_ERR_VALUE(ret)) {
	397	dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
	398	__func__, parent_name);
	399	ret = -EINVAL;
	400	}
	401
	402	clk_put(parent);
	403	clk_put(fclk);
	404
	405	return ret;
	406	}
	407
	408	struct omap_device_pm_latency omap2_dmtimer_latency[] = {
	409	{
	410	.deactivate_func = omap_device_idle_hwmods,
411	.activate_func = omap_device_enable_hwmods,
412	.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
413	},
414	};
415
416	/**
417	* omap_timer_init - build and register timer device with an
418	* associated timer hwmod
419	* @oh: timer hwmod pointer to be used to build timer device
420	* @user: parameter that can be passed from calling hwmod API
421	*
422	* Called by omap_hwmod_for_each_by_class to register each of the timer
423	* devices present in the system. The number of timer devices is known
424	* by parsing through the hwmod database for a given class name. At the
425	* end of function call memory is allocated for timer device and it is
426	* registered to the framework ready to be proved by the driver.
427	*/
428	static int __init omap_timer_init(struct omap_hwmod oh, void unused)
429	{
430	int id;
431	int ret = 0;
432	char *name = "omap_timer";
433	struct dmtimer_platform_data *pdata;
434	struct omap_device *od;
435	struct omap_timer_capability_dev_attr *timer_dev_attr;
436
437	pr_debug("%s: %s\n", __func__, oh->name);
438
439	/* on secure device, do not register secure timer */
440	timer_dev_attr = oh->dev_attr;
441	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
442	if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
443	return ret;
444
445	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
446	if (!pdata) {
447	pr_err("%s: No memory for [%s]\n", __func__, oh->name);
448	return -ENOMEM;
449	}
450
451	/*
452	* Extract the IDs from name field in hwmod database
453	* and use the same for constructing ids' for the
454	* timer devices. In a way, we are avoiding usage of
455	* static variable witin the function to do the same.
456	* CAUTION: We have to be careful and make sure the
457	* name in hwmod database does not change in which case
458	* we might either make corresponding change here or
459	* switch back static variable mechanism.
460	*/
461	sscanf(oh->name, "timer%2d", &id);
462
463	pdata->set_timer_src = omap2_dm_timer_set_src;
464	pdata->timer_ip_version = oh->class->rev;
465
466	od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
467	omap2_dmtimer_latency,
468	ARRAY_SIZE(omap2_dmtimer_latency),
469	0);
470
471	if (IS_ERR(od)) {
472	pr_err("%s: Can't build omap_device for %s: %s.\n",
473	__func__, name, oh->name);
474	ret = -EINVAL;
475	}
476
477	kfree(pdata);
478
479	return ret;
480	}