[linux-2.6-block.git] / arch / arm / mach-omap2 / timer.c

/*
 * linux/arch/arm/mach-omap2/timer.c
 *
 * OMAP2 GP timer support.
 *
 * Copyright (C) 2009 Nokia Corporation
 *
 * Update to use new clocksource/clockevent layers
 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
 * Copyright (C) 2007 MontaVista Software, Inc.
 *
 * Original driver:
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *         Juha Yrjölä <juha.yrjola@nokia.com>
 * OMAP Dual-mode timer framework support by Timo Teras
 *
 * Some parts based off of TI's 24xx code:
 *
 * Copyright (C) 2004-2009 Texas Instruments, Inc.
 *
 * Roughly modelled after the OMAP1 MPU timer code.
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/slab.h>
#include <linux/of.h>

#include <asm/mach/time.h>
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>

#include <asm/arch_timer.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/dmtimer.h>
#include <plat/omap-pm.h>

#include "soc.h"
#include "common.h"
#include "powerdomain.h"

/* Parent clocks, eventually these will come from the clock framework */

#define OMAP2_MPU_SOURCE	"sys_ck"
#define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
#define OMAP4_MPU_SOURCE	"sys_clkin_ck"
#define OMAP2_32K_SOURCE	"func_32k_ck"
#define OMAP3_32K_SOURCE	"omap_32k_fck"
#define OMAP4_32K_SOURCE	"sys_32k_ck"

#ifdef CONFIG_OMAP_32K_TIMER
#define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER	12
#else
#define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER	1
#endif

#define REALTIME_COUNTER_BASE				0x48243200
#define INCREMENTER_NUMERATOR_OFFSET			0x10
#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET		0x14
#define NUMERATOR_DENUMERATOR_MASK			0xfffff000

/* Clockevent code */

static struct omap_dm_timer clkev;
static struct clock_event_device clockevent_gpt;

static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_gpt;

	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction omap2_gp_timer_irq = {
	.name		= "gp_timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= omap2_gp_timer_interrupt,
};

static int omap2_gp_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
						0xffffffff - cycles, 1);

	return 0;
}

static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 period;

	__omap_dm_timer_stop(&clkev, 1, clkev.rate);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		period = clkev.rate / HZ;
		period -= 1;
		/* Looks like we need to first set the load value separately */
		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
					0xffffffff - period, 1);
		__omap_dm_timer_load_start(&clkev,
					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
						0xffffffff - period, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device clockevent_gpt = {
	.name		= "gp_timer",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.rating		= 300,
	.set_next_event	= omap2_gp_timer_set_next_event,
	.set_mode	= omap2_gp_timer_set_mode,
};

static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
						int gptimer_id,
						const char *fck_source)
{
	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
	struct omap_hwmod *oh;
	struct resource irq_rsrc, mem_rsrc;
	size_t size;
	int res = 0;
	int r;

	sprintf(name, "timer%d", gptimer_id);
	omap_hwmod_setup_one(name);
	oh = omap_hwmod_lookup(name);
	if (!oh)
		return -ENODEV;

	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
	if (r)
		return -ENXIO;
	timer->irq = irq_rsrc.start;

	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
	if (r)
		return -ENXIO;
	timer->phys_base = mem_rsrc.start;
	size = mem_rsrc.end - mem_rsrc.start;

	/* Static mapping, never released */
	timer->io_base = ioremap(timer->phys_base, size);
	if (!timer->io_base)
		return -ENXIO;

	/* After the dmtimer is using hwmod these clocks won't be needed */
	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
	if (IS_ERR(timer->fclk))
		return -ENODEV;

	omap_hwmod_enable(oh);

	if (omap_dm_timer_reserve_systimer(gptimer_id))
		return -ENODEV;

	if (gptimer_id != 12) {
		struct clk *src;

		src = clk_get(NULL, fck_source);
		if (IS_ERR(src)) {
			res = -EINVAL;
		} else {
			res = __omap_dm_timer_set_source(timer->fclk, src);
			if (IS_ERR_VALUE(res))
				pr_warning("%s: timer%i cannot set source\n",
						__func__, gptimer_id);
			clk_put(src);
		}
	}
	__omap_dm_timer_init_regs(timer);
	__omap_dm_timer_reset(timer, 1, 1);
	timer->posted = 1;

	timer->rate = clk_get_rate(timer->fclk);

	timer->reserved = 1;

	return res;
}

static void __init omap2_gp_clockevent_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
	BUG_ON(res);

	omap2_gp_timer_irq.dev_id = &clkev;
	setup_irq(clkev.irq, &omap2_gp_timer_irq);

	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);

	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
				     clockevent_gpt.shift);
	clockevent_gpt.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	clockevent_gpt.min_delta_ns =
		clockevent_delta2ns(3, &clockevent_gpt);
		/* Timer internal resynch latency. */

	clockevent_gpt.cpumask = cpu_possible_mask;
	clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
	clockevents_register_device(&clockevent_gpt);

	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
		gptimer_id, clkev.rate);
}

/* Clocksource code */
static struct omap_dm_timer clksrc;
static bool use_gptimer_clksrc;

/*
 * clocksource
 */
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
}

static struct clocksource clocksource_gpt = {
	.name		= "gp_timer",
	.rating		= 300,
	.read		= clocksource_read_cycles,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static u32 notrace dmtimer_read_sched_clock(void)
{
	if (clksrc.reserved)
		return __omap_dm_timer_read_counter(&clksrc, 1);

	return 0;
}

#ifdef CONFIG_OMAP_32K_TIMER
/* Setup free-running counter for clocksource */
static int __init omap2_sync32k_clocksource_init(void)
{
	int ret;
	struct omap_hwmod *oh;
	void __iomem *vbase;
	const char *oh_name = "counter_32k";

	/*
	 * First check hwmod data is available for sync32k counter
	 */
	oh = omap_hwmod_lookup(oh_name);
	if (!oh || oh->slaves_cnt == 0)
		return -ENODEV;

	omap_hwmod_setup_one(oh_name);

	vbase = omap_hwmod_get_mpu_rt_va(oh);
	if (!vbase) {
		pr_warn("%s: failed to get counter_32k resource\n", __func__);
		return -ENXIO;
	}

	ret = omap_hwmod_enable(oh);
	if (ret) {
		pr_warn("%s: failed to enable counter_32k module (%d)\n",
							__func__, ret);
		return ret;
	}

	ret = omap_init_clocksource_32k(vbase);
	if (ret) {
		pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
							__func__, ret);
		omap_hwmod_idle(oh);
	}

	return ret;
}
#else
static inline int omap2_sync32k_clocksource_init(void)
{
	return -ENODEV;
}
#endif

static void __init omap2_gptimer_clocksource_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	BUG_ON(res);

	__omap_dm_timer_load_start(&clksrc,
			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);

	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
		pr_err("Could not register clocksource %s\n",
			clocksource_gpt.name);
	else
		pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
			gptimer_id, clksrc.rate);
}

static void __init omap2_clocksource_init(int gptimer_id,
						const char *fck_source)
{
	/*
	 * First give preference to kernel parameter configuration
	 * by user (clocksource="gp_timer").
	 *
	 * In case of missing kernel parameter for clocksource,
	 * first check for availability for 32k-sync timer, in case
	 * of failure in finding 32k_counter module or registering
	 * it as clocksource, execution will fallback to gp-timer.
	 */
	if (use_gptimer_clksrc == true)
		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
	else if (omap2_sync32k_clocksource_init())
		/* Fall back to gp-timer code */
		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
}

#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
/*
 * The realtime counter also called master counter, is a free-running
 * counter, which is related to real time. It produces the count used
 * by the CPU local timer peripherals in the MPU cluster. The timer counts
 * at a rate of 6.144 MHz. Because the device operates on different clocks
 * in different power modes, the master counter shifts operation between
 * clocks, adjusting the increment per clock in hardware accordingly to
 * maintain a constant count rate.
 */
static void __init realtime_counter_init(void)
{
	void __iomem *base;
	static struct clk *sys_clk;
	unsigned long rate;
	unsigned int reg, num, den;

	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
	if (!base) {
		pr_err("%s: ioremap failed\n", __func__);
		return;
	}
	sys_clk = clk_get(NULL, "sys_clkin_ck");
	if (IS_ERR(sys_clk)) {
		pr_err("%s: failed to get system clock handle\n", __func__);
		iounmap(base);
		return;
	}

	rate = clk_get_rate(sys_clk);
	/* Numerator/denumerator values refer TRM Realtime Counter section */
	switch (rate) {
	case 1200000:
		num = 64;
		den = 125;
		break;
	case 1300000:
		num = 768;
		den = 1625;
		break;
	case 19200000:
		num = 8;
		den = 25;
		break;
	case 2600000:
		num = 384;
		den = 1625;
		break;
	case 2700000:
		num = 256;
		den = 1125;
		break;
	case 38400000:
	default:
		/* Program it for 38.4 MHz */
		num = 4;
		den = 25;
		break;
	}

	/* Program numerator and denumerator registers */
	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
			NUMERATOR_DENUMERATOR_MASK;
	reg |= num;
	__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);

	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
			NUMERATOR_DENUMERATOR_MASK;
	reg |= den;
	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);

	iounmap(base);
}
#else
static inline void __init realtime_counter_init(void)
{}
#endif

#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
				clksrc_nr, clksrc_src)			\
static void __init omap##name##_timer_init(void)			\
{									\
	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
	omap2_clocksource_init((clksrc_nr), clksrc_src);		\
}

#define OMAP_SYS_TIMER(name)						\
struct sys_timer omap##name##_timer = {					\
	.init	= omap##name##_timer_init,				\
};

#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER(2)
#endif

#ifdef CONFIG_ARCH_OMAP3
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
			2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3_secure)
#endif

#ifdef CONFIG_SOC_AM33XX
OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
OMAP_SYS_TIMER(3_am33xx)
#endif

#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
			      OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
#endif

static void __init omap4_timer_init(void)
{
	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
#ifdef CONFIG_LOCAL_TIMERS
	/* Local timers are not supprted on OMAP4430 ES1.0 */
	if (omap_rev() != OMAP4430_REV_ES1_0) {
		int err;

		if (of_have_populated_dt()) {
			twd_local_timer_of_register();
			return;
		}

		err = twd_local_timer_register(&twd_local_timer);
		if (err)
			pr_err("twd_local_timer_register failed %d\n", err);
	}
#endif
}
OMAP_SYS_TIMER(4)
#endif

#ifdef CONFIG_SOC_OMAP5
static void __init omap5_timer_init(void)
{
	int err;

	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
	realtime_counter_init();

	err = arch_timer_of_register();
	if (err)
		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
}
OMAP_SYS_TIMER(5)
#endif

/**
 * omap_timer_init - build and register timer device with an
 * associated timer hwmod
 * @oh:	timer hwmod pointer to be used to build timer device
 * @user:	parameter that can be passed from calling hwmod API
 *
 * Called by omap_hwmod_for_each_by_class to register each of the timer
 * devices present in the system. The number of timer devices is known
 * by parsing through the hwmod database for a given class name. At the
 * end of function call memory is allocated for timer device and it is
 * registered to the framework ready to be proved by the driver.
 */
static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
{
	int id;
	int ret = 0;
	char *name = "omap_timer";
	struct dmtimer_platform_data *pdata;
	struct platform_device *pdev;
	struct omap_timer_capability_dev_attr *timer_dev_attr;

	pr_debug("%s: %s\n", __func__, oh->name);

	/* on secure device, do not register secure timer */
	timer_dev_attr = oh->dev_attr;
	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
			return ret;

	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	if (!pdata) {
		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
		return -ENOMEM;
	}

	/*
	 * Extract the IDs from name field in hwmod database
	 * and use the same for constructing ids' for the
	 * timer devices. In a way, we are avoiding usage of
	 * static variable witin the function to do the same.
	 * CAUTION: We have to be careful and make sure the
	 * name in hwmod database does not change in which case
	 * we might either make corresponding change here or
	 * switch back static variable mechanism.
	 */
	sscanf(oh->name, "timer%2d", &id);

	if (timer_dev_attr)
		pdata->timer_capability = timer_dev_attr->timer_capability;

	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
				 NULL, 0, 0);

	if (IS_ERR(pdev)) {
		pr_err("%s: Can't build omap_device for %s: %s.\n",
			__func__, name, oh->name);
		ret = -EINVAL;
	}

	kfree(pdata);

	return ret;
}

/**
 * omap2_dm_timer_init - top level regular device initialization
 *
 * Uses dedicated hwmod api to parse through hwmod database for
 * given class name and then build and register the timer device.
 */
static int __init omap2_dm_timer_init(void)
{
	int ret;

	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
	if (unlikely(ret)) {
		pr_err("%s: device registration failed.\n", __func__);
		return -EINVAL;
	}

	return 0;
}
arch_initcall(omap2_dm_timer_init);

/**
 * omap2_override_clocksource - clocksource override with user configuration
 *
 * Allows user to override default clocksource, using kernel parameter
 *   clocksource="gp_timer"	(For all OMAP2PLUS architectures)
 *
 * Note that, here we are using same standard kernel parameter "clocksource=",
 * and not introducing any OMAP specific interface.
 */
static int __init omap2_override_clocksource(char *str)
{
	if (!str)
		return 0;
	/*
	 * For OMAP architecture, we only have two options
	 *    - sync_32k (default)
	 *    - gp_timer (sys_clk based)
	 */
	if (!strcmp(str, "gp_timer"))
		use_gptimer_clksrc = true;

	return 0;
}
early_param("clocksource", omap2_override_clocksource);
Commit	Line	Data
1dbae815	1	/*
0f622e8c	2	* linux/arch/arm/mach-omap2/timer.c
1dbae815 TL	3	*
	4	* OMAP2 GP timer support.
	5	*
f248076c PW	6	* Copyright (C) 2009 Nokia Corporation
f248076c PW	7	*
5a3a388f KH	8	* Update to use new clocksource/clockevent layers
	9	* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
	10	* Copyright (C) 2007 MontaVista Software, Inc.
	11	*
	12	* Original driver:
1dbae815 TL	13	* Copyright (C) 2005 Nokia Corporation
1dbae815 TL	14	* Author: Paul Mundt <paul.mundt@nokia.com>
96de0e25	15	* Juha Yrjölä <juha.yrjola@nokia.com>
77900a2f	16	* OMAP Dual-mode timer framework support by Timo Teras
1dbae815 TL	17	*
	18	* Some parts based off of TI's 24xx code:
	19	*
44169075	20	* Copyright (C) 2004-2009 Texas Instruments, Inc.
1dbae815 TL	21	*
1dbae815 TL	22	* Roughly modelled after the OMAP1 MPU timer code.
44169075	23	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 TL	24	*
	25	* This file is subject to the terms and conditions of the GNU General Public
	26	* License. See the file "COPYING" in the main directory of this archive
	27	* for more details.
	28	*/
	29	#include <linux/init.h>
	30	#include <linux/time.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/err.h>
f8ce2547	33	#include <linux/clk.h>
77900a2f	34	#include <linux/delay.h>
e6687290	35	#include <linux/irq.h>
5a3a388f KH	36	#include <linux/clocksource.h>
5a3a388f KH	37	#include <linux/clockchips.h>
c345c8b0	38	#include <linux/slab.h>
eed0de27	39	#include <linux/of.h>
f8ce2547	40
1dbae815	41	#include <asm/mach/time.h>
a45c983f	42	#include <asm/smp_twd.h>
cbc94380	43	#include <asm/sched_clock.h>
7d7e1eba	44
3c7c5dab	45	#include <asm/arch_timer.h>
2a296c8f	46	#include "omap_hwmod.h"
25c7d49e	47	#include "omap_device.h"
7d7e1eba	48	#include <plat/dmtimer.h>
b481113a TKD	49	#include <plat/omap-pm.h>
b481113a TKD	50
dbc04161	51	#include "soc.h"
7d7e1eba	52	#include "common.h"
b481113a	53	#include "powerdomain.h"
1dbae815	54
aa561889 TL	55	/* Parent clocks, eventually these will come from the clock framework */
	56
	57	#define OMAP2_MPU_SOURCE "sys_ck"
	58	#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
	59	#define OMAP4_MPU_SOURCE "sys_clkin_ck"
	60	#define OMAP2_32K_SOURCE "func_32k_ck"
	61	#define OMAP3_32K_SOURCE "omap_32k_fck"
	62	#define OMAP4_32K_SOURCE "sys_32k_ck"
	63
	64	#ifdef CONFIG_OMAP_32K_TIMER
	65	#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
	66	#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
	67	#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
	68	#define OMAP3_SECURE_TIMER 12
	69	#else
	70	#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
	71	#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
	72	#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
	73	#define OMAP3_SECURE_TIMER 1
	74	#endif
d8328f3b	75
fa6d79d2 SS	76	#define REALTIME_COUNTER_BASE 0x48243200
	77	#define INCREMENTER_NUMERATOR_OFFSET 0x10
	78	#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
	79	#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
	80
aa561889 TL	81	/* Clockevent code */
	82
	83	static struct omap_dm_timer clkev;
5a3a388f	84	static struct clock_event_device clockevent_gpt;
1dbae815	85
0cd61b68	86	static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
1dbae815	87	{
5a3a388f KH	88	struct clock_event_device *evt = &clockevent_gpt;
5a3a388f KH	89
ee17f114	90	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
1dbae815	91
5a3a388f	92	evt->event_handler(evt);
1dbae815 TL	93	return IRQ_HANDLED;
	94	}
	95
	96	static struct irqaction omap2_gp_timer_irq = {
f36921be	97	.name = "gp_timer",
b30fabad	98	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
1dbae815 TL	99	.handler = omap2_gp_timer_interrupt,
	100	};
	101
5a3a388f KH	102	static int omap2_gp_timer_set_next_event(unsigned long cycles,
5a3a388f KH	103	struct clock_event_device *evt)
1dbae815	104	{
ee17f114	105	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
aa561889	106	0xffffffff - cycles, 1);
5a3a388f KH	107
	108	return 0;
	109	}
	110
	111	static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
	112	struct clock_event_device *evt)
	113	{
	114	u32 period;
	115
ee17f114	116	__omap_dm_timer_stop(&clkev, 1, clkev.rate);
5a3a388f KH	117
	118	switch (mode) {
	119	case CLOCK_EVT_MODE_PERIODIC:
aa561889	120	period = clkev.rate / HZ;
5a3a388f	121	period -= 1;
aa561889	122	/* Looks like we need to first set the load value separately */
ee17f114	123	__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
aa561889	124	0xffffffff - period, 1);
ee17f114	125	__omap_dm_timer_load_start(&clkev,
aa561889 TL	126	OMAP_TIMER_CTRL_AR \| OMAP_TIMER_CTRL_ST,
aa561889 TL	127	0xffffffff - period, 1);
5a3a388f KH	128	break;
	129	case CLOCK_EVT_MODE_ONESHOT:
	130	break;
	131	case CLOCK_EVT_MODE_UNUSED:
	132	case CLOCK_EVT_MODE_SHUTDOWN:
	133	case CLOCK_EVT_MODE_RESUME:
	134	break;
	135	}
	136	}
	137
	138	static struct clock_event_device clockevent_gpt = {
f36921be	139	.name = "gp_timer",
5a3a388f KH	140	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
5a3a388f KH	141	.shift = 32,
11d6ec2e	142	.rating = 300,
5a3a388f KH	143	.set_next_event = omap2_gp_timer_set_next_event,
	144	.set_mode = omap2_gp_timer_set_mode,
	145	};
	146
aa561889 TL	147	static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
	148	int gptimer_id,
	149	const char *fck_source)
5a3a388f	150	{
aa561889 TL	151	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
aa561889 TL	152	struct omap_hwmod *oh;
6c0c27fd	153	struct resource irq_rsrc, mem_rsrc;
aa561889 TL	154	size_t size;
aa561889 TL	155	int res = 0;
6c0c27fd	156	int r;
aa561889 TL	157
	158	sprintf(name, "timer%d", gptimer_id);
	159	omap_hwmod_setup_one(name);
	160	oh = omap_hwmod_lookup(name);
	161	if (!oh)
	162	return -ENODEV;
	163
6c0c27fd PW	164	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
	165	if (r)
	166	return -ENXIO;
	167	timer->irq = irq_rsrc.start;
	168
	169	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
	170	if (r)
	171	return -ENXIO;
	172	timer->phys_base = mem_rsrc.start;
	173	size = mem_rsrc.end - mem_rsrc.start;
aa561889 TL	174
	175	/* Static mapping, never released */
	176	timer->io_base = ioremap(timer->phys_base, size);
	177	if (!timer->io_base)
	178	return -ENXIO;
	179
	180	/* After the dmtimer is using hwmod these clocks won't be needed */
ae6df418	181	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
aa561889 TL	182	if (IS_ERR(timer->fclk))
	183	return -ENODEV;
	184
aa561889 TL	185	omap_hwmod_enable(oh);
aa561889 TL	186
b7b4ff76 JH	187	if (omap_dm_timer_reserve_systimer(gptimer_id))
b7b4ff76 JH	188	return -ENODEV;
11a0186f	189
aa561889 TL	190	if (gptimer_id != 12) {
	191	struct clk *src;
	192
	193	src = clk_get(NULL, fck_source);
	194	if (IS_ERR(src)) {
	195	res = -EINVAL;
	196	} else {
	197	res = __omap_dm_timer_set_source(timer->fclk, src);
	198	if (IS_ERR_VALUE(res))
	199	pr_warning("%s: timer%i cannot set source\n",
	200	__func__, gptimer_id);
	201	clk_put(src);
	202	}
	203	}
ee17f114 TL	204	__omap_dm_timer_init_regs(timer);
ee17f114 TL	205	__omap_dm_timer_reset(timer, 1, 1);
aa561889 TL	206	timer->posted = 1;
	207
	208	timer->rate = clk_get_rate(timer->fclk);
1dbae815	209
aa561889	210	timer->reserved = 1;
38698bef	211
aa561889 TL	212	return res;
aa561889 TL	213	}
f248076c	214
aa561889 TL	215	static void __init omap2_gp_clockevent_init(int gptimer_id,
	216	const char *fck_source)
	217	{
	218	int res;
f248076c	219
aa561889 TL	220	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
aa561889 TL	221	BUG_ON(res);
f248076c	222
a032d33b	223	omap2_gp_timer_irq.dev_id = &clkev;
aa561889	224	setup_irq(clkev.irq, &omap2_gp_timer_irq);
5a3a388f	225
ee17f114	226	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
aa561889 TL	227
aa561889 TL	228	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
5a3a388f KH	229	clockevent_gpt.shift);
	230	clockevent_gpt.max_delta_ns =
	231	clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	232	clockevent_gpt.min_delta_ns =
df88acbb AK	233	clockevent_delta2ns(3, &clockevent_gpt);
df88acbb AK	234	/* Timer internal resynch latency. */
5a3a388f	235
11d6ec2e SS	236	clockevent_gpt.cpumask = cpu_possible_mask;
11d6ec2e SS	237	clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
5a3a388f	238	clockevents_register_device(&clockevent_gpt);
aa561889 TL	239
	240	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
	241	gptimer_id, clkev.rate);
5a3a388f KH	242	}
5a3a388f KH	243
f248076c	244	/* Clocksource code */
3d05a3e8	245	static struct omap_dm_timer clksrc;
1fe97c8f	246	static bool use_gptimer_clksrc;
3d05a3e8	247
5a3a388f KH	248	/*
	249	* clocksource
	250	*/
8e19608e	251	static cycle_t clocksource_read_cycles(struct clocksource *cs)
5a3a388f	252	{
ee17f114	253	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
5a3a388f KH	254	}
	255
	256	static struct clocksource clocksource_gpt = {
f36921be	257	.name = "gp_timer",
5a3a388f KH	258	.rating = 300,
	259	.read = clocksource_read_cycles,
	260	.mask = CLOCKSOURCE_MASK(32),
5a3a388f KH	261	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	262	};
	263
2f0778af	264	static u32 notrace dmtimer_read_sched_clock(void)
cbc94380	265	{
3d05a3e8	266	if (clksrc.reserved)
dbc3982a	267	return __omap_dm_timer_read_counter(&clksrc, 1);
5a3a388f	268
2f0778af	269	return 0;
3d05a3e8 TL	270	}
3d05a3e8 TL	271
45caae74	272	#ifdef CONFIG_OMAP_32K_TIMER
3d05a3e8	273	/* Setup free-running counter for clocksource */
1fe97c8f VH	274	static int __init omap2_sync32k_clocksource_init(void)
	275	{
	276	int ret;
	277	struct omap_hwmod *oh;
	278	void __iomem *vbase;
	279	const char *oh_name = "counter_32k";
	280
	281	/*
	282	* First check hwmod data is available for sync32k counter
	283	*/
	284	oh = omap_hwmod_lookup(oh_name);
	285	if (!oh \|\| oh->slaves_cnt == 0)
	286	return -ENODEV;
	287
	288	omap_hwmod_setup_one(oh_name);
	289
	290	vbase = omap_hwmod_get_mpu_rt_va(oh);
	291	if (!vbase) {
	292	pr_warn("%s: failed to get counter_32k resource\n", __func__);
	293	return -ENXIO;
	294	}
	295
	296	ret = omap_hwmod_enable(oh);
	297	if (ret) {
	298	pr_warn("%s: failed to enable counter_32k module (%d)\n",
	299	__func__, ret);
	300	return ret;
	301	}
	302
	303	ret = omap_init_clocksource_32k(vbase);
	304	if (ret) {
	305	pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
	306	__func__, ret);
	307	omap_hwmod_idle(oh);
	308	}
	309
	310	return ret;
	311	}
45caae74 IG	312	#else
	313	static inline int omap2_sync32k_clocksource_init(void)
	314	{
	315	return -ENODEV;
	316	}
	317	#endif
1fe97c8f VH	318
1fe97c8f VH	319	static void __init omap2_gptimer_clocksource_init(int gptimer_id,
3d05a3e8 TL	320	const char *fck_source)
	321	{
	322	int res;
	323
	324	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	325	BUG_ON(res);
5a3a388f	326
ee17f114	327	__omap_dm_timer_load_start(&clksrc,
e9d0b97e	328	OMAP_TIMER_CTRL_ST \| OMAP_TIMER_CTRL_AR, 0, 1);
2f0778af	329	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
cbc94380	330
3d05a3e8 TL	331	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
	332	pr_err("Could not register clocksource %s\n",
	333	clocksource_gpt.name);
1fe97c8f VH	334	else
	335	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
	336	gptimer_id, clksrc.rate);
	337	}
	338
	339	static void __init omap2_clocksource_init(int gptimer_id,
	340	const char *fck_source)
	341	{
	342	/*
	343	* First give preference to kernel parameter configuration
	344	* by user (clocksource="gp_timer").
	345	*
	346	* In case of missing kernel parameter for clocksource,
	347	* first check for availability for 32k-sync timer, in case
	348	* of failure in finding 32k_counter module or registering
	349	* it as clocksource, execution will fallback to gp-timer.
	350	*/
	351	if (use_gptimer_clksrc == true)
	352	omap2_gptimer_clocksource_init(gptimer_id, fck_source);
	353	else if (omap2_sync32k_clocksource_init())
	354	/* Fall back to gp-timer code */
	355	omap2_gptimer_clocksource_init(gptimer_id, fck_source);
5a3a388f	356	}
5a3a388f	357
fa6d79d2 SS	358	#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
	359	/*
	360	* The realtime counter also called master counter, is a free-running
	361	* counter, which is related to real time. It produces the count used
	362	* by the CPU local timer peripherals in the MPU cluster. The timer counts
	363	* at a rate of 6.144 MHz. Because the device operates on different clocks
	364	* in different power modes, the master counter shifts operation between
	365	* clocks, adjusting the increment per clock in hardware accordingly to
	366	* maintain a constant count rate.
	367	*/
	368	static void __init realtime_counter_init(void)
	369	{
	370	void __iomem *base;
	371	static struct clk *sys_clk;
	372	unsigned long rate;
	373	unsigned int reg, num, den;
	374
	375	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
	376	if (!base) {
	377	pr_err("%s: ioremap failed\n", __func__);
	378	return;
	379	}
	380	sys_clk = clk_get(NULL, "sys_clkin_ck");
533b2981	381	if (IS_ERR(sys_clk)) {
fa6d79d2 SS	382	pr_err("%s: failed to get system clock handle\n", __func__);
	383	iounmap(base);
	384	return;
	385	}
	386
	387	rate = clk_get_rate(sys_clk);
	388	/* Numerator/denumerator values refer TRM Realtime Counter section */
	389	switch (rate) {
	390	case 1200000:
	391	num = 64;
	392	den = 125;
	393	break;
	394	case 1300000:
	395	num = 768;
	396	den = 1625;
	397	break;
	398	case 19200000:
	399	num = 8;
	400	den = 25;
	401	break;
	402	case 2600000:
	403	num = 384;
	404	den = 1625;
	405	break;
	406	case 2700000:
	407	num = 256;
	408	den = 1125;
	409	break;
	410	case 38400000:
	411	default:
	412	/* Program it for 38.4 MHz */
	413	num = 4;
	414	den = 25;
	415	break;
	416	}
	417
	418	/* Program numerator and denumerator registers */
	419	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
	420	NUMERATOR_DENUMERATOR_MASK;
	421	reg \|= num;
	422	__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
	423
	424	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
	425	NUMERATOR_DENUMERATOR_MASK;
	426	reg \|= den;
	427	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
	428
	429	iounmap(base);
	430	}
	431	#else
	432	static inline void __init realtime_counter_init(void)
	433	{}
	434	#endif
	435
3d05a3e8 TL	436	#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
3d05a3e8 TL	437	clksrc_nr, clksrc_src) \
e74984e4 TL	438	static void __init omap##name##_timer_init(void) \
e74984e4 TL	439	{ \
aa561889	440	omap2_gp_clockevent_init((clkev_nr), clkev_src); \
1fe97c8f	441	omap2_clocksource_init((clksrc_nr), clksrc_src); \
e74984e4 TL	442	}
	443
	444	#define OMAP_SYS_TIMER(name) \
	445	struct sys_timer omap##name##_timer = { \
	446	.init = omap##name##_timer_init, \
	447	};
	448
	449	#ifdef CONFIG_ARCH_OMAP2
3d05a3e8	450	OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
e74984e4 TL	451	OMAP_SYS_TIMER(2)
	452	#endif
	453
	454	#ifdef CONFIG_ARCH_OMAP3
3d05a3e8	455	OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
e74984e4	456	OMAP_SYS_TIMER(3)
3d05a3e8 TL	457	OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
3d05a3e8 TL	458	2, OMAP3_MPU_SOURCE)
e74984e4 TL	459	OMAP_SYS_TIMER(3_secure)
	460	#endif
	461
08f30989 AM	462	#ifdef CONFIG_SOC_AM33XX
	463	OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
	464	OMAP_SYS_TIMER(3_am33xx)
	465	#endif
	466
e74984e4	467	#ifdef CONFIG_ARCH_OMAP4
39e1d4c1	468	#ifdef CONFIG_LOCAL_TIMERS
a45c983f	469	static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
7d7e1eba	470	OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
39e1d4c1	471	#endif
a45c983f MZ	472
	473	static void __init omap4_timer_init(void)
	474	{
aa561889	475	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
1fe97c8f	476	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
a45c983f MZ	477	#ifdef CONFIG_LOCAL_TIMERS
	478	/* Local timers are not supprted on OMAP4430 ES1.0 */
	479	if (omap_rev() != OMAP4430_REV_ES1_0) {
	480	int err;
	481
eed0de27 SS	482	if (of_have_populated_dt()) {
	483	twd_local_timer_of_register();
	484	return;
	485	}
	486
a45c983f MZ	487	err = twd_local_timer_register(&twd_local_timer);
	488	if (err)
	489	pr_err("twd_local_timer_register failed %d\n", err);
	490	}
	491	#endif
1dbae815	492	}
e74984e4 TL	493	OMAP_SYS_TIMER(4)
e74984e4 TL	494	#endif
c345c8b0	495
37b3280d	496	#ifdef CONFIG_SOC_OMAP5
fa6d79d2 SS	497	static void __init omap5_timer_init(void)
fa6d79d2 SS	498	{
3c7c5dab SS	499	int err;
3c7c5dab SS	500
fa6d79d2 SS	501	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
	502	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
	503	realtime_counter_init();
3c7c5dab SS	504
	505	err = arch_timer_of_register();
	506	if (err)
	507	pr_err("%s: arch_timer_register failed %d\n", __func__, err);
fa6d79d2	508	}
37b3280d S	509	OMAP_SYS_TIMER(5)
	510	#endif
	511
c345c8b0 TKD	512	/**
	513	* omap_timer_init - build and register timer device with an
	514	* associated timer hwmod
	515	* @oh: timer hwmod pointer to be used to build timer device
	516	* @user: parameter that can be passed from calling hwmod API
	517	*
	518	* Called by omap_hwmod_for_each_by_class to register each of the timer
	519	* devices present in the system. The number of timer devices is known
	520	* by parsing through the hwmod database for a given class name. At the
	521	* end of function call memory is allocated for timer device and it is
	522	* registered to the framework ready to be proved by the driver.
	523	*/
	524	static int __init omap_timer_init(struct omap_hwmod oh, void unused)
	525	{
	526	int id;
	527	int ret = 0;
	528	char *name = "omap_timer";
	529	struct dmtimer_platform_data *pdata;
c541c15f	530	struct platform_device *pdev;
c345c8b0 TKD	531	struct omap_timer_capability_dev_attr *timer_dev_attr;
	532
	533	pr_debug("%s: %s\n", __func__, oh->name);
	534
	535	/* on secure device, do not register secure timer */
	536	timer_dev_attr = oh->dev_attr;
	537	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
	538	if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
	539	return ret;
	540
	541	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	542	if (!pdata) {
	543	pr_err("%s: No memory for [%s]\n", __func__, oh->name);
	544	return -ENOMEM;
	545	}
	546
	547	/*
	548	* Extract the IDs from name field in hwmod database
	549	* and use the same for constructing ids' for the
	550	* timer devices. In a way, we are avoiding usage of
	551	* static variable witin the function to do the same.
	552	* CAUTION: We have to be careful and make sure the
	553	* name in hwmod database does not change in which case
	554	* we might either make corresponding change here or
	555	* switch back static variable mechanism.
	556	*/
	557	sscanf(oh->name, "timer%2d", &id);
	558
d1c1691b JH	559	if (timer_dev_attr)
d1c1691b JH	560	pdata->timer_capability = timer_dev_attr->timer_capability;
0dad9fae	561
c541c15f	562	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
c16ae1e6	563	NULL, 0, 0);
c345c8b0	564
c541c15f	565	if (IS_ERR(pdev)) {
c345c8b0 TKD	566	pr_err("%s: Can't build omap_device for %s: %s.\n",
	567	__func__, name, oh->name);
	568	ret = -EINVAL;
	569	}
	570
	571	kfree(pdata);
	572
	573	return ret;
	574	}
3392cdd3 TKD	575
	576	/**
	577	* omap2_dm_timer_init - top level regular device initialization
	578	*
	579	* Uses dedicated hwmod api to parse through hwmod database for
	580	* given class name and then build and register the timer device.
	581	*/
	582	static int __init omap2_dm_timer_init(void)
	583	{
	584	int ret;
	585
	586	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
	587	if (unlikely(ret)) {
	588	pr_err("%s: device registration failed.\n", __func__);
	589	return -EINVAL;
	590	}
	591
	592	return 0;
	593	}
	594	arch_initcall(omap2_dm_timer_init);
1fe97c8f VH	595
	596	/**
	597	* omap2_override_clocksource - clocksource override with user configuration
	598	*
	599	* Allows user to override default clocksource, using kernel parameter
	600	* clocksource="gp_timer" (For all OMAP2PLUS architectures)
	601	*
	602	* Note that, here we are using same standard kernel parameter "clocksource=",
	603	* and not introducing any OMAP specific interface.
	604	*/
	605	static int __init omap2_override_clocksource(char *str)
	606	{
	607	if (!str)
	608	return 0;
	609	/*
	610	* For OMAP architecture, we only have two options
	611	* - sync_32k (default)
	612	* - gp_timer (sys_clk based)
	613	*/
	614	if (!strcmp(str, "gp_timer"))
	615	use_gptimer_clksrc = true;
	616
	617	return 0;
	618	}
	619	early_param("clocksource", omap2_override_clocksource);